CN107403610B - A kind of scanning GOA circuit - Google Patents
A kind of scanning GOA circuit Download PDFInfo
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- CN107403610B CN107403610B CN201710860740.6A CN201710860740A CN107403610B CN 107403610 B CN107403610 B CN 107403610B CN 201710860740 A CN201710860740 A CN 201710860740A CN 107403610 B CN107403610 B CN 107403610B
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- 239000010409 thin film Substances 0.000 claims abstract description 231
- 239000010408 film Substances 0.000 claims abstract description 75
- 239000003990 capacitor Substances 0.000 claims abstract description 39
- 239000013078 crystal Substances 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 238000004088 simulation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
Abstract
The present invention provides a kind of scanning GOA circuit comprising: first film transistor, the second thin film transistor (TFT), third thin film transistor (TFT), the 4th thin film transistor (TFT), first capacitor；The first end of first film transistor accesses inverting clock signal, and second end is connect with the first end of the second thin film transistor (TFT), as output end；The grid of third thin film transistor (TFT) accesses scan start signal, and the first end of third thin film transistor (TFT) is connect with the grid of the second thin film transistor (TFT), and the second end of third thin film transistor (TFT) connect with the second end of the second thin film transistor (TFT) and accesses high level signal；The grid of 4th thin film transistor (TFT) connects with source electrode and accesses scan start signal, and drain electrode is connect with the grid of first film transistor；First capacitor is connected in parallel on the second end with the grid of first film transistor and first film transistor, and first end is source electrode, and second end is drain electrode or first end is drain electrode, and second end is source electrode.The present invention can guarantee output end normal output signal.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of scanning GOA circuits.
Background technique
It is aobvious that GOA (Gate Driver on Array, the driving of array substrate row) technology can allow gate driving circuit to be integrated in
Show on panel, can save in this way and the IC (integrated circuit, integrated circuit) of grid potential signal is provided.For soft
Property OLED display, due to needing the threshold voltage and mobility of compensation film transistor, thus need more grid signals,
In this way, providing grid signal from exterior I C becomes extremely difficult.The stability of GOA is also very for display panel simultaneously
It is important.In order to improve display image quality, each company puts forward a variety of GOA circuits, and Fig. 1 is a kind of GOA circuit announced, and Fig. 2 is
The waveform diagram of CK (clock signal), XCK (inverting clock signal), STV (scan start signal), the operation of the GOA circuit
It is as follows:
Stage 1:CK (clock signal) is L (low level), and XCK (inverting clock signal) is H (high level), and STV (open by scanning
Dynamic signal) it is L (low level), M3, M4, M5, M10, M11, M12 are opened, and the grid voltage of thin film transistor (TFT) M1 is L+Vth, Vth
For the threshold voltage of M2, the grid voltage of thin film transistor (TFT) M3 is L, therefore M1, M3 are opened, and the grid voltage of M2 is H, therefore M2
It closes.Output end OUT output is XCK, is high level.
Stage 2:CK is H, XCK L, STV H, thin film transistor (TFT) M10, M11, M12, M6, M7 opening, M3, M4, M5, M8
It closes.Because the grid voltage of the effect of capacitor C1, C2, M1 and M2 keep voltage status on last stage.One end of C1 and M1's
Grid is connected, and when the other end is connected with VGH, at stage 2, output end OUT should export XCK signal, but due to the grid of M1 electricity
Pressure is L+Vth, therefore M1 has the incomplete risk of opening, be easy to cause output end OUT output voltage to be greater than L, thus can not be complete
The whole normal XCK signal of output.And during GOA grades of biographies, the output end OUT of level-one GOA circuit exports abnormal wave
Shape signal, will lead to subsequent GOA circuit can not output waveform, break down so as to cause subsequent GOA circuit output.Together
When, the signal of output end OUT output becomes L from H, and the grid voltage of M2 can be caused to be pulled low because of the parasitic capacitance effect of M2,
So that M2 and M9 is accidentally opened, M2, which is opened, causes the output end of M2 to export high level signal VGH, to cause output end OUT defeated
It makes mistake；M9 is opened, and the current potential in Fig. 1 at PD is caused to be raised, so that M1 be closed, the output of output end OUT is caused to be sent out
Raw failure.
Stage 3:CK is L, and XCK H, STV H, M7, M8, M9, M12 are opened, so that the grid voltage of M2 is L+Vth, M1
Grid voltage be H, then M2 open, M1 close, OUT terminal export VGH, be high level.
When above-mentioned GOA circuit is used in series, the STV signal of the 1st grade of GOA circuit access is as shown in Fig. 2, next stage
The grid of M4 in GOA circuit is connect with the output end OUT of upper level GOA circuit.It can be seen that the 1st grade of GOA from Fig. 3 a, 3b
Circuit can not export correct SCAN (scanning signal) waveform, because in the stage 2, the voltage of PD point can not be drawn lower, make CK
Or XCK signal waveform can not be exported completely.It, can be because parasitic capacitance effect makes PU simultaneously when the parasitic capacitance of M2 is larger
Point is pulled low at stage 2, and M9 is opened, so that PD point voltage is raised, M1 grid voltage is excessively high, causes not exporting normal
SCAN waveform.
Summary of the invention
In order to solve the above technical problems, the present invention provides a kind of scanning GOA circuit, it can guarantee that its output end normally exports
Signal does not break down.
A kind of scanning GOA circuit provided by the invention, comprising: first film transistor, the second thin film transistor (TFT), third are thin
Film transistor, the 4th thin film transistor (TFT), first capacitor；
The first end of the first film transistor accesses inverting clock signal, the second end of the first film transistor
It is connect with the first end of second thin film transistor (TFT), and as output end；
The grid of the third thin film transistor (TFT) accesses scan start signal, the first end of the third thin film transistor (TFT) with
The grid of second thin film transistor (TFT) connects, the second end of the third thin film transistor (TFT) and second thin film transistor (TFT)
Second end connection and access high level signal；
The grid of 4th thin film transistor (TFT) connects with source electrode and accesses scan start signal, drains and described first is thin
The grid of film transistor connects；
The both ends of the first capacitor respectively with the grid of the first film transistor and the first film crystal
The second end of pipe connects；
Wherein, first end is source electrode, and second end is drain electrode or first end is drain electrode, and second end is source electrode.
Preferably, further includes: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th film are brilliant
Body pipe；
The grid of 6th thin film transistor (TFT) is connected with source electrode and accesses inverting clock signal, and the 6th film is brilliant
The drain electrode of body pipe is connect with the first end of the grid of the 7th thin film transistor (TFT), the 5th thin film transistor (TFT) respectively；
The grid of 8th thin film transistor (TFT) is connect with the first end of the 7th thin film transistor (TFT) and incoming clock is believed
Number, the first end of the 8th thin film transistor (TFT) is connect with the second end of the 7th thin film transistor (TFT), and the 8th film is brilliant
The second end of body pipe is connect with the first end of the third thin film transistor (TFT)；
The grid of 5th thin film transistor (TFT) connect with the grid of the third thin film transistor (TFT) and accesses sweep start
The second end of signal, the 5th thin film transistor (TFT) is connect with the second end of second thin film transistor (TFT).
Preferably, further includes: the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11st thin film transistor (TFT), the 12nd thin
Film transistor, the second capacitor, third capacitor；
The drain electrode of 4th thin film transistor (TFT) passes through the tenth thin film transistor (TFT) and the first film transistor
The connection of the first end of grid and the 12nd thin film transistor (TFT)；
The grid of tenth thin film transistor (TFT) accesses scan start signal, the first end of the tenth thin film transistor (TFT) with
The drain electrode of 4th thin film transistor (TFT) connects, second end and the first film transistor of the tenth thin film transistor (TFT)
The connection of the first end of grid and the 12nd thin film transistor (TFT)；
The grid of 12nd thin film transistor (TFT) accesses low level signal, and the source electrode of the 12nd thin film transistor (TFT)
It is connect with the other end of drain electrode with the first end of the 9th thin film transistor (TFT), the second end of the 9th thin film transistor (TFT) and institute
State the second end connection of the second thin film transistor (TFT), the grid of the 9th thin film transistor (TFT) and the grid of second thin film transistor (TFT)
Pole connection；
The grid of 11st thin film transistor (TFT) accesses low level signal, the first end of the 11st thin film transistor (TFT)
Scan start signal is accessed, the second end of the 11st thin film transistor (TFT) is connect with the grid of the third thin film transistor (TFT)；
The both ends of second capacitor respectively with the grid and the 9th film crystal of the 9th thin film transistor (TFT)
The second end of pipe connects；
The both ends of the third capacitor are connect with the source electrode and drain electrode of the 9th thin film transistor (TFT) respectively.
It preferably, further include the 4th capacitor；
The both ends of 4th capacitor are connect with the source electrode and drain electrode of the 5th thin film transistor (TFT) respectively.
It preferably, further include the 13rd thin film transistor (TFT)；
The grid of 13rd thin film transistor (TFT) is connect with the grid of the first film transistor respectively, and the described tenth
The first end of three thin film transistor (TFT)s accesses high level signal, the second end of the 13rd thin film transistor (TFT) and second film
The grid of transistor connects.
Preferably, the first film transistor, the second thin film transistor (TFT), third thin film transistor (TFT), the 4th film crystal
Pipe, the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT), the 9th film crystal
Pipe, the tenth thin film transistor (TFT), the 11st thin film transistor (TFT), the 12nd thin film transistor (TFT), the 13rd thin film transistor (TFT) are p-type
Metal-oxide-semiconductor.
Preferably, high level signal and low level signal are direct current signal.
Preferably, scan start signal on startup between be low level, clock signal first half period be low level,
And the starting time and first half period are corresponding.
The invention has the following beneficial effects: the both ends of first capacitor respectively with the grid of first film transistor
And the second end connection of first film transistor.Because first capacitor be directly parallel in first film transistor grid and
In the second end of first film transistor, when stage 2 shown in Fig. 2, first capacitor can maintain on last stage i.e. stage 1
Voltage status is low level L, and along with the parasitic capacitance of first film transistor, the grid voltage of first film transistor is small
In 2L, so that first film transistor fully opens, output end exports the corresponding low level signal of inverting clock signal.Meanwhile
First capacitor is directly parallel in the grid of first film transistor and the second end of first film transistor, output end by
When high level H becomes low level L, prevent because the grid voltage that drags down of parasitic capacitance, open and draw high current potential at PD, close
First film transistor.Therefore, the output end of GOA circuit can be with normal output signal.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the GOA circuit diagram in background technique provided by the invention.
Fig. 2 is clock signal provided by the invention, the waveform diagram of inverting clock signal, scan start signal.
Fig. 3 a be it is provided by the invention selection 20 background techniques in GOA circuit be connected in series after, obtain 1~
The simulation result diagram of 4 grades of GOA circuit outputs.
Fig. 3 b be it is provided by the invention selection 20 background techniques in GOA circuit be connected in series after, obtain 16
The simulation result diagram of~20 grades of GOA circuit outputs.
Fig. 4 is scanning GOA circuit diagram provided by the invention.
Fig. 5 a is 1~4 grade of obtained GOA electricity after 20 scanning GOA circuits of selection provided by the invention are connected in series
The simulation result diagram of road output.
Fig. 5 b is 16~20 grades of obtained GOA after 20 scanning GOA circuits of selection provided by the invention are connected in series
The simulation result diagram of circuit output.
Specific embodiment
The present invention provides a kind of scanning GOA circuit, as shown in figure 4, scanning GOA circuit includes: first film transistor
M1, the second thin film transistor (TFT) M2, third thin film transistor (TFT) M3, the 4th thin film transistor (TFT) M4, first capacitor C1.
The first end of first film transistor M1 accesses inverting clock signal XCK, the second end of first film transistor M1
It is connect with the first end of the second thin film transistor (TFT) M2, and as output end.
The grid of third thin film transistor (TFT) M3 accesses scan start signal STV, the first end of third thin film transistor (TFT) M3 with
The grid of second thin film transistor (TFT) M2 connects, the second end of the second end of third thin film transistor (TFT) M3 and the second thin film transistor (TFT) M2
Connection and access high level signal VGH.
The grid of 4th thin film transistor (TFT) M4 connects with source electrode and accesses scan start signal STV, drain electrode and the first film
The grid of transistor M1 connects.
The both ends of first capacitor C1 respectively with the grid of first film transistor M1 and first film transistor M1
The connection of two ends.
Wherein, first end is the source electrode of thin film transistor (TFT), and second end is the drain electrode of thin film transistor (TFT) or first end is thin
The drain electrode of film transistor, second end are the source electrode of thin film transistor (TFT).
Because first capacitor C1 is directly parallel in the grid and first film transistor M1 of first film transistor M1
In second end, when stage 2 shown in Fig. 2, first capacitor C1 can maintain on last stage the voltage status in i.e. stage 1, be low
Level L, along with the parasitic capacitance of first film transistor M1, the grid voltage of first film transistor M1 is less than 2L, so that
First film transistor M1 is fully opened, and output end OUT exports the corresponding low level signal of inverting clock signal XCK.Meanwhile the
One capacitor C1 is directly parallel in the grid of first film transistor M1 and the second end of first film transistor M1, is being exported
When end OUT becomes low level L from high level H, prevent from opening M9 because the parasitic capacitance of M2 drags down the grid voltage of M2 and drawing high
Current potential at PD closes M1.Therefore, the output end OUT of GOA circuit can be with normal output signal.
Further, scanning GOA circuit further include: the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin
Film transistor M7, the 8th thin film transistor (TFT) M8.
The grid of 6th thin film transistor (TFT) M6 is connected with source electrode and accesses inverting clock signal XCK, the 6th film crystal
The drain electrode of pipe M6 is connect with the first end of the grid of the 7th thin film transistor (TFT) M7, the 5th thin film transistor (TFT) M5 respectively.
The grid of 8th thin film transistor (TFT) M8 is connect with the first end of the 7th thin film transistor (TFT) M7 and incoming clock signal CK,
The first end of 8th thin film transistor (TFT) M8 is connect with the second end of the 7th thin film transistor (TFT) M7, and the second of the 8th thin film transistor (TFT) M8
End is connect with the first end of third thin film transistor (TFT) M3.
The grid of 5th thin film transistor (TFT) M5 connect with the grid of third thin film transistor (TFT) M3 and accesses scan start signal
STV, the second end of the 5th thin film transistor (TFT) M5 are connect with the second end of the second thin film transistor (TFT) M2.
Further, scanning GOA circuit further include: the 9th thin film transistor (TFT) M9, the tenth thin film transistor (TFT) M10, the tenth
One thin film transistor (TFT) M11, the 12nd thin film transistor (TFT) M2, the second capacitor C2, third capacitor C3.
The drain electrode of 4th thin film transistor (TFT) M4 passes through the grid of the tenth thin film transistor (TFT) M10 and first film transistor M1,
And the 12nd thin film transistor (TFT) M12 first end connection.
The grid of tenth thin film transistor (TFT) M10 accesses scan start signal STV, the first end of the tenth thin film transistor (TFT) M10
It is connect with the drain electrode of the 4th thin film transistor (TFT) M4, the second end of the tenth thin film transistor (TFT) M10 and the grid of first film transistor M1
The connection of the first end of pole and the 12nd thin film transistor (TFT) M12.
The grid of 12nd thin film transistor (TFT) M12 accesses low level signal VGL, and the source of the 12nd thin film transistor (TFT) M12
The other end of pole and drain electrode is connect with the first end of the 9th thin film transistor (TFT) M9, the second end and second of the 9th thin film transistor (TFT) M9
The second end of thin film transistor (TFT) M2 connects, and the grid of the 9th thin film transistor (TFT) M9 is connect with the grid of the second thin film transistor (TFT) M2.
The grid of 11st thin film transistor (TFT) M11 accesses low level signal VGL, and the first of the 11st thin film transistor (TFT) M11
It terminates into scan start signal STV, the second end of the 11st thin film transistor (TFT) M11 and the grid of third thin film transistor (TFT) M3 connect
It connects.
The both ends of second capacitor C2 respectively with the grid of the 9th thin film transistor (TFT) M9 and the 9th thin film transistor (TFT) M9
The connection of two ends.Second capacitor C2, because of the parasitic capacitance inside the second thin film transistor (TFT) M2, can lead to avoid in the stage 2
The grid voltage of two thin film transistor (TFT) M2 and the 9th thin film transistor (TFT) M9 is pulled low, so as to cause the second thin film transistor (TFT) M2 and
Nine thin film transistor (TFT) M9 are accidentally opened, and when the 9th thin film transistor (TFT) M9 is opened, be will cause the voltage at PD and are raised, thus
First film transistor M1 is closed, output failure is caused.Therefore, the second capacitor C2 can maintain the second thin film transistor (TFT) M2 and
The grid voltage of nine thin film transistor (TFT) M9 is stablized, and then first film transistor M1 is avoided accidentally to be closed, and maintains output end OUT
Normal output.
The both ends of third capacitor C3 are connect with the source electrode and drain electrode of the 9th thin film transistor (TFT) M9 respectively.Third capacitor C3 can be with
The charge for storing the leakage current release of the 9th thin film transistor (TFT) M9, maintains the 9th thin film transistor (TFT) M9 and the 12nd thin film transistor (TFT)
The current potential of tie point is stablized between M12.
Further, scanning GOA circuit further includes the 4th capacitor C4.The both ends of 4th capacitor C4 respectively with the 5th film
The source electrode and drain electrode of transistor M5 connects.
Further, scanning GOA circuit further includes the 13rd thin film transistor (TFT) M13.The purpose of 4th capacitor C4 is dimension
The grid voltage for holding the 7th thin film transistor (TFT) M7 is stablized, and avoids inverting clock signal XCK during variation (becoming L from H),
Because of the parasitic capacitance of the 6th thin film transistor (TFT) M6, the grid voltage of the 7th thin film transistor (TFT) M7 is caused to reduce, and then is accidentally beaten
It opens, causes the output failure of GOA circuit.
The grid of 13rd thin film transistor (TFT) M13 is connect with the grid of first film transistor M1 respectively, the 13rd film
The first end of transistor M13 accesses high level signal VGH, the second end and the second film crystal of the 13rd thin film transistor (TFT) M13
The grid of pipe M2 connects.13rd thin film transistor (TFT) M13 in order to guarantee at PD in low potential when, prevent the second film brilliant
Body pipe M2 is accidentally opened, to ensure that the output of GOA circuit is stablized.
Further, first film transistor M1, the second thin film transistor (TFT) M2, third thin film transistor (TFT) M3, the 4th film
Transistor M4, the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7, the 8th thin film transistor (TFT) M8,
9th thin film transistor (TFT) M9, the tenth thin film transistor (TFT) M10, the 11st thin film transistor (TFT) M11, the 12nd thin film transistor (TFT) M12,
13 thin film transistor (TFT) M13 are p-type metal-oxide-semiconductor.
Further, high level signal VGH and low level signal VGL is direct current signal.
Further, scan start signal STV on startup between be low level, clock signal CK is in first half period
Low level, and starting time and first half period are corresponding.I.e. the starting time is the stage 1 shown in Fig. 2.Inverting clock signal
The current potential of XCK is corresponding with the current potential of clock signal CK opposite.
The action process of GOA circuit structure of the invention is:
Stage 1:CK is that L XCK is H, and STV L, M3, M4, M5, M10, M11, M12 opening, the grid voltage of M1 is L+
Vth, the Vth are the threshold voltage of M2, and M1 is opened, and the grid voltage of M2 is H, and M2 is closed.The output of OUT terminal is XCK, for high electricity
It is flat.
Stage 2:CK is H, and XCK L, STV H, M10, M11, M12, M13, M6, M7 opening, M4, M3, M5, M8 are closed.
Because at this time M13 open, guarantee M2 grid voltage be H, will not because of M2 parasitic capacitance and cause M2 and M9 accidentally to be opened,
Cause output error.Meanwhile because first capacitor C1 maintains the current potential in stage 1, and because of the parasitic capacitance of M1, M1
Grid voltage be less than 2L it is low level L that so that M1 is fully opened, OUT terminal output, which is XCK,.
Stage 3:CK is L, and XCK H, STV H, M12, M9, M8, M7 are opened, so that the grid voltage of M2 is L+Vth, it should
Locate the threshold voltage that Vth is M2, open M9, to make the grid voltage H of M1, then M2 is opened, and M1 is closed, OUT terminal output
VGH is high level.
20 above-mentioned GOA circuit structures are connected in series, the output end OUT of upper level GOA circuit is as next
The STV input terminal of grade GOA circuit, i.e., connect with the grid of the M4 of next stage GOA circuit.In the STV input of the 1st grade of GOA circuit
End inputs STV signal shown in Fig. 2, shown in Fig. 2 in CK input terminal and XCK the input terminal input of every level-one GOA circuit
CK signal and XCK signal.
The simulation result diagram of finally obtained 1~4 grade of GOA circuit output is as shown in Figure 5 a, 16~20 grades of GOA circuit outputs
Simulation result diagram it is as shown in Figure 5 b, in Fig. 5 b it can also be seen that the 20th grade of GOA circuit in PU point and PD point current potential.It can see
Corresponding GOA circuit can export normal waveform out.
An end of C1 is connected to output end OUT by GOA circuit of the invention, also addition M13, C4, during multistage transmitting,
It can guarantee to export more stable.It avoids because the parasitic capacitance effect of thin film transistor (TFT) leads to opening by mistake and missing for thin film transistor (TFT)
It closes, causes OUT terminal output error.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (6)
1. a kind of scanning GOA circuit characterized by comprising first film transistor, the second thin film transistor (TFT), third film
Transistor, the 4th thin film transistor (TFT), first capacitor；
The first end of the first film transistor accesses inverting clock signal, the second end of the first film transistor and institute
The first end connection of the second thin film transistor (TFT) is stated, and as output end；
The grid of the third thin film transistor (TFT) accesses scan start signal, the first end of the third thin film transistor (TFT) with it is described
The grid of second thin film transistor (TFT) connects, and the second of the second end of the third thin film transistor (TFT) and second thin film transistor (TFT)
End connection and access high level signal；
The grid of 4th thin film transistor (TFT) connects with source electrode and accesses scan start signal, and drain electrode is brilliant with the first film
The grid of body pipe connects；
The both ends of the first capacitor respectively with the grid of the first film transistor and the first film transistor
Second end connection；
Wherein, first end is source electrode, and second end is drain electrode or first end is drain electrode, and second end is source electrode；
The scanning GOA circuit, further includes: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th
Thin film transistor (TFT)；
The grid of 6th thin film transistor (TFT) is connected with source electrode and accesses inverting clock signal, the 6th thin film transistor (TFT)
Drain electrode connect respectively with the first end of the grid of the 7th thin film transistor (TFT), the 5th thin film transistor (TFT)；
The grid of 8th thin film transistor (TFT) is connect with the first end of the 7th thin film transistor (TFT) and incoming clock signal, institute
The first end for stating the 8th thin film transistor (TFT) is connect with the second end of the 7th thin film transistor (TFT), the 8th thin film transistor (TFT)
Second end is connect with the first end of the third thin film transistor (TFT)；
The grid of 5th thin film transistor (TFT) connect and accesses scan start signal with the grid of the third thin film transistor (TFT),
The second end of 5th thin film transistor (TFT) is connect with the second end of second thin film transistor (TFT)；
The scanning GOA circuit, further includes: the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11st thin film transistor (TFT),
12 thin film transistor (TFT)s, the second capacitor, third capacitor；
The grid of 4th thin film transistor (TFT) to drain through the tenth thin film transistor (TFT) and the first film transistor,
And the first end connection of the 12nd thin film transistor (TFT)；
The grid of tenth thin film transistor (TFT) accesses scan start signal, the first end of the tenth thin film transistor (TFT) with it is described
The drain electrode of 4th thin film transistor (TFT) connects, the second end of the tenth thin film transistor (TFT) and the grid of the first film transistor
The connection of the first end of pole and the 12nd thin film transistor (TFT)；
The grid of 12nd thin film transistor (TFT) accesses low level signal, and the source electrode of the 12nd thin film transistor (TFT) and leakage
The other end of pole is connect with the first end of the 9th thin film transistor (TFT), the second end of the 9th thin film transistor (TFT) and described the
The second end of two thin film transistor (TFT)s connects, and the grid of the 9th thin film transistor (TFT) and the grid of second thin film transistor (TFT) connect
It connects；
The grid of 11st thin film transistor (TFT) accesses low level signal, the first end access of the 11st thin film transistor (TFT)
The second end of scan start signal, the 11st thin film transistor (TFT) is connect with the grid of the third thin film transistor (TFT)；
The both ends of second capacitor respectively with the grid of the 9th thin film transistor (TFT) and the 9th thin film transistor (TFT)
Second end connection；
The both ends of the third capacitor are connect with the source electrode and drain electrode of the 9th thin film transistor (TFT) respectively.
2. scanning GOA circuit according to claim 1, which is characterized in that further include the 4th capacitor；
The both ends of 4th capacitor are connect with the source electrode and drain electrode of the 5th thin film transistor (TFT) respectively.
3. scanning GOA circuit according to claim 2, which is characterized in that further include the 13rd thin film transistor (TFT)；
The grid of 13rd thin film transistor (TFT) is connect with the grid of the first film transistor respectively, and the described 13rd is thin
The first end of film transistor accesses high level signal, the second end of the 13rd thin film transistor (TFT) and second film crystal
The grid of pipe connects.
4. scanning GOA circuit according to claim 3, which is characterized in that the first film transistor, the second film are brilliant
Body pipe, third thin film transistor (TFT), the 4th thin film transistor (TFT), the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th film crystal
Pipe, the 8th thin film transistor (TFT), the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11st thin film transistor (TFT), the 12nd film are brilliant
Body pipe, the 13rd thin film transistor (TFT) are p-type metal-oxide-semiconductor.
5. scanning GOA circuit according to claim 3, which is characterized in that high level signal and low level signal are straight
Flow signal.
6. scanning GOA circuit according to claim 4, which is characterized in that scan start signal on startup between be low electricity
Flat, clock signal is low level in first half period, and the starting time and first half period are corresponding.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710860740.6A CN107403610B (en) | 2017-09-21 | 2017-09-21 | A kind of scanning GOA circuit |
| PCT/CN2017/109116 WO2019056508A1 (en) | 2017-09-21 | 2017-11-02 | Scan goa circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710860740.6A CN107403610B (en) | 2017-09-21 | 2017-09-21 | A kind of scanning GOA circuit |
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| CN107403610A CN107403610A (en) | 2017-11-28 |
| CN107403610B true CN107403610B (en) | 2019-10-11 |
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| CN201710860740.6A Active CN107403610B (en) | 2017-09-21 | 2017-09-21 | A kind of scanning GOA circuit |
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| WO (1) | WO2019056508A1 (en) |
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| US10803779B2 (en) | 2017-12-29 | 2020-10-13 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Gate driver on array (GOA) circuit unit, GOA circuit, and display panel |
| CN107909958B (en) * | 2017-12-29 | 2020-02-18 | 武汉华星光电半导体显示技术有限公司 | GOA circuit unit, GOA circuit and display panel |
| CN108399902A (en) * | 2018-03-27 | 2018-08-14 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit and display device |
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| Publication number | Publication date |
|---|---|
| CN107403610A (en) | 2017-11-28 |
| WO2019056508A1 (en) | 2019-03-28 |
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