CN107395530B - Switching chip, network equipment and power consumption control method - Google Patents
Switching chip, network equipment and power consumption control method Download PDFInfo
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- CN107395530B CN107395530B CN201710422273.9A CN201710422273A CN107395530B CN 107395530 B CN107395530 B CN 107395530B CN 201710422273 A CN201710422273 A CN 201710422273A CN 107395530 B CN107395530 B CN 107395530B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3278—Power saving in modem or I/O interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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Abstract
The invention discloses a switching chip, network equipment and a power consumption control method, wherein the switching chip comprises a power supply turn-off module, a plurality of PCS units and a physical layer unit; the PCS units are respectively connected with the physical layer unit and the power supply shutdown module; the PCS unit controls the power of a non-public SerDes interface in an unused state in the physical layer unit to be switched off; the power supply shutoff module judges whether to shut off the power supply of the public SerDes interface according to the notification signal output by each PCS unit; the network equipment comprises a switching chip and a processor for controlling the switching chip, and the technical problem that in the prior art, when a certain SerDes interface and a PCS channel are not used, the SerDes interface is in a power consumption state, so that power consumption is wasted is solved.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a switch chip, a network device, and a power consumption control method.
Background
SerDes interfaces (SERializer/DESerializer) have been widely used in the field of communications due to the increasing transmission bandwidth, and the number of SerDes interfaces has increased. Due to the implementation of SerDes PHY (Physical Layer) circuits, the power consumption of SerDes interfaces is relatively large. Low power control of the SerDes interface has become one of the cases that must be considered for low power control of the communication chip.
At present, SerDes Physical layer devices are designed in a multi-channel manner during design, that is, multiple PCS (Physical Coding sub-layers) are connected to one SerDes Physical layer device, so that sharing of partial resources is realized, and resource utilization rate is improved. However, when the SerDes interface is in operation, not all channels are used at the same time, and unused channels cause power consumption waste of the SerDes interface.
Therefore, in the prior art, when a certain SerDes interface and a channel of a PCS are not used, the SerDes interface is in a power consumption state, which results in waste of power consumption.
Disclosure of Invention
Embodiments of the present invention provide a switch chip, a network device, and a power consumption control method, so as to solve the technical problem in the prior art that when a channel between a SerDes interface and a PCS is not used, the SerDes interface is also in a power consumption state, which results in power consumption waste.
In a first aspect, an embodiment of the present invention provides a switch chip, including a switch module and an interface module, where the switch module is connected to the interface module, and is characterized in that:
the exchange chip also comprises a power supply turn-off module;
the interface module comprises a plurality of PCS units and a physical layer unit;
the PCS units are connected with the physical layer unit and the power supply shutdown module;
the PCS unit is used for controlling the power supply of the non-public SerDes interface in an unused state in the physical layer unit to be switched off;
the PCS unit is also used for outputting a first notification signal to the power supply shutdown module; the first notification signal is used to characterize a non-common SerDes interface connected to a PCS that outputs the first notification signal as being in an unused state;
the power supply turn-off module is also connected with a public SerDes interface in the physical layer unit;
the power supply turn-off module is used for judging whether to turn off the power supply of the public SerDes interface according to the first notification signal output by each PCS unit; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
Optionally, the power shutdown module further has an enable terminal for each non-common SerDes interface;
the power supply turn-off module is further configured to determine, for any one non-common SerDes interface, whether an unused state of the non-common SerDes interface needs to be considered based on a control signal of an enable terminal corresponding to the non-common SerDes interface when determining whether to turn off the power supply of the common SerDes interface according to the first notification signal output by each PCS unit.
In a second aspect, an embodiment of the present invention provides a network device including the foregoing switching chip, where the network device further includes a processor, the switching chip includes a switching module and an interface module, the switching module is connected to the interface module, and the switching chip further includes a power shutdown module; the interface module comprises a plurality of PCS units and a physical layer unit;
the PCS units are connected with the physical layer unit and the power supply shutdown module; the processor is connected with a power supply cut-off module in the exchange chip, and the power supply cut-off module is connected with a public SerDes interface in the physical layer unit;
the processor is used for determining whether each non-public SerDes interface is in an unused state or not, and controlling the power supply of the non-public SerDes interface in the unused state in the physical layer unit to be turned off through the PCS unit.
Optionally, the processor is further configured to output the first notification signal to the power shutdown module through the PCS unit.
In a third aspect, an embodiment of the invention provides a network device,
the network device comprises a processor and a switch chip, wherein the processor is used for determining whether each non-public SerDes interface in the switch chip is in an unused state; the processor controls the power of a non-public SerDes interface in an unused state in the physical layer unit to be switched off through a PCS unit in the exchange chip;
the processor is further configured to output a first control signal to a power shutdown module in the switch chip, where the power shutdown module determines whether to shut down a power supply of the common SerDes interface based on the first control signal; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
In a fourth aspect, an embodiment of the present invention provides a power consumption control method, including:
determining whether each SerDes interface in a physical layer unit is in an unused state;
controlling power-off of a SerDes interface in an unused state in the physical layer unit.
Optionally, the processor is connected to each of the plurality of non-public SerDes interfaces through each of the plurality of physical mask sublayers PCS, respectively, and the method includes:
the processor determining whether each non-common SerDes interface is in an unused state;
the processor controls the non-public SerDes interface in an unused state to be powered off through a physical mask sublayer PCS connected with the non-public SerDes interface in the unused state.
Optionally, the plurality of physical mask sublayers PCS are connected to the common SerDes interfaces in the physical layer unit through a power down module, and after the processor determines whether each non-common SerDes interface is in an unused state, the method further includes:
the processor outputs a first notification signal to the power supply shutdown module through a physical mask sublayer (PCS) connected with a non-public SerDes interface in an unused state, wherein the first notification signal is used for representing that the non-public SerDes interface connected with the PCS outputting the first notification signal is in the unused state;
the power supply turn-off module judges whether to turn off the power supply of the public SerDes interface based on each received first notification signal;
when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
Optionally, the processor is connected to the common SerDes interface in the physical layer unit through a power down module, and after the processor determines whether each non-common SerDes interface is in an unused state, the method further includes: the processor determining whether to power off the common SerDes interface based on a usage status of each non-common SerDes interface;
when the common SerDes interface is powered off, the processor controls the common SerDes interface to be powered off through the power-off module.
Optionally, the power shutdown module further includes a plurality of enable terminals, and the method further includes:
and when the power supply turn-off module judges whether to control the power supply turn-off of the public SerDes interface based on each received first notification signal, for any one non-public SerDes interface, determining whether the unused state of the non-public SerDes interface needs to be considered based on the control signal of the enabling end corresponding to the non-public SerDes interface.
One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages: the power supply of the non-public SerDes interface in an unused state is turned off through the PCS unit, and the power supply of the public SerDes interface is controlled to be turned off through the power supply turn-off module. Thus, power consumption of the SerDes interface is reduced, which in turn reduces power consumption of a switch chip including the SerDes interface and power consumption of a network device including the switch chip.
Drawings
FIG. 1 is a first diagram of a switch chip according to an embodiment of the present invention;
FIG. 2 is a second schematic diagram of a switch chip according to an embodiment of the invention;
FIG. 3 is a diagram of a physical layer unit according to an embodiment of the present invention;
FIG. 4 is a diagram of a power shutdown module according to an embodiment of the invention;
fig. 5 is a first diagram of a network device in an embodiment of the invention;
FIG. 6 is a second diagram of a network device in an embodiment of the invention;
fig. 7 is a first flowchart of a power consumption control method according to an embodiment of the present invention.
Detailed Description
In order to solve the technical problem, the technical scheme in the embodiment of the invention has the following general idea: a exchange chip, network equipment and power consumption control method, the exchange chip also includes the power cut-off module; the interface module comprises a plurality of PCS units and a physical layer unit; the PCS units are connected with the physical layer unit and the power supply shutdown module; the PCS unit is used for controlling the power supply of the non-public SerDes interface in an unused state in the physical layer unit to be switched off; the PCS unit is also used for outputting a first notification signal to the power supply shutdown module; the first notification signal is used to characterize a non-common SerDes interface connected to a PCS that outputs the first notification signal as being in an unused state; the power supply turn-off module is used for judging whether to turn off the power supply of the public SerDes interface according to the first notification signal output by each PCS unit; if so, the power shutdown module controls the power shutdown of the common SerDes interface; the network device comprises a switching chip and a processor for controlling the switching chip.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
Referring to fig. 1, an embodiment of the present invention provides a switch chip, where the switch chip includes a switch module 10 and an interface module 20, and the switch chip further includes a power shutdown module 30, where the power shutdown module shown in fig. 1 is disposed outside the interface module, and preferably, the power shutdown module may be disposed inside the interface module. The switch module 10 is connected to the interface module 20, and the switch module 10 receives data from the interface module 20 and transmits data to the outside through the interface module.
The interface module 20 includes a plurality of PCS units and physical layer units;
the PCS units are connected with the physical layer unit and the power supply shutdown module; specifically, each PCS unit is connected to each non-common SerDes interface in the physical layer unit, i.e., the PCS units correspond to the non-common SerDes interfaces one to one.
The PCS unit is used for controlling the power supply of the non-public SerDes interface in an unused state in the physical layer unit to be switched off;
the PCS unit is further configured to output a first notification signal to the power shutdown module 30; the first notification signal is used to characterize a non-common SerDes interface connected to a PCS that outputs the first notification signal as being in an unused state;
a power-off module 30 is connected to each PCS unit, and the power-off module 30 is also connected to the common SerDes interface in the physical layer unit.
The power shutdown module 30 is configured to determine whether to shut down the power supply of the common SerDes interface according to the first notification signal output by each PCS unit; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
The switch includes, among other things, a switching chip and a processor (CPU). The processor in the switch can determine whether the SerDes interface is in a use state according to the configuration of a user on the SerDes interface, and the user can set the SerDes interface to be in a non-use state when the user does not need to use a certain SerDes interface. When the processor determines that a certain non-public SerDes interface is in an unused state, the power of the non-public SerDes interface is controlled to be turned off through the PCS unit connected with the non-public SerDes interface, namely, the PCS unit connected with the non-public SerDes interface controls the power of the non-public SerDes interface to be turned off according to the instruction of the CPU.
In addition, when the processor determines that a certain non-common SerDes interface is in an unused state, the processor can also output a first notification signal to the power shutdown module through a PCS unit connected with the non-common SerDes interface. If each PCS unit outputs a first notification signal to the power shutdown module, that is, if each non-common SerDes interface is in an unused state, the power shutdown module shuts down the power of the common SerDes interface.
The physical layer unit may include a common SerDes interface and a plurality of non-common SerDes interfaces, and the specific number of the common SerDes interfaces and the non-common SerDes interfaces may be selected according to an actual application situation, which is not limited herein. The public SerDes interface provides work support for the non-public SerDes interface, and when the power supply of the public SerDes interface is turned off, namely is not in a working state, the non-public SerDes interface cannot work.
In this embodiment, the power-off of each non-common SerDes interface in the physical layer unit is controlled by the PCS unit, and the power of the common SerDes interface is controlled by the power-off module according to the state of each non-common SerDes interface output by each PCS unit. Because the embodiment can perform the turn-off processing on the non-public SerDes interfaces in the unused state, and can also perform the turn-off control on the power supply of the public SerDes interfaces according to the state of each non-public SerDes interface, the power consumption of the SerDes interfaces is reduced, and thus the power management scheme of the physical layer unit is optimized, and the power loss of the switching chip is reduced.
Optionally, the power shutdown module 30 also has an enable terminal for each non-common SerDes interface; the power turn-off module 30 is further configured to determine, for any one non-common SerDes interface, whether an unused state of the non-common SerDes interface needs to be considered based on a control signal of an enable end corresponding to the non-common SerDes interface when determining whether to turn off the power supply of the common SerDes interface according to the first notification signal output by each PCS unit. For example, if a non-public SerDes interface is not important or not needed, the enabling end corresponding to the non-public SerDes interface is controlled, so that whether the non-public SerDes interface is in a use state or not can be considered when judging whether the power supply of the public SerDes interface is turned off, functions of the switching chip are enriched, and power consumption is reduced in one step.
Specifically, referring to fig. 2, the interface module 20 includes a physical layer unit 102 and a plurality of physical mask sublayers PCS, where the number of PCS is 4 PCS0-PCS3 shown in fig. 2 or fig. 3, and the number of PCS may be set according to actual requirements, and is not limited to 4. Preferably, the power down module shown in fig. 2 is arranged inside the interface module, the power down module may also be arranged outside the interface module.
The internal structure of the physical layer unit 102 is, as shown in fig. 3, the physical layer unit 102 includes 4 non-common SerDes interfaces (such as SerDes interfaces 0-3 in fig. 3) and 1 common SerDes interface (such as SerDes interface 4 in fig. 4), and the number of the specific non-common SerDes interfaces and common SerDes interfaces in the physical layer unit 102 may be set according to the amount of SerDes interfaces required in actual applications. As shown in fig. 3, SerDes interface 0 includes a data interface 100 and a control interface 200, SerDes interface 2 includes a data interface 101 and a control interface 201, and SerDes interface 3 includes a data interface 102 and a control interface 202.
The power shutdown module 30 may be implemented by a gate circuit, or may be implemented by other circuit structures. If the power shutdown module 30 is implemented by a gate circuit, the internal structure of the power shutdown module 30 may be as shown in fig. 4 (the number of and gates in the power shutdown module 30 may also be adaptively changed according to the difference between the number of PCSs and the number of SerDes interfaces of the physical layer unit), where the power shutdown module 30 includes four or gates 501 and 504 and an and gate 505 shown in fig. 4, and two input terminals of the or gates are respectively connected to the enable terminal and the control interface of the power shutdown module. The power shutdown module 30 has an enable terminal 400-an enable terminal 403 and a control interface 300-a control interface 303.
Referring to fig. 2 to 4, the first operation principle of the switch chip is (assuming that the plurality of enable terminals of the power shutdown module 30 are all floating): the power-off of the non-common SerDes interface in an unused state in the physical layer unit 102 may be controlled by PCS0-PCS 3; assuming that SerDes interface 0 and SerDes interface 1 in the physical layer unit are in an unused state, the power of SerDes interface 0 is controlled to be turned off through PCS0, and the power of SerDes interface 1 is controlled to be turned off through PCS 1;
the PCS0 also sends a first notification signal to the or gate 501 in the power shutdown module 30, such as the state of the on-or control interface 300 being 1, and the PCS1 also sends a first notification signal to the or gate 502 in the power shutdown module 30, such as the state of the on-or control interface 301 being 1. Wherein the first notification signal is used to characterize that a non-common SerDes interface connected to a PCS that outputs the first notification signal is in an unused state;
if the SerDes interfaces 0-3 are all in an unused state, the states of the output pins of the four or gates of the power shutdown module 30 all become 1, and a control signal in the state of 1 is output through the and gate 505 phase and then to control the power shutdown of the common SerDes interface 4 connected to the common control interface 204.
Referring to fig. 2-4, the second operation principle of the switch chip is (assuming that the plurality of enable terminals of the power shutdown module 30 are controlled, for example, the plurality of enable terminals may be controlled by an external processor, and the external processor may control the enable terminals through a PCS, or the external processor directly controls the enable terminals): when the power shutdown module 30 controls the state of the enable terminal 403 of the or gate 504 in the power shutdown module 30 to be always 1, assuming that the unused state of the non-common SerDes interface 3 does not need to be considered, no matter whether the signal received by the power shutdown module from the PCS3 is that the SerDes interface 3 is in the used state or the unused state, or the output signal of the output terminal of the or gate 504 is always 1, the power of the common SerDes interface 4 is turned off without considering that the SerDes interface 3 is in the unused state or the used state.
Referring to fig. 5, a second embodiment of the present invention provides a network device, which includes a switch chip and a processor 40. The exchange chip comprises an exchange module and an interface module, wherein the exchange module receives data from the interface module and sends the data to the outside through the interface module. The interface module includes a plurality of PCS units and a physical layer unit. Also included in the switching chip is a power down module, preferably disposed inside the interface module as shown in fig. 5. The power down module may also be arranged outside the interface module. The input end of the power shutdown module is connected to each PCS unit, and the output end of the power shutdown module 30 is connected to the common SerDes interface in the physical layer unit. The common SerDes interface is shown in figure 3 as SerDes interface 4.
Each PCS unit is connected to a physical layer unit. Specifically, each PCS unit is connected to each non-common SerDes interface in the physical layer unit, i.e., the PCS units correspond to the non-common SerDes interfaces one to one. Non-common SerDes interfaces are SerDes interface 1, SerDes interface 2, and SerDes interface 3 shown in fig. 3. The processor 40 is configured to determine whether each non-common SerDes interface is in an unused state, and control, by the PCS unit, power of the non-common SerDes interface in the unused state in the physical layer unit to be turned off; and the PCS unit is used for controlling the power supply of the non-public SerDes interface in an unused state in the physical layer unit to be switched off.
The processor 40 is further configured to output the first notification signal to the power shutdown module through the PCS unit. The first notification signal is used to characterize that a non-common SerDes interface connected to the PCS that outputs the first notification signal is in an unused state.
The power shutdown module 30 is configured to determine whether to shut down the power supply of the common SerDes interface according to the first notification signal output by each PCS unit; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
Wherein the network device may be a switch. A processor in the network device may determine whether the SerDes interface is in a use state according to a configuration of the SerDes interface by a user, and the user may set a SerDes interface to a non-use state when the user does not need to use the SerDes interface. When the processor determines that a certain non-public SerDes interface is in an unused state, the power of the non-public SerDes interface is controlled to be turned off through the PCS unit connected with the non-public SerDes interface, namely, the PCS unit connected with the non-public SerDes interface controls the power of the non-public SerDes interface to be turned off according to the instruction of the CPU.
When the processor determines that a certain non-public SerDes interface is in an unused state, the processor can also output a first notification signal to the power shutdown module through the PCS unit connected with the non-public SerDes interface. If each PCS unit outputs a first notification signal to the power shutdown module, that is, if each non-common SerDes interface is in an unused state, the power shutdown module shuts down the power of the common SerDes interface.
In this embodiment, the turn-off of the power supply of each SerDes interface in the network device is controlled respectively, the processor in the network device turns off the power supply of the non-common SerDes interface in an unused state through the PCS unit, the processor in the network device outputs a first notification signal to the power turn-off module through the PCS unit, and the power turn-off module controls the turn-off of the power supply of the common SerDes interface according to the first notification signal output by each PCS unit. Thus, power consumption of the SerDes interface is reduced, which in turn reduces power consumption of a switch chip including the SerDes interface and power consumption of a network device including the switch chip.
Specifically, referring to fig. 5, 3 and 4, the processor 40 is respectively connected to PCS0-PCS3, PCS0-PCS3 are respectively connected to SerDes interfaces 0-SerDes interfaces 3 in the physical layer unit 102 in a one-to-one correspondence manner, PCS0-PCS3 are also respectively connected to or gates 501-504 in the power shutdown module 30 in a one-to-one correspondence manner, and the output terminal of the and gate 505 of the power shutdown module is connected to the common SerDes interface 4.
The processor 40 may control power-off of the non-common SerDes interfaces in the physical layer unit 102 in an unused state through PCS0-PCS 3. Assuming that SerDes interface 0 and SerDes interface 1 in the physical layer unit are in an unused state, the processor controls the power of SerDes interface 0 to be turned off through PCS0, and controls the power of SerDes interface 1 to be turned off through PCS 1;
the processor also sends a first notification signal, such as the state of the on-or control interface 300 is 1, to the or gate 501 in the power down module 30 through the PCS0, and the PCS1 also sends a first notification signal, such as the state of the on-or control interface 301 is 1, to the or gate 502 in the power down module 30. Wherein the first notification signal is used to characterize that a non-common SerDes interface connected to a PCS that outputs the first notification signal is in an unused state.
Assuming that a plurality of enable terminals of the power shutdown module 30 are not controlled and in a floating state at this time, if the SerDes interfaces 0 to 3 are all in an unused state, the states of the output pins of the four or gates of the power shutdown module 30 all become 1, and a control signal in a 1 state is output through the and gate 505 phase and then to control the power shutdown of the common SerDes interface 4 connected to the common control interface 204.
Assuming that the plurality of enable terminals of the power shutdown module 30 are controlled, for example, the plurality of enable terminals may be controlled by an external processor, and the external processor may control the enable terminals through a PCS, or the external processor directly controls the enable terminals, when the power shutdown module 30, assuming that consideration is not required for the unused state of the non-common SerDes interface 3, the state of the enable terminal 403 of the or gate 504 in the power shutdown module 30 is always controlled to be 1 regardless of whether the non-common SerDes interface 3 is in the used state or the unused state, and the power of the common SerDes interface 4 is turned off regardless of whether the signal received by the power shutdown module from the PCS3 is that the SerDes interface 3 is in the used state or the unused state, or the output signal of the output terminal of the gate 504 is always 1, and regardless of whether the SerDes interface 3 is in the unused state or the used state.
Referring to fig. 6, a third embodiment of the present invention provides a network device, which includes a processor 40 and a switch chip. The exchange chip comprises an exchange module and an interface module, and the exchange module is connected with the interface module. Processor 40 is directly connected to a power-off module that interfaces with the common SerDes in the switch chip. The power down module shown in fig. 6 is provided outside the interface module, and preferably, the power down module may be provided inside the interface module. The interface module includes a plurality of PCS units and a physical layer unit.
The processor 40 is configured to determine whether each non-common SerDes interface in the switch chip is in an unused state; the processor 40 controls the power of the non-common SerDes interface in the physical layer unit in an unused state to be turned off through the PCS unit in the switch chip. Non-common SerDes interfaces are SerDes interface 1, SerDes interface 2, and SerDes interface 3 shown in fig. 3.
The processor 40 is further configured to output a first control signal to a power shutdown module in the switch chip, where the power shutdown module determines whether to shut off a power supply of the common SerDes interface based on the first control signal; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off. The common SerDes interface is shown in figure 3 as SerDes interface 4.
The processor may determine whether the SerDes interface is in a use state based on a configuration of the SerDes interface by a user, and the user may set a SerDes interface to a non-use state when the user does not need to use the SerDes interface. When the processor determines that a certain non-public SerDes interface is in an unused state, the power of the non-public SerDes interface is controlled to be turned off through the PCS unit connected with the non-public SerDes interface, namely, the PCS unit connected with the non-public SerDes interface controls the power of the non-public SerDes interface to be turned off according to the instruction of the CPU.
The processor may send a first control signal to a power shutdown module when it is determined that all non-common SerDes interfaces are in an unused state, the power shutdown module determining whether to shut off a power supply of the common SerDes interfaces based on the first control signal; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
In this embodiment, the processor in the network device turns off the power supply of the non-common SerDes interface in an unused state through the PCS unit, and the processor in the network device directly controls the turning off of the power supply of the common SerDes interface through the power supply turning-off module. Thus, power consumption of the SerDes interface is reduced, which in turn reduces power consumption of a switch chip including the SerDes interface and power consumption of a network device including the switch chip.
Specifically, referring to fig. 6 and 3, the processor 40 may control power-off of the non-common SerDes interface in an unused state in the physical layer unit 102 through PCS0-PCS 3; assuming that SerDes interface 0 and SerDes interface 1 in the physical layer unit are in an unused state, the processor controls the power of SerDes interface 0 to be turned off through PCS0, and controls the power of SerDes interface 1 to be turned off through PCS 1;
the processor 40 may output a first control signal to a power shutdown module 30 that determines whether to shut off power to the common SerDes interface based on the first control signal when it is determined that SerDes interface 0, SerDes interface 1, SerDes interface 2, and SerDes interface 3 are all in an unused state; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
Referring to fig. 7, a fourth embodiment of the present invention provides a power consumption control method, including:
s10, determining whether each SerDes interface in the physical layer unit is in an unused state;
and S20, controlling the power of the SerDes interface in an unused state in the physical layer unit to be switched off.
The processor may determine whether the SerDes interface is in a use state based on a configuration of the SerDes interface by a user, and the user may set a SerDes interface to a non-use state when the user does not need to use the SerDes interface. When the processor determines that a certain non-public SerDes interface is in an unused state, the power of the non-public SerDes interface is controlled to be turned off through the PCS unit connected with the non-public SerDes interface, namely, the PCS unit connected with the non-public SerDes interface controls the power of the non-public SerDes interface to be turned off according to the instruction of the CPU.
The power consumption control method in this embodiment determines whether each SerDes interface is in an unused state, and turns off the power supply of the SerDes interface in the unused state, thereby optimizing the power management scheme of the physical layer unit and reducing power loss.
Optionally, the physical layer unit includes a public SerDes interface and a plurality of non-public SerDes interfaces, and the processor is respectively connected to each of the plurality of non-public SerDes interfaces through each of a plurality of physical mask sublayers PCS, and the method specifically includes:
the processor determining whether each non-common SerDes interface is in an unused state;
the processor controls the non-public SerDes interface in an unused state to be powered off through a physical mask sublayer PCS connected with the non-public SerDes interface in the unused state.
Further, there are two connection modes for controlling the power of the public SerDes interface to be turned off.
The first connection mode is as follows: the plurality of physical mask sublayers PCS are connected to a common SerDes interface in the physical layer unit through a power-off module.
After the processor determines whether each non-common SerDes interface is in an unused state, the method further comprises:
the processor outputs a first notification signal to the power supply shutdown module through a physical mask sublayer (PCS) connected with a non-public SerDes interface in an unused state, wherein the first notification signal is used for representing that the non-public SerDes interface connected with the PCS outputting the first notification signal is in the unused state;
the power supply turn-off module may be specifically a gate circuit, and determines whether to turn off the power supply of the common SerDes interface based on each received first notification signal; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
The connection mode in the embodiment simplifies the calculation complexity of the processor, the power supply of the non-public SerDes interface in the unused state is cut off through the PCS unit, and the power supply of the public SerDes interface is cut off and controlled through the power supply cut-off module according to the use state of each non-public SerDes interface, so that the power consumption of the SerDes interface is reduced, and the power loss of the exchange chip is reduced.
Further, the power shutdown module further includes a plurality of enabling ends, and when the power shutdown module determines whether to control power shutdown of the common SerDes interface based on each received first notification signal, for any one non-common SerDes interface, it determines whether it is necessary to consider an unused state of the non-common SerDes interface based on a control signal of the enabling end corresponding to the non-common SerDes interface. For example, if a non-public SerDes interface is not important or does not need to be used, the non-public SerDes interface can be not considered to be in an unused state by controlling the enabling end corresponding to the non-public SerDes interface, so that the functions of the switching chip are enriched, and the power consumption is reduced by one step. Specifically, referring to fig. 5, 3 and 4, the processor 40 is respectively connected to PCS0-PCS3, PCS0-PCS3 are respectively connected to SerDes interfaces 0-SerDes interfaces 3 in the physical layer unit 102 in a one-to-one correspondence manner, PCS0-PCS3 are also respectively connected to or gates 501-504 in the power shutdown module 30 in a one-to-one correspondence manner, and the output terminal of the and gate 505 of the power shutdown module is connected to the common SerDes interface 4.
The processor 40 can control the power of the non-common SerDes interface in the unused state in the physical layer unit 102 to be turned off through PCS0-PCS 3; assuming that SerDes interface 0 and SerDes interface 1 in the physical layer unit are in an unused state, the processor controls the power of SerDes interface 0 to be turned off through PCS0, and controls the power of SerDes interface 1 to be turned off through PCS 1;
the processor also sends a first notification signal, such as the state of the on-or control interface 300 is 1, to the or gate 501 in the power down module 30 through the PCS0, and the PCS1 also sends a first notification signal, such as the state of the on-or control interface 301 is 1, to the or gate 502 in the power down module 30. Wherein the first notification signal is used to characterize that a non-common SerDes interface connected to a PCS that outputs the first notification signal is in an unused state;
assuming that a plurality of enable terminals of the power shutdown module 30 are not controlled and in a floating state at this time, if the SerDes interfaces 0 to 3 are all in an unused state, the states of the output pins of the four or gates of the power shutdown module 30 all become 1, and a control signal in a 1 state is output through the and gate 505 phase and then to control the power shutdown of the common SerDes interface 4 connected to the common control interface 204.
Assuming that the plurality of enable terminals of the power shutdown module 30 are controlled, for example, the plurality of enable terminals may be controlled by an external processor, and the external processor may control the enable terminals through a PCS, or the external processor directly controls the enable terminals, when the power shutdown module 30, assuming that consideration is not required for the unused state of the non-common SerDes interface 3, the state of the enable terminal 403 of the or gate 504 in the power shutdown module 30 is always controlled to be 1 regardless of whether the non-common SerDes interface 3 is in the used state or the unused state, and the power of the common SerDes interface 4 is turned off regardless of whether the signal received by the power shutdown module from the PCS3 is that the SerDes interface 3 is in the used state or the unused state, or the output signal of the output terminal of the gate 504 is always 1, and regardless of whether the SerDes interface 3 is in the unused state or the used state.
The second connection mode is as follows: the processor is connected with the common SerDes interface in the physical layer unit through a power-off module. After the processor determines whether each non-common SerDes interface is in an unused state, the processor determines whether to power off the common SerDes interface based on the usage state of each non-common SerDes interface;
when the common SerDes interface is powered off, the processor controls the common SerDes interface to be powered off through the power-off module.
The connection mode processor in the embodiment is directly connected with the public SerDes interface through the power supply cut-off unit in the exchange chip, controls the power supply of the public SerDes interface to be cut off, reduces the pressure of the PCS unit for processing data, and cuts off the power supply of the non-public SerDes interface in an unused state through the PCS unit.
Specifically, referring to fig. 6 and 3, the processor 40 may control power-off of the non-common SerDes interface in an unused state in the physical layer unit 102 through PCS0-PCS 3; assuming that SerDes interface 0 and SerDes interface 1 in the physical layer unit are in an unused state, the processor controls the power of SerDes interface 0 to be turned off through PCS0, and controls the power of SerDes interface 1 to be turned off through PCS 1;
the processor 40 outputs a first control signal to a power shutdown module 30, which determines whether to shut off the power of the common SerDes interface based on the first control signal; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
A fifth embodiment of the present invention provides a computer apparatus, which includes a processing unit, and the processing unit is configured to implement the steps of the method according to the fourth embodiment when executing the computer program stored in the memory.
An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, where the computer program is characterized in that: the computer program, when being executed by a processing unit, implements the steps of the method according to embodiment four.
The technical scheme in the embodiment of the invention at least has the following technical effects or advantages: the method comprises the steps of respectively controlling the power supply of each SerDes interface in a physical layer unit to be switched off, judging whether each SerDes interface is in an unused state or not, and switching off the power supply of the SerDes interface in the unused state, so that the power supply management scheme of the physical layer unit is optimized, and the power loss of a switching chip is reduced.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A switching chip comprises a switching module and an interface module, wherein the switching module is connected with the interface module, and the switching chip is characterized in that:
the exchange chip also comprises a power supply turn-off module;
the interface module comprises a plurality of PCS units and a physical layer unit;
the PCS units are connected with the physical layer unit and the power supply shutdown module;
the PCS unit is used for controlling the power supply of the non-public SerDes interface in an unused state in the physical layer unit to be switched off;
the PCS unit is also used for outputting a first notification signal to the power supply shutdown module; the first notification signal is used to characterize a non-common SerDes interface connected to a PCS that outputs the first notification signal as being in an unused state;
the power supply turn-off module is also connected with a public SerDes interface in the physical layer unit;
the power supply turn-off module is used for judging whether to turn off the power supply of the public SerDes interface according to the first notification signal output by each PCS unit; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
2. The chip of claim 1, wherein:
the power shutdown module further has an enable terminal for each non-common SerDes interface;
the power supply turn-off module is further configured to determine, for any one non-common SerDes interface, whether an unused state of the non-common SerDes interface needs to be considered based on a control signal of an enable terminal corresponding to the non-common SerDes interface when determining whether to turn off the power supply of the common SerDes interface according to the first notification signal output by each PCS unit.
3. A network device comprising the switch chip of claim 1 or 2, wherein: the network device further comprises a processor, wherein the processor is used for determining whether each non-public SerDes interface is in an unused state, and controlling the power supply of the non-public SerDes interface in the unused state in the physical layer unit to be turned off through the PCS unit.
4. The network device of claim 3, wherein: the processor is further configured to output the first notification signal to the power shutdown module through the PCS unit.
5. A network device comprises a processor and a switching chip, wherein the switching chip comprises a switching module and an interface module, and the switching module is connected with the interface module; the interface module comprises a plurality of PCS units and a physical layer unit;
the PCS units are connected with the physical layer unit and the power supply shutdown module; the processor is connected with a power supply cut-off module in the exchange chip, and the power supply cut-off module is connected with a public SerDes interface in the physical layer unit;
the processor is configured to determine whether each non-common SerDes interface in the switch chip is in an unused state; controlling the power supply of a non-public SerDes interface in an unused state in a physical layer unit to be switched off through a PCS unit in the exchange chip;
the processor is further configured to output a first control signal to a power shutdown module in the switch chip, where the power shutdown module determines whether to shut off a power supply of the common SerDes interface based on the first control signal; when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
6. A method of power consumption control, wherein a processor is respectively connected to each of a plurality of non-common SerDes interfaces through each of a plurality of physical mask sublayers PCS, the method comprising:
determining whether each of the non-common SerDes interfaces in a physical layer unit is in an unused state;
the power-off of the non-common SerDes interface in an unused state in the physical layer unit is controlled by a physical mask sublayer PCS connected to the non-common SerDes interface in an unused state.
7. The method of claim 6, wherein the plurality of physical mask sublayers (PCS) are connected with a common SerDes interface in the physical layer unit through a power-off module, the method further comprising, after the processor determines whether each of the non-common SerDes interfaces is in an unused state:
the processor outputs a first notification signal to the power supply shutdown module through a physical mask sublayer (PCS) connected with a non-public SerDes interface in an unused state, wherein the first notification signal is used for representing that the non-public SerDes interface connected with the PCS outputting the first notification signal is in the unused state;
the power supply turn-off module judges whether to turn off the power supply of the public SerDes interface based on each received first notification signal;
when the common SerDes interface is powered off, the power-off module controls the common SerDes interface to be powered off.
8. The method of claim 6, wherein the processor is connected with a common SerDes interface in the physical layer unit through a power down module, the method further comprising, after the processor determines whether each non-common SerDes interface is in an unused state: the processor determining whether to power off the common SerDes interface based on a usage status of each non-common SerDes interface;
when the common SerDes interface is powered off, the processor controls the common SerDes interface to be powered off through the power-off module.
9. The method of claim 7, wherein the power shutdown module further comprises a plurality of enable terminals, the method further comprising:
and when the power supply turn-off module judges whether to control the power supply turn-off of the public SerDes interface based on each received first notification signal, for any one non-public SerDes interface, determining whether the unused state of the non-public SerDes interface needs to be considered based on the control signal of the enabling end corresponding to the non-public SerDes interface.
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| CN112636932B (en) * | 2019-10-08 | 2022-08-30 | 烽火通信科技股份有限公司 | Dynamic adjustment method and system for equipment power consumption |
| CN111092739B (en) * | 2019-12-26 | 2022-02-15 | 网络通信与安全紫金山实验室 | A method for dynamic adjustment of switch power consumption |
| CN111555989B (en) * | 2020-04-24 | 2022-01-11 | 北京物芯科技有限责任公司 | Configurable switching chip port |
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| CN101938360B (en) * | 2009-06-30 | 2013-01-30 | 瑞昱半导体股份有限公司 | Network interface device and related power saving method |
| CN103268262A (en) * | 2013-04-28 | 2013-08-28 | 北京创毅讯联科技股份有限公司 | Method for multiple basebands to access single-user identification card, and processor |
| EP2992713B1 (en) * | 2013-04-30 | 2018-10-03 | Sony Corporation | Terminal-initiated power mode switching |
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