CN107369649A - A kind of semiconductor devices and its manufacture method - Google Patents
A kind of semiconductor devices and its manufacture method Download PDFInfo
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- CN107369649A CN107369649A CN201610308959.0A CN201610308959A CN107369649A CN 107369649 A CN107369649 A CN 107369649A CN 201610308959 A CN201610308959 A CN 201610308959A CN 107369649 A CN107369649 A CN 107369649A
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明提供一种半导体器件及其制造方法，涉及半导体技术领域。包括：提供第一衬底，在第一衬底的第一表面一侧形成包括晶体管和第一互连结构的射频前端器件，以及位于晶体管外侧的第二互连结构；提供第二衬底，通过键合工艺将第二衬底与所述第一衬底的形成有所述射频前端器件的一侧相接合；从所述第一衬底的与所述第一表面相对的第二表面一侧对所述第一衬底进行减薄处理至第一衬底厚度；在减薄至第一衬底厚度的第一衬底的第二表面形成背面介电层；第一衬底厚度在所述晶体管最小特征尺寸的0.01倍以上及晶体管最大特征尺寸的10倍以下。根据本发明的制造方法，通过对体硅衬底进行减薄，提高了CMOS器件的射频性能。
The invention provides a semiconductor device and a manufacturing method thereof, which relate to the technical field of semiconductors. Including: providing a first substrate, forming a radio frequency front-end device including a transistor and a first interconnection structure on the first surface side of the first substrate, and a second interconnection structure located outside the transistor; providing a second substrate, The second substrate is bonded to the side of the first substrate on which the radio frequency front-end device is formed through a bonding process; from the second surface of the first substrate opposite to the first surface Thinning the first substrate to the first substrate thickness; forming a back dielectric layer on the second surface of the first substrate thinned to the first substrate thickness; the first substrate thickness is at the first substrate thickness More than 0.01 times the smallest characteristic size of the transistor and less than 10 times the largest characteristic size of the transistor. According to the manufacturing method of the invention, the radio frequency performance of the CMOS device is improved by thinning the bulk silicon substrate.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its
Manufacture method.
Background technology
With the lifting of CMOS performances and under the leading of wireless communication chips Integrated Trend,
Radio frequency (RF) CMOS processing procedures are not only the heat subject of educational circles's research, also result in industry
Concern.RF CMOS processing procedure biggest advantages are can be by radio frequency, fundamental frequency and memory
The high degree of integration integrated Deng component, and component cost is reduced simultaneously.
RF CMOS technologies typically have and can be divided into two major classes：Bulk CMOS technique and insulator
Upper silicon (SOI) CMOS technology.Wherein, Bulk CMOS technique has relative SOI CMOS
Technique lower cost, however, in conventional bulk silicon CMOS technology, due to the influence of substrate,
So that the radiofrequency characteristicses of device reduce a lot.
Therefore, in order to solve the above technical problems, be necessary to propose a kind of new semiconductor devices and
Its manufacture method.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply and be further described in mode part.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean to attempt the protection domain for determining technical scheme claimed.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of semiconductor devices
Manufacture method, methods described include：
The first substrate is provided, being formed in the first surface side of first substrate includes multiple crystalline substances
The radio frequency front-end devices of body pipe and the first interconnection structure, and on the outside of the transistor
Two interconnection structures；
The second substrate is provided, by bonding technology by second substrate and first substrate
Side formed with the radio frequency front-end devices engages；
From the second surface side relative with the first surface of first substrate to described
First substrate carries out reduction processing to the first substrate thickness；
The back side is formed in the second surface for being thinned to the first substrate of first substrate thickness to be situated between
Electric layer；
Wherein, 0.01 times in the transistor minimum feature size of first substrate thickness
Above and less than 10 times of the transistor maximum characteristic size.
Further, in the first surface side of first substrate, the both sides of the transistor
Formed with fleet plough groove isolation structure in first substrate.
Further, the reduction processing is stopped on the fleet plough groove isolation structure.
Further, it is further comprising the steps of after the backside dielectric layer is formed：
Formed and second interconnection structure in the second surface side of first substrate
Bottom metal layers electrical connection through-hole structure；
Pad, the pad and institute are formed on the part second surface of first substrate
State through-hole structure electrical connection.
Further, after the pad is formed, in addition to step：
Form the second surface for covering first substrate but expose beating for the pad
The passivation layer in line area.
Further, first substrate is body silicon substrate.
Further, the method for the reduction processing uses backgrind technique, chemically mechanical polishing
Or the one or more in wet-etching technology.
Further, first interconnection structure includes bottom metal layers, metal layer at top and position
Intermediate metal layer between bottom metal layers and metal layer at top, in the part intermetallic metal
Formed with metal-insulating layer-metal capacitor on layer.
Further, before the bonding technology is carried out, in second substrate and described the
Bonded layer is formed on the surface that one substrate engages.
Another aspect of the present invention provides a kind of semiconductor devices, is made and obtained using foregoing method
The semiconductor devices.
In summary, manufacturing method according to the invention, by the way that body silicon substrate is thinned,
Improve the radio-frequency performance of cmos device.The semiconductor devices of the present invention, as a result of
Above-mentioned manufacture method, thus equally there is above-mentioned advantage.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 E are a kind of manufacturer of semiconductor devices in one embodiment of the invention
The sectional view for the structure that the correlation step of method is formed；
Fig. 2 is a kind of manufacture method of semiconductor devices of an alternative embodiment of the invention
Indicative flowchart.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is it is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, those skilled in the art be will fully convey the scope of the invention to and.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term limits.These terms be used merely to distinguish an element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., herein can for convenience description and by use from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, "one" and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, the presence or addition of element, part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
Herein with reference to the horizontal stroke of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view come describe invention embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or from the change of shown shape caused by tolerance.Therefore, embodiments of the invention should not limit to
Given shape in area shown here, but it is inclined including the shape caused by for example manufacturing
Difference.For example, be shown as the injection region of rectangle generally has circle at its edge or bending features and
/ or implantation concentration gradient, rather than the binary change from injection region to non-injection regions.Equally,
The surface passed through when by injecting the disposal area formed the disposal area and injection can be caused to carry out
Between area in some injection.Therefore, the area shown in figure is substantially schematical, it
Shape be not intended display device area true form and be not intended limit the present invention
Scope.
In order to thoroughly understand the present invention, will be proposed in following description detailed step and in detail
Thin structure, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is detailed
Carefully it is described as follows, but in addition to these detailed descriptions, the present invention can also have other implementations
Mode.
The present invention is in order to solve the problems, such as that current technique is present, there is provided a kind of semiconductor devices
Manufacture method, as shown in Fig. 2 methods described includes：
Step S201：The first substrate is provided, in the first surface side shape of first substrate
Into the radio frequency front-end devices including multiple transistors and the first interconnection structure, and positioned at the crystalline substance
The second interconnection structure on the outside of body pipe；
Step S202：The second substrate is provided, by bonding technology by second substrate and institute
The side that stating the formation of the first substrate has the radio frequency front-end devices engages；
Step S203：From the second surface relative with the first surface of first substrate
Side carries out reduction processing to first substrate to the first substrate thickness；
Step S204：In the second surface for the first substrate for being thinned to first substrate thickness
Form backside dielectric layer；
Wherein, 0.01 times in the transistor minimum feature size of first substrate thickness
Above and less than 10 times of the transistor maximum characteristic size.
In summary, manufacturing method according to the invention, by the way that substrate is thinned, improve
The radio-frequency performance and yield of devices of cmos device.The semiconductor devices of the present invention, due to
Above-mentioned manufacture method is employed, thus equally there is above-mentioned advantage.
Embodiment one
Below, reference picture 1A to Fig. 1 E and Fig. 2 proposes to describe the embodiment of the present invention
The detailed step of one illustrative methods of manufacture method of semiconductor devices.Wherein, 1A extremely schemes
1E is that a kind of correlation step of the manufacture method of semiconductor devices of the embodiment of the present invention is formed
The sectional view of structure；Fig. 2 is a kind of manufacture method of semiconductor devices of the embodiment of the present invention
Indicative flowchart.
The manufacture method of the semiconductor devices of the present embodiment, specifically comprises the following steps：
First, as shown in Figure 1A, there is provided the first substrate 100, in first substrate 100
First surface side formed and include the radio-frequency front-end of the interconnection structure 103 of transistor 102 and first
Device, and the second interconnection structure 105 positioned at the outside of transistor 102.
Specifically, the first substrate 100 is body silicon substrate, and it can be the following material being previously mentioned
At least one of：Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or
Other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc..
Wherein, in the first surface side of first substrate 100, the transistor 102
Formed with fleet plough groove isolation structure 101 in first substrate 100 of both sides.
The isolation of active device is realized using fleet plough groove isolation structure 101, for this area
The step of fleet plough groove isolation structure is formed for technical staff and defines active area is well known skill
Art means are not just described in detail herein, and any suitable method can be used to form trench isolations knot
Structure and definition active area.
Alternatively, the material filled in fleet plough groove isolation structure 101 can be silica, nitridation
One or more in silicon or silicon oxynitride.
As an example, it is also formed with radio-frequency devices on the first surface of the first substrate 100.
In the present embodiment, transistor 102 is used to form various circuits, and radio-frequency devices are used to form radio frequency
Component or module, the first interconnection structure 103 be used for connect transistor 102, radio-frequency devices and
Other assemblies in radio frequency front-end devices.Wherein, transistor 102 can be normal transistor,
High-k/metal gate transistors, fin transistor or other suitable transistors.First mutually links
Structure 103 can include metal level (such as layers of copper or aluminium lamination), through hole etc..Radio-frequency devices can be with
Including devices such as inductance (inductor).
The corresponding predetermined region for forming pad of second interconnection structure 105, wherein described second
Interconnection structure 105 include more metal layers (such as layers of copper or aluminium lamination) and adjacent metal it
Between through hole, wherein the bottom metal layer 1051 of second interconnection structure 105 is positioned at described
The top of the first surface of first substrate 100.
Alternatively, first interconnection structure 103 and second interconnection structure 105 include bottom
Portion's metal level, metal layer at top and the centre between bottom metal layers and metal layer at top
Metal level, different metal materials can be also used for each metal level, for example, bottom can be made
Metal level and the material of metal layer at top are copper, and the material of intermediate metal layer is aluminium.
In addition to including transistor 102, radio-frequency devices and the first interconnection structure 103, radio-frequency front-end
Device can also include other various feasible components, such as resistance, electric capacity, MEMS devices
Part etc., is not defined herein.
Alternatively, passive device is provided with the first surface of the first substrate, the passive device
Metal-insulating layer-metal capacitor (MIM) 104, spiral inductor etc. can be included.
Wherein, first interconnection structure 103 include bottom metal layers, metal layer at top and
Intermediate metal layer between bottom metal layers and metal layer at top, the gold among part is described
Belong on layer formed with the metal-insulating layer-metal capacitor 104, as shown in Figure 1A.
Wherein, the concrete structure and forming method of each component in radio frequency front-end devices, ability
The technical staff in domain can be selected according to being actually needed with reference to prior art, no longer superfluous herein
State.
Exemplarily, second interconnection structure 105 and first interconnection structure 103 can be same
When formed, its forming method can select conventional manufacture method, such as form dielectric layer, so
The dielectric layer is patterned afterwards, is open with being formed and is opened from described in conductive material filling
Mouthful, each metal level and through hole are sequentially formed, to form the interconnection structure, described in formation
Further dielectric layer after metal layer at top, to cover the metal layer at top and flat
Change, as shown in Figure 1A.
Wherein, the metal layer at top is from the heavy of metal material Cu, the metal material Cu
Product method can be chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or
Low-pressure chemical vapor deposition (LPCVD), the laser of the formation such as ald (ALD) method burn
One kind in erosion deposition (LAD) and selective epitaxy growth (SEG), it is preferably in the present invention
Physical vapour deposition (PVD) (PVD) method, it is possible to use method of electrochemical plating etc..
Further, bonding has also been can be selectively formed on the first surface of first substrate
Layer 106, wherein the bonded layer 106 selects oxide, such as from SiO2Deng not office
It is limited to the example.
Then, as shown in Figure 1B, there is provided the second substrate 200, in second substrate 200
The surface engaged with first substrate 100 on formed bonded layer 201.
In the present embodiment, the second substrate 200 is carrying substrate (carrier wafer), is used for
Held in the technique of reduction processing and other subsequent techniques are subsequently carried out to the first substrate 100
Carry and protect radio frequency front-end devices.Second substrate 200 its can use any Semiconductor substrate example
Such as silicon, or the ceramic bases of aluminum oxide etc., quartz or substrate of glass etc..
Bonded layer 201 can be any suitable film material used needed for bonding technology,
For example, the material of the bonded layer 201 be able to can be used with materials such as silica, silicon oxynitrides
Any method well known to those skilled in the art is formed, such as chemical vapour deposition technique, physics gas
Phase sedimentation or atomic layer deposition method etc..
Bonded layer 201 can also be the lamination of stratified film composition.
Then, as shown in Figure 1 C, by bonding technology by second substrate 200 with it is described
The side that the formation of first substrate 100 has the radio frequency front-end devices engages.
Exemplarily, bonded layer 106 and bonded layer 201 are directly contacted with each other, passes through bonding
The formation of the side of second substrate 200 and the first substrate 100 is had radio frequency front-end devices by technique
Side (i.e. first surface side) engages (bonding), as shown in Figure 1 C.Wherein, key
Closing technique can use any method well known to those skilled in the art to carry out, such as oxide fusion
Bonding technology etc..
Then, as shown in figure iD, from second relative with first surface of the first substrate 100
Surface side carries out reduction processing to the first substrate 200 to the first substrate thickness.
Wherein, the thickness of remaining first substrate 100 can be according to the reality of device after reduction processing
Border needs reasonably to be selected.According to the skill of radio-frequency front-end system and the RF transistors
Art requirement, first substrate thickness should be at 0.01 times of the transistor minimum feature size
More than, and at less than 10 times of the transistor maximum characteristic size；For example, included radio frequency
The channel length of switch CMOS transistor be 250 nanometers its be minimum feature size, then institute
Stating the first substrate thickness should be more than 2.5 nanometer, and included radio frequency high tension or power
The channel length of CMOS transistor be 2.0 microns its be maximum characteristic size, then described first
Substrate thickness should be below 20 microns.
Characteristic size refers to the minimum dimension in semiconductor devices.It is special in CMOS technology
Levy the width that size Typical Representative is " grid structure ", namely the channel length of MOS device.
Wherein, the multiple transistors formed in Semiconductor substrate in the present embodiment include difference
The transistor of type, such as RF switch CMOS transistor and radio frequency high tension or power CMOS
Transistor, the plurality of transistor take on a different character size, namely different channel lengths,
Therefore, minimum feature size refers to minimum channel length in the plurality of transistor, and maximum
Characteristic size refers to maximum channel length in the plurality of transistor.
Exemplarily, the first substrate 100 is body silicon substrate, and shallow ridges is provided with body silicon substrate
Recess isolating structure 101, the shallow trench isolation junction that the reduction processing is stopped in body silicon substrate
On structure 101.
The method of the reduction processing can use backgrind technique, chemically mechanical polishing
In (Chemical Mechanical Polishing, abbreviation CMP) or wet-etching technology
One or more, other suitable methods can also be used.
Wherein, backgrind technique has faster grinding rate, may be such that substrate is quickly subtracted
It is thin, in order to obtain smooth surface can also combine CMP and/or wet-etching technology realize for
First substrate 200 is thinned.
Wherein, when being body silicon substrate for the first substrate, by the reduction processing to body silicon substrate,
The RF performances of device can be improved.
Then, as referring to figure 1E, it is being thinned to the first substrate 100 of first substrate thickness
Second surface formed backside dielectric layer 107, in second table of first substrate 100
The formation of face side electrically connects logical with the bottom metal layers 1051 of second interconnection structure 105
Pore structure 108, pad 109 is formed on the part second surface of first substrate,
The pad 109 electrically connects 107 with the through-hole structure.
The material of backside dielectric layer 107 can include but is not limited to Si oxide or silicon nitride,
Such as SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC), silicon nitride (SiN) or
Carbonitride of silicium (SiCN) etc..Or it can also use and be formd on fluorocarbon (CF)
Film of SiCN films etc..Fluorocarbon is with fluorine (F) and carbon (C) for main component.Carbon fluorination is closed
Thing can also use the material constructed with noncrystal (amorphism).
The backside dielectric layer can be formed using any depositing operation well known to those skilled in the art
107, for example, chemical vapor deposition method, physical gas-phase deposition etc., wherein chemical gas
Phase depositing operation can select thermal chemical vapor deposition (thermal CVD) manufacturing process or highly dense
Spend plasma (HDP) manufacturing process.
Can be according to the suitable deposit thickness of size selection of the semiconductor devices of predetermined formation, herein
It is not especially limited.
Exemplarily, the method for forming through-hole structure 108 comprises the following steps：First, from institute
The second surface for stating the first substrate 100 starts, and is sequentially etched rear dielectric layers 107, shallow
Groove isolation construction 101 and part are located at the positive dielectric layer of fleet plough groove isolation structure, until
The bottom metal layers 1051 of second interconnection structure 105 described in expose portion, to form through hole knot
Structure opening.
Wherein, it is located at for rear dielectric layers 107, fleet plough groove isolation structure 101 and part
The etching of the positive dielectric layer of fleet plough groove isolation structure can use dry etching or adopt
Use wet etching.Dry etching can use the anisotropic etching method based on carbon fluoride gas.
Wet etching can use hydrofluoric acid solution, such as buffer oxide etch agent
(buffer oxide etchant (BOE)) or hydrofluoric acid cushioning liquid
(buffer solution of hydrofluoric acid (BHF)), etching stopping is in the described second interconnection
In the bottom metal layers 1051 of structure 105.
The through-hole structure opening is subsequently filled to form through-hole structure, wherein, the through hole knot
Structure 108 includes conductive layer, barrier layer and backing layer successively from inside to outside.
Wherein, conductive layer can be arbitrarily suitable conductive material, including but unlimited
In metal material, and one kind that metal material can be including Cu, Al or W etc. in metal or
It is several.
Pad 109 is used to signal or power supply passing through the second interconnection structure 105 and the first interconnection
Structure 103 is input to the inside of semiconductor devices.The material of pad 109 can be aluminium, copper or
Other suitable conductive materials.It can use and be sunk the methods of physical vapour deposition (PVD), chemical vapor deposition
Product is formed.
Then, in addition to step：Form the second surface for covering first substrate 100
But expose the passivation layer 110 in the routing area of the pad 109.
In one example, the second surface that covers first substrate 100 but sudden and violent is formed
Expose the passivation layer 110 in the routing area of the pad 105.
Passivation layer 110 is used to protect the first substrate 100 and pad 109.Passivation layer 110
Material can be silica, silicon nitride or other suitable materials.Chemical vapor deposition can be used
The methods of deposit to form passivation layer 110.
So far, Jie of the committed step of the manufacture method of the semiconductor devices of the present embodiment is completed
Continue.For complete device making method, it is also possible to need other previous steps, intermediate steps
Or subsequent step, then this does not repeat.
In summary, manufacturing method according to the invention, by the way that body silicon substrate is thinned,
The radio-frequency performance of cmos device is improved, and the production cost of device can be reduced.
Embodiment two
The embodiment of the present invention provides a kind of semiconductor devices, and it uses the system in previous embodiment one
The method of making prepares.The semiconductor devices, can be the collection for including radio frequency (RF) device
Into circuit or integrated circuit intermediate products.
Below, reference picture 1E come describe the embodiment of the present invention proposition semiconductor devices one kind
Structure.Wherein, Fig. 1 E are a kind of section view of the structure of the semiconductor devices of the embodiment of the present invention
Figure.
As referring to figure 1E, the semiconductor devices of the present embodiment includes：
First substrate 100, the first surface side of first substrate 100 formed with including
Radio frequency front-end devices of the interconnection structure 103 of transistor 102 and first and positioned at the transistor
Second interconnection structure 105 in 102 outsides, in first substrate 100 after being thinned
The second surface side relative with the first surface is formed with through-hole structure 108, the through hole
Structure 108 electrically connects with the bottom metal layers 1051 of second interconnection structure 105, in institute
State formation pad 109, the pad 109 on the part second surface of the first substrate 100
Electrically connected with the through-hole structure 108, and the second substrate 200 and first substrate are set
The side that 100 formation has the radio frequency front-end devices engages.
Specifically, the first substrate 100 is body silicon substrate, and it can be the following material being previously mentioned
At least one of：Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or
Other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc..
Wherein, it is described be thinned after the first substrate 100 there is the first substrate thickness, according to radio frequency
The technical requirements of front end system and the RF transistors, first substrate thickness should be
More than 0.01 times of the transistor minimum feature size, and in the transistor maximum feature chi
Very little less than 10 times；For example, the channel length of included RF switch CMOS transistor is
250 nanometers its be minimum feature size, then first substrate thickness should 2.5 nanometers with
On, and the channel length of included radio frequency high tension or power CMOS transistors be 2.0 microns its
For maximum characteristic size, then first substrate thickness should be below 20 microns.
Wherein, in the first surface side of first substrate 100, the transistor 102
Formed with fleet plough groove isolation structure 101 in first substrate 100 of both sides.
The isolation of active device is realized using fleet plough groove isolation structure 101, in Semiconductor substrate
Fleet plough groove isolation structure is formed in 200, forms shallow trench for a person skilled in the art
The step of isolation structure and definition active area is that well known technological means is not just described in detail herein,
Any suitable method can be used to form groove isolation construction and define active area.
Alternatively, the material filled in fleet plough groove isolation structure 101 can be silica, nitridation
One or more in silicon or silicon oxynitride.
As an example, it is also formed with radio-frequency devices on the first surface of the first substrate 100.
In the present embodiment, transistor 102 is used to form various circuits, and radio-frequency devices are used to form radio frequency
Component or module, the first interconnection structure 103 be used for connect transistor 102, radio-frequency devices and
Other assemblies in radio frequency front-end devices.Wherein, transistor 102 can be normal transistor,
High-k/metal gate transistors, fin transistor or other suitable transistors.First mutually links
Structure 103 can include metal level (such as layers of copper or aluminium lamination), through hole etc..Radio-frequency devices can be with
Including devices such as inductance (inductor).
The corresponding predetermined region for forming pad of second interconnection structure 105, wherein described second
Interconnection structure 105 include more metal layers (such as layers of copper or aluminium lamination) and adjacent metal it
Between through hole, wherein the bottom metal layer 1051 of second interconnection structure 105 is positioned at described
The top of the first surface of first substrate 100.
Alternatively, first interconnection structure 103 and second interconnection structure 105 include bottom
Portion's metal level, metal layer at top and the centre between bottom metal layers and metal layer at top
Metal level, different metal materials can be also used for each metal level, for example, bottom can be made
Metal level and the material of metal layer at top are copper, and the material of intermediate metal layer is aluminium.
In addition to including transistor 102, radio-frequency devices and the first interconnection structure 103, radio-frequency front-end
Device can also include other various feasible components, such as resistance, electric capacity, MEMS devices
Part etc., is not defined herein.
Alternatively, the passive device is provided with the first surface of the first substrate, this is passive
Device can include metal-insulating layer-metal capacitor (MIM) 104, spiral inductor etc..
Wherein, first interconnection structure 103 include bottom metal layers, metal layer at top and
Intermediate metal layer between bottom metal layers and metal layer at top, the gold among part is described
Belong on layer formed with the metal-insulating layer-metal capacitor 104, as referring to figure 1E.
Wherein, the concrete structure and forming method of each component in radio frequency front-end devices, ability
The technical staff in domain can be selected according to being actually needed with reference to prior art, no longer superfluous herein
State.
Wherein, second interconnection structure 105 and first interconnection structure 103 can shapes simultaneously
Conventional manufacture method can be selected into, its forming method, the second interconnection structure 105 and described
First interconnection structure 103 may be contained within dielectric layer.
Further, the formation of the second substrate 200 and first substrate 100 is set to have described
The side of radio frequency front-end devices engages, wherein, can be by the way that the second substrate 200 and first be served as a contrast
Bonded layer 201 is set on the surface that bottom engages, on the first surface of first substrate also
Bonded layer 106,106 direct contact-key of bonded layer 201 and bonded layer are can be selectively formed
Close, and then realize the engagement of the first substrate 100 and the second substrate 200.
Wherein described bonded layer 106 selects oxide, such as from SiO2Deng not limiting to
In the example.
Second substrate 200 its can use any Semiconductor substrate such as silicon, or aluminum oxide
Deng ceramic bases, quartz or substrate of glass etc..
Bonded layer 201 can be any suitable film material used needed for bonding technology,
For example, the material of the bonded layer 201 can be with the materials such as silica, silicon oxynitride, bonded layer
201 can also be the lamination of stratified film composition.
Further, shallow ridges is exposed in the second surface of first substrate 100 after being thinned
The back side of recess isolating structure 101.
Exemplarily, in the second table of the first substrate 100 for being thinned to first substrate thickness
Face is formed with backside dielectric layer 107, in first substrate 100 after being thinned and institute
The relative second surface side of first surface is stated formed with through-hole structure 108, the through-hole structure
108 electrically connect with the bottom metal layers 1051 of second interconnection structure 105, described
Pad 109, the pad 109 and institute are formed on the part second surface of one substrate 100
State through-hole structure 108 to electrically connect, and the second substrate 200 and first substrate 100 are set
Side formed with the radio frequency front-end devices engages.
Wherein, the material of backside dielectric layer 107 can include but is not limited to Si oxide or silicon nitrogen
Compound, such as SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC), silicon nitride (SiN),
Or carbonitride of silicium (SiCN) etc..Or it can also use and be formd on fluorocarbon (CF)
Film of SiCN films etc..Fluorocarbon is with fluorine (F) and carbon (C) for main component.Carbon fluorination is closed
Thing can also use the material constructed with noncrystal (amorphism).
Wherein, the through-hole structure 108 includes conductive layer, barrier layer and lining successively from inside to outside
Nexine.
Wherein, conductive layer can be arbitrarily suitable conductive material, including but unlimited
In metal material, and one kind that metal material can be including Cu, Al or W etc. in metal or
It is several.
Exemplarily, through-hole structure 108 sequentially passes through since the second surface of the first substrate
Backside dielectric layer 107, fleet plough groove isolation structure 101, positioned at fleet plough groove isolation structure 101 just
The dielectric layer in face until directly being contacted with the bottom metal layers 1051 of the second interconnection structure 105 and
Electrical connection.
Pad 109 is used to signal or power supply passing through the second interconnection structure 105 and the first interconnection
Structure 103 is input to the inside of semiconductor devices.The material of pad 109 can be aluminium, copper or
Other suitable conductive materials.Exemplarily, set and cover the described of first substrate 100
Second surface but the passivation layer 110 for exposing the routing area of the pad 109.
Passivation layer 110 is used to protect the first substrate 100 and pad 109.Passivation layer 110
Material can be silica, silicon nitride or other suitable materials.Chemical vapor deposition can be used
The methods of deposit to form passivation layer 110.
The semiconductor devices of the present invention, is obtained as a result of the manufacture method in previous embodiment one
, thus equally there are aforementioned advantages.
The semiconductor devices of the present embodiment, can be RF front-end module or other circuits or mould
Block.Because the radio-frequency performance of the semiconductor devices gets a promotion, thus can meet more to apply
To the demand of device performance under environment.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modifications can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of manufacture method of semiconductor devices, it is characterised in that methods described includes：
The first substrate is provided, being formed in the first surface side of first substrate includes multiple crystalline substances
The radio frequency front-end devices of body pipe and the first interconnection structure, and on the outside of the transistor
Two interconnection structures；
The second substrate is provided, by bonding technology by second substrate and first substrate
Side formed with the radio frequency front-end devices engages；
From the second surface side relative with the first surface of first substrate to described
First substrate carries out reduction processing to the first substrate thickness；
The back side is formed in the second surface for being thinned to the first substrate of first substrate thickness to be situated between
Electric layer；
Wherein, 0.01 times in the transistor minimum feature size of first substrate thickness
Above and less than 10 times of the transistor maximum characteristic size.
2. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that
First substrate in the first surface side of first substrate, the both sides of the transistor
In formed with fleet plough groove isolation structure.
3. the manufacture method of semiconductor devices as claimed in claim 2, it is characterised in that
The reduction processing is stopped on the fleet plough groove isolation structure.
4. the manufacture method of the semiconductor devices as described in claim 1 or 3, its feature exists
In further comprising the steps of after the backside dielectric layer is formed：
Formed and second interconnection structure in the second surface side of first substrate
Bottom metal layers electrical connection through-hole structure；
Pad, the pad and institute are formed on the part second surface of first substrate
State through-hole structure electrical connection.
5. the manufacture method of semiconductor devices as claimed in claim 4, it is characterised in that
After the pad is formed, in addition to step：
Form the second surface for covering first substrate but expose beating for the pad
The passivation layer in line area.
6. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that
First substrate is body silicon substrate.
7. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that
The method of the reduction processing uses backgrind technique, chemically mechanical polishing or wet etching
One or more in technique.
8. manufacture method as claimed in claim 1, it is characterised in that first interconnection
Structure includes bottom metal layers, metal layer at top and positioned at bottom metal layers and metal layer at top
Between intermediate metal layer, formed with metal-insulator-gold on the intermediate metal layer of part
Belong to electric capacity.
9. manufacture method as claimed in claim 1, it is characterised in that carrying out the key
Before closing technique, formed on the surface engaged with first substrate of second substrate
Bonded layer.
10. a kind of semiconductor devices, it is characterised in that using such as one of claim 1 to 9
Described method, which makes, obtains the semiconductor devices.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112782558A (en) * | 2020-12-29 | 2021-05-11 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Method for acquiring failure rate of integrated circuit |
| JP2021536679A (en) * | 2018-09-07 | 2021-12-27 | エルファウンドリー エッセ．エッレ．エッレ | How to make a built-in spiral inductor with low board loss |
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| US20130147061A1 (en) * | 2010-12-24 | 2013-06-13 | Io Semiconductor, Inc. | Trap Rich Layer with Through-Silicon-Vias in Semiconductor Devices |
| CN105448898A (en) * | 2014-07-28 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof and electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130147061A1 (en) * | 2010-12-24 | 2013-06-13 | Io Semiconductor, Inc. | Trap Rich Layer with Through-Silicon-Vias in Semiconductor Devices |
| CN105448898A (en) * | 2014-07-28 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof and electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2021536679A (en) * | 2018-09-07 | 2021-12-27 | エルファウンドリー エッセ．エッレ．エッレ | How to make a built-in spiral inductor with low board loss |
| CN112782558A (en) * | 2020-12-29 | 2021-05-11 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Method for acquiring failure rate of integrated circuit |
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