CN107368635A - The method for detecting low pressure well region and high-pressure trap area hybrid junction - Google Patents
The method for detecting low pressure well region and high-pressure trap area hybrid junction Download PDFInfo
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- CN107368635A CN107368635A CN201710543028.3A CN201710543028A CN107368635A CN 107368635 A CN107368635 A CN 107368635A CN 201710543028 A CN201710543028 A CN 201710543028A CN 107368635 A CN107368635 A CN 107368635A
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- well region
- low pressure
- trap area
- pressure well
- hybrid junction
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 238000001514 detection method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A kind of method for detecting low pressure well region and high-pressure trap area hybrid junction provided by the invention, including：Circuit layout is obtained, the circuit layout has low pressure well region and high-pressure trap area；Judge whether there is device in the low pressure well region；When in the low pressure well region without device, detect between the metal interconnecting wires on the metal interconnecting wires and the high-pressure trap area on the low pressure well region with the presence or absence of being electrically connected with, if there is electric connection, the low pressure well region and the high-pressure trap area hybrid junction in the metal interconnecting wires with layer.In the present invention, when having device in low pressure well region, low pressure well region directly can be detected by channel check and whether there is hybrid junction with high-pressure trap area, when not having device in low pressure well region, by judging that the connection of metal interconnecting wires detects connection error between low pressure well region and high-pressure trap area, flow failure risk is avoided.
Description
Technical field
The present invention relates to semiconductor integrated circuit technical field, more particularly to a kind of detection low pressure well region and high-pressure trap area to mix
The method connect.
Background technology
Electric design automation (Electronic Design Automation, EDA) means to design using computer
And the performance of the electronic circuit on Integration of Simulation circuit, EDA, which has been proceeded to, can handle the semiconductor integrated circuit for making excessive demands complexity
Design work.In the integrated circuit designed and physically by the circuit layout well after, the checking integrated electricity need to be tested
Whether road correctly works.In existing IC design, it can detect that the connection between each part of circuit is closed by EDA
System.
In device manufacturing processes, layout design is carried out to device, technique manufacture is carried out according to domain, manufactured in technique
Cheng Zhong, due to various process equipments, the reason such as deviation of process conditions, cause to exist between the structure of device and layout design
Enter, for example, being attached to well region in back segment manufacturing process, it may appear that asking for the high potential of high-pressure trap area of low pressure well region hybrid junction
Topic, the problems such as causing device breakdown.
The content of the invention
It is an object of the present invention to provide a kind of method for detecting low pressure well region and high-pressure trap area hybrid junction, solves existing skill
Art can not detect the technical problem of low pressure well region and high-pressure trap area.
In order to solve the above technical problems, the present invention provides a kind of method for detecting low pressure well region and high-pressure trap area hybrid junction, bag
Include：
Circuit layout is obtained, the circuit layout has low pressure well region and high-pressure trap area；
Judge whether there is device in the low pressure well region；
When in the low pressure well region without device, the metal interconnecting wires on the low pressure well region and the high-pressure trap area are detected
On metal interconnecting wires between with the presence or absence of be electrically connected with, if with layer metal interconnecting wires exist be electrically connected with, the low pressure
Well region and the high-pressure trap area hybrid junction.
Optionally, the low pressure well region is N-type well region.
Optionally, the high-pressure trap area is N-type well region.
Optionally, the low pressure well region and the high-pressure trap area are adjacent to each other, and physically separate.
Optionally, when judging whether to there is device in the low pressure well region, if active area and polycrystalline in the low pressure well region
Silicon has overlapping, then has device in the low pressure well region；If active area does not have overlapping with polysilicon in the low pressure well region,
Then do not have device in the low pressure well region.
Optionally, when having device in the low pressure well region, the electric current of the circuit layout is emulated, when electric current is more than standard
During electric current, the low pressure well region and the high-pressure trap area hybrid junction.
Optionally, there is PMOS transistor, and lining of the low pressure well region as PMOS transistor in the low pressure well region
Bottom picks out.
Optionally, there are 3~6 layers of metal interconnecting wires on the low pressure well region, pass through between the metal interconnecting wires of adjacent layer
Through hole is electrically connected with.
Optionally, there are 3~6 layers of metal interconnecting wires on the high-pressure trap area, pass through between the metal interconnecting wires of adjacent layer
Through hole is electrically connected with.
Compared with prior art, in the method for detection low pressure well region of the invention and high-pressure trap area hybrid junction, when the low pressure
When there is device in well region, the electric current of artificial circuit domain, when electric current is bigger than normalized current, the low pressure well region and the height
Press well region hybrid junction；When in the low pressure well region without device, the metal interconnecting wires on the low pressure well region and the high pressure are detected
With the presence or absence of being electrically connected between metal interconnecting wires on well region, it is electrically connected with if existing, the low pressure well region and the height
Press well region hybrid junction.In the present invention, when having device in low pressure well region, can directly by channel check detect low pressure well region with
High-pressure trap area whether there is hybrid junction, when not having device in low pressure well region, by judging the connections of metal interconnecting wires by low pressure trap
Connection error detects between area and high-pressure trap area, avoids flow failure risk.
Brief description of the drawings
Fig. 1 is the method flow diagram that low pressure well region and high-pressure trap area hybrid junction are detected in one embodiment of the invention；
Fig. 2 is the electrical block diagram that one embodiment of the invention mesolow well region has transistor；
Fig. 3 is the connection diagram of the metal interconnecting wires of one embodiment of the invention mesolow well region and high-pressure trap area.
Embodiment
The detection low pressure well region of the present invention and the method for high-pressure trap area hybrid junction are carried out below in conjunction with schematic diagram more detailed
Description, which show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change described here
The present invention, and still realize the advantageous effects of the present invention.Therefore, description below is appreciated that for those skilled in the art
It is widely known, and be not intended as limitation of the present invention.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expended
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The core concept of the present invention is, there is provided the method for detection low pressure well region and high-pressure trap area hybrid junction, when the low pressure
When there is device in well region, the electric current of artificial circuit domain, when electric current is bigger than normalized current, the low pressure well region and the height
Press well region hybrid junction；When in the low pressure well region without device, the metal interconnecting wires on the low pressure well region and the high pressure are detected
With the presence or absence of being electrically connected between metal interconnecting wires on well region, it is electrically connected with if existing, the low pressure well region and the height
Press well region hybrid junction.In the present invention, when having device in low pressure well region, can directly by channel check detect low pressure well region with
High-pressure trap area whether there is hybrid junction, when not having device in low pressure well region, by judging the connections of metal interconnecting wires by low pressure trap
Connection error detects between area and high-pressure trap area, avoids flow failure risk.
Carried out specifically below in conjunction with the method for accompanying drawing 1~3 pair of detection low pressure well region and high-pressure trap area hybrid junction of the invention
Bright, Fig. 1 is the flow chart of detection method, and Fig. 2~3 are that low pressure well region detects embodiments, the present invention with the presence or absence of the different of device
Detection method comprise the following steps：
Step S1 is performed, circuit layout is obtained, there is low pressure well region (Low Voltage Well) in the circuit layout
With high-pressure trap area (High Voltage Well), in the present embodiment, using the low pressure well region as N-type well region (Low
Voltage N Well, LVNW), the high-pressure trap area be N-type well region (High Voltage N WellHVNW) exemplified by said
It is bright.Certainly low pressure well region and the high-pressure trap area can also be P type trap zone described in the other embodiment of the present invention.Also, institute
State low pressure well region LVNW and the high-pressure trap area HVNW be adjacent to each other, and physically separate, the low pressure well region LVNW and
It can be separated between the high-pressure trap area HVNW by fleet plough groove isolation structure STI.
Step S2 is performed, judges whether there is device in the low pressure well region LVNW, when LVNW has in the low pressure well region
When having device, emulate the electric current of the circuit layout, when the electric current ratio is more than normalized current, the low pressure well region LVNW with it is described
High-pressure trap area HVNW connections.When judging whether to there is device in the low pressure well region, if active area (ACT) in the low pressure well region
With polysilicon (Poly) have it is overlapping, then there is device in the low pressure well region；If active area and polycrystalline in the low pressure well region
Silicon does not then have device without overlapping in the low pressure well region.
In the present embodiment, illustrated exemplified by there is PMOS transistor in the low pressure well region LVNW, with reference to the institute of figure 2
Show that there is PMOS transistor, the source electrode connection power end of PMOS transistor, one NMOS of drain electrode connection in the low pressure well region LVNW
The drain electrode of transistor, grid are connected with the grid of the nmos pass transistor, the source electrode connection ground terminal of nmos pass transistor, and described low
Pressure well region LVNW picks out as the substrate of PMOS transistor.When pair pmos transistor and nmos pass transistor are emulated, if
The source current Id of PMOS transistor increases suddenly, more than PMOS transistor normalized current when, then the substrate of PMOS transistor
High potential is connect, i.e., hybrid junction occurs in described low pressure well region LVNW and high-pressure trap area HVNW.When having device in low pressure well region LVNW
During part structure, hybrid junction directly can determine whether by the current detecting of the device, it is simple and easy.In addition, work as low pressure trap
When device be present in area LVNW, can also by by circuit layout compared with circuit structure, so that it is determined that low pressure well region
LVNW whether with high-pressure trap area hybrid junction
Step S3 is performed, when in the low pressure well region LVNW without device, detects the metal on the low pressure well region LVNW
The annexation between metal interconnecting wires on interconnection line and the high-pressure trap area HVNW, if the gold on the low pressure well region LVNW
Same layer metal interconnecting wires between category interconnection line and the metal interconnecting wires on the high-pressure trap area HVNW are when overlapping being present, then institute
Low pressure well region LVNW is stated to be connected with the high-pressure trap area HVNW.Specifically, with reference to shown in figure 3, found out in circuit layout described
Metal interconnecting wires on low pressure well region LVNW, the low pressure well region LVNW have 3~6 layers of metal interconnecting wires, for example, with M1, M2,
M3, M4, M5 totally five layers of metal interconnecting wires, it is electrically connected with by through hole MV1, MV2, MV3, MV4 between every layer of metal interconnecting wires, and
And metal interconnecting wires M1 is connected by through hole CONT with the pad NTAP in substrate.Likewise, found out in circuit layout described
Metal interconnecting wires on high-pressure trap area HVNW, the high-pressure trap area HVNW have 3~6 layers of metal interconnecting wires, for example, with M1 ',
M2 ', M3 ', M4 ', M5 ' totally five layers of metal interconnecting wires, pass through through hole between every layer of metal interconnecting wires M1 ', M2 ', M3 ', M4 ', M5 '
MV1 ', MV2 ', MV3 ', MV4 ' connections, also, metal interconnecting wires M1 ' are connected by the pad NTAP ' in through hole CONT ' and substrate
Connect, the device in high-pressure trap area HVNW is drawn.In detection process, using low pressure well region LVNW top-level metallic interconnection line M5 as one
Node Node1, with high-pressure trap area HVNW top-level metallic interconnection line M5 ' for another node Node2, as long as the metal in device is mutual
Exist between line M1, M2, M3, M4, M5 and metal interconnecting wires M1 ', M2 ', M3 ', M4 ', M5 ' same layer metal exist it is overlapping,
That is, exist between metal interconnecting wires M1, M2, M3, M4, M5 and metal interconnecting wires M1 ', M2 ', M3 ', M4 ', M5 ' a certain
The situation that layer is electrically connected with, that is, low pressure well region LVNW and high-pressure trap area HVNW is caused to produce hybrid junction, so as to which the low pressure well region be entered
Line flag, the design to the low pressure well region is prompted to modify.
In summary, the method for detection low pressure well region and high-pressure trap area hybrid junction provided by the invention, when the low pressure well region
It is interior when there is device, the electric current of artificial circuit domain, when electric current is bigger than normalized current, the low pressure well region and the high pressure trap
Area's hybrid junction；When in the low pressure well region without device, the metal interconnecting wires on the low pressure well region and the high-pressure trap area are detected
On metal interconnecting wires between with the presence or absence of being electrically connected with, be electrically connected with if existing, the low pressure well region and the high pressure trap
Area's hybrid junction.In the present invention, when having device in low pressure well region, low pressure well region and high pressure directly can be detected by channel check
Well region whether there is hybrid junction, when not having device in low pressure well region, by judge the connections of metal interconnecting wires by low pressure well region and
Connection error detects between high-pressure trap area, avoids flow failure risk.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (9)
- A kind of 1. method for detecting low pressure well region and high-pressure trap area hybrid junction, it is characterised in that including：Circuit layout is obtained, the circuit layout has low pressure well region and high-pressure trap area；Judge whether there is device in the low pressure well region；When in the low pressure well region without device, detect on metal interconnecting wires and the high-pressure trap area on the low pressure well region With the presence or absence of being electrically connected between metal interconnecting wires, if electric connection, the low pressure well region be present in the metal interconnecting wires with layer With the high-pressure trap area hybrid junction.
- 2. the method for detection low pressure well region and high-pressure trap area hybrid junction as claimed in claim 1, it is characterised in that the low pressure trap Area is N-type well region.
- 3. the method for detection low pressure well region and high-pressure trap area hybrid junction as claimed in claim 1, it is characterised in that the high pressure trap Area is N-type well region.
- 4. the method for detection low pressure well region and high-pressure trap area hybrid junction as claimed in claim 1, it is characterised in that the low pressure trap Area and the high-pressure trap area are adjacent to each other, and physically separate.
- 5. the method for detection low pressure well region and high-pressure trap area hybrid junction as claimed in claim 1, it is characterised in that judge described low When whether there is device in pressure well region, if active area has overlapping, the low pressure well region with polysilicon in the low pressure well region In there is device；If active area does not have overlapping with polysilicon in the low pressure well region, do not have device in the low pressure well region Part.
- 6. the method for detection low pressure well region and high-pressure trap area hybrid junction as claimed in claim 1, it is characterised in that when the low pressure When there is device in well region, emulate the electric current of the circuit layout, when electric current is more than normalized current, the low pressure well region with it is described High-pressure trap area hybrid junction.
- 7. the method for detection low pressure well region and high-pressure trap area hybrid junction as claimed in claim 6, it is characterised in that the low pressure trap There is PMOS transistor, and the low pressure well region picks out as the substrate of PMOS transistor in area.
- 8. the method for detection low pressure well region and high-pressure trap area hybrid junction as claimed in claim 1, it is characterised in that the low pressure trap There are 3~6 floor metal interconnecting wires in area, be electrically connected between the metal interconnecting wires of adjacent layer by through hole.
- 9. the method for detection low pressure well region and high-pressure trap area hybrid junction as claimed in claim 1, it is characterised in that the high pressure trap There are 3~6 floor metal interconnecting wires in area, be electrically connected between the metal interconnecting wires of adjacent layer by through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710543028.3A CN107368635B (en) | 2017-07-05 | 2017-07-05 | Method for detecting mixed connection of low-voltage well region and high-voltage well region |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710543028.3A CN107368635B (en) | 2017-07-05 | 2017-07-05 | Method for detecting mixed connection of low-voltage well region and high-voltage well region |
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| Publication Number | Publication Date |
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| CN107368635A true CN107368635A (en) | 2017-11-21 |
| CN107368635B CN107368635B (en) | 2021-07-02 |
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