CN107356818B - Duty ratio detection method and circuit, driving circuit and mobile terminal - Google Patents
Duty ratio detection method and circuit, driving circuit and mobile terminal Download PDFInfo
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Abstract
A duty ratio detection method, a circuit, a driving circuit and a mobile terminal are provided, wherein the duty ratio detection method comprises the following steps: converting the PWM signal into an electrical signal, the amplitude of the electrical signal being proportional to the duty cycle of the PWM signal; quantizing the amplitude of the electrical signal to obtain a target digital code; and determining the duty ratio of the PWM signal by utilizing the proportion of the value represented by the target digital code to the full scale value during quantization. By adopting the technical scheme of the invention, the detection precision and range of the signal duty ratio can be effectively improved, so that the minimum dimming brightness and dimming consistency of the mobile terminal are optimized.
Description
Technical Field
The invention relates to the technical field of PWM dimming, in particular to a duty ratio detection method and circuit, a driving circuit and a mobile terminal.
Background
Pulse-Width Modulation (PWM) is a technique for controlling an analog circuit using the digital output of a microprocessor. Because the duty ratio of the PWM signal is accurate and adjustable, the PWM signal is widely applied to the electronic field and the industrial control field and is used for controlling output voltage, current or other parameters. PWM dimming techniques are typically accomplished by using a PWM signal to regulate the forward current in the light emitting diode.
Nowadays, a mobile phone has become a powerful personal mobile multimedia terminal, not only a data communication device providing voice and simple Short Message Service (SMS). With the increase of the mobile phone screen, people have higher requirements on the color and the fineness of the screen, which means that the requirements on the backlight driving chip are higher and higher. The backlight chip adjusts the driving current of the light-emitting device by controlling the duty ratio of the PWM signal so as to adjust the light-emitting brightness of the mobile phone. The inductance boost type backlight drive has the advantages of good current matching degree of the light emitting diode, few interface connecting lines with a screen and the like, so that mobile phone designers select the large-size backlight drive of the smart phone. The traditional backlight driving chip is limited by the process and the circuit design, and generally can only support the minimum dimming brightness of 3% -5%, and the lower brightness can cause the screen of the mobile phone to be turned off or flickered. In a low-brightness environment, human eyes are more sensitive to the brightness of a screen, and therefore, higher requirements are made on the lowest brightness and consistency which can be supported by the backlight driving chip. Currently, the backlight driving chip of the international factory can support the minimum dimming brightness of 0.2%, which means that the backlight driving chip is required to be able to accurately recognize the PWM signal with the duty ratio as low as 0.2%.
In the prior art, the duty ratio of the PWM signal is mostly detected by adopting a mode of counting the PWM signal by using a high-speed clock, the detection precision of the mode depends on the frequency of the high-speed clock and the frequency of the PWM signal, and in the prior art, the high-precision detection of the PWM signal with the duty ratio as low as 0.2% is difficult to realize.
Therefore, in the prior art, detection accuracy for the duty ratio of the PWM signal needs to be improved to meet higher requirements for minimum brightness and consistency of backlight driving in the mobile terminal.
Disclosure of Invention
The invention solves the technical problem of how to improve the detection precision of the duty ratio of the PWM signal.
In order to solve the above technical problem, an embodiment of the present invention provides a duty ratio detection method, where the duty ratio detection method includes: converting the PWM signal into an electrical signal, the amplitude of the electrical signal being proportional to the duty cycle of the PWM signal; quantizing the amplitude of the electrical signal to obtain a target digital code; and determining the duty ratio of the PWM signal by utilizing the proportion of the value represented by the target digital code to the full scale value during quantization.
Optionally, the electrical signal is a voltage signal or a current signal.
Optionally, the electrical signal is a voltage signal; the quantizing the amplitude of the electrical signal to obtain the target digital code comprises: taking the reference voltage as a reference, and generating corresponding conversion voltage by using a digital-to-analog converter under the action of different digital codes; and respectively comparing the amplitude of the voltage signal with each conversion voltage to obtain a comparison result, wherein when the comparison result indicates that the amplitudes of the conversion voltage and the voltage signal are equal, the digital code corresponding to the conversion voltage is the target digital code.
Optionally, the switching voltage is varied in an increasing or decreasing order; when the comparison result indicates that the converted voltage and the amplitude of the voltage signal are equal, the digital code corresponding to the converted voltage is the target digital code, and the method comprises the following steps: in two adjacent comparisons, when the logic levels of the comparison results are opposite, one of the digital codes corresponding to the conversion voltage adopted in the two comparisons is selected as the target digital code.
Optionally, the determining the duty cycle of the PWM signal using the ratio of the value characterized by the target digital code to the full scale value when quantized comprises: and determining the duty ratio of the PWM signal according to the ratio of the value represented by the potential value when the PWM signal is at a logic high level and a logic low level, the reference voltage and the target digital code to the full-scale value of the digital-to-analog converter.
Optionally, when the potential value of the logic low level of the PWM signal is 0V, and the potential value of the logic high level of the PWM signal is equal to the reference voltage, the ratio of the value represented by the target digital code to the full-scale value of the digital-to-analog converter is equal to the duty ratio of the PWM signal.
Optionally, the electrical signal is a voltage signal; the quantizing the amplitude of the electrical signal to obtain the target digital code comprises: and quantizing the amplitude of the voltage signal by using an analog-to-digital converter by taking the reference voltage as a reference so as to obtain the target digital code.
In order to solve the above technical problem, an embodiment of the present invention further provides a duty ratio detection circuit, where the duty ratio detection circuit includes: the conversion module is suitable for converting the PWM signal into an electric signal, and the amplitude of the electric signal is in direct proportion to the duty ratio of the PWM signal; the quantization module is accessed to the reference electric signal and the electric signal and is suitable for quantizing the amplitude of the electric signal to obtain a target digital code; a processor adapted to determine the duty cycle of the PWM signal using the ratio of the value characterized by the target digital code to the full scale value of the quantization module.
Optionally, the electrical signal is a voltage signal or a current signal.
Optionally, the electrical signal is a voltage signal; the quantization module comprises: the digital-to-analog converter is suitable for generating corresponding conversion voltages under the action of different digital codes and outputting the conversion voltages through output ends of the digital-to-analog converter; and the comparator is suitable for respectively comparing the amplitude of the voltage signal with each conversion voltage to obtain a comparison result, and when the comparison result indicates that the amplitudes of the conversion voltage and the voltage signal are equal, the digital code corresponding to the conversion voltage is the target digital code.
Optionally, the processor is adapted to generate respective digital codes such that the converted voltages vary in an increasing or decreasing order; in two adjacent comparisons, when the logic levels of the comparison results are opposite, one of the digital codes corresponding to the conversion voltage adopted in the two comparisons is the target digital code.
Optionally, the processor is adapted to determine the duty cycle of the PWM signal according to the ratio of the value represented by the reference voltage, the target digital code, and the potential value of the PWM signal at the logic high level and the logic low level to the full scale value of the digital-to-analog converter.
Optionally, when the potential value of the logic low level of the PWM signal is 0V, and the potential value of the logic high level of the PWM signal is equal to the reference voltage, the ratio of the value represented by the target digital code to the full-scale value of the digital-to-analog converter is equal to the duty ratio of the PWM signal.
Optionally, the electrical signal is a voltage signal; the quantization module comprises: and the reference end of the analog-to-digital converter is connected with a reference voltage, and the analog-to-digital converter is suitable for quantizing the amplitude of the voltage signal to obtain the target digital code.
Optionally, the conversion module comprises: a low pass filter adapted to convert the PWM signal to the voltage signal.
To solve the above technical problem, an embodiment of the present invention further provides a driving circuit, where the driving circuit includes: the duty ratio detection circuit; and the driving current generation circuit is directly or indirectly coupled with the duty ratio detection circuit and is suitable for generating driving current according to the obtained duty ratio of the PWM signal.
In order to solve the above technical problem, an embodiment of the present invention further provides a mobile terminal, where the mobile terminal includes: the above-described drive circuit; an array of light emitting devices adapted to emit light under the drive of the drive current; and the display screen is suitable for displaying by taking the light emitting device array as a background light source.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a duty ratio detection method, which comprises the steps of converting a PWM signal into an electric signal, quantizing the amplitude of the electric signal to obtain a target digital code, and determining the duty ratio of the PWM signal by utilizing the ratio of a numerical value represented by the target digital code to a full-scale numerical value during quantization. According to the embodiment of the invention, the duty ratio detection precision of the PWM signal can be improved by improving the quantization precision of the electric signal. For example, when the quantization resolution is 10 bits, the minimum duty cycle that can be detected is about 0.098%. Compared with the prior art, the embodiment of the invention does not need to improve the duty ratio detection precision by improving the clock frequency or reducing the PWM signal frequency, reduces the detection complexity, is easy to implement, and can effectively improve the detection precision and range of the signal duty ratio, so that the minimum dimming brightness and the dimming consistency of the mobile terminal applying the duty ratio detection method of the embodiment are optimized.
Drawings
Fig. 1 is a schematic diagram of a duty cycle detection method in the prior art.
Fig. 2 is a flowchart of a duty ratio detection method according to an embodiment of the present invention.
Fig. 3 is a schematic structural block diagram of a duty ratio detection circuit according to an embodiment of the present invention.
Fig. 4 is a schematic block diagram of another duty cycle detection circuit according to an embodiment of the present invention.
Detailed Description
As described in the background section, in the prior art, the duty ratio of the PWM signal is often detected by counting the PWM signal with the high-speed clock, the detection accuracy of the method depends on the frequency of the high-speed clock and the frequency of the PWM signal itself, and in the prior art, it is difficult to achieve high-accuracy detection of the PWM signal with the duty ratio as low as 0.2%.
The present inventors further analyzed the prior art scheme. Referring to fig. 1, in the duty ratio detection method in the prior art, a high-speed clock CLK is mostly used to count time lengths of a logic high level and a logic low level of an input PWM signal P, respectively, and then the time lengths of the logic high level and the logic low level of the PWM signal P are calculated according to a count result and a frequency of the high-speed clock CLK, and a time length of a whole period occupied by the high level is calculated, that is, a duty ratio of the PWM signal P is calculated. Specifically, first, the time lengths of the logic high level and the logic low level of the PWM signal P are recognized, which may be converted into the single pulse signals PWMH and PWML in fig. 1; then, the counter 1 is adopted to count the high-speed clock CLK when the single pulse signal PWMH is at a logic high level, and the counter 2 is adopted to count the high-speed clock CLK when the single pulse signal PWML is at a logic high level; finally, the counting results of the two counters are transmitted to the digital signal processor 10, and the duty ratio of the PWM signal P is calculated by the digital signal processor.
The duty ratio detection accuracy depends on the frequency of the PWM signal P itself and the frequency of the high-speed clock CLK, wherein the higher the frequency of the high-speed clock CLK is, and/or the lower the frequency of the PWM signal P is, the higher the duty ratio detection accuracy is.
Assuming that the frequency of the PWM signal P to be detected is 100kHz and the minimum value of the duty ratio is 0.2%, if it is to be identified, the time length 1/100kHz × 0.2% of the logic high level needs to be counted (or referred to as sampling) for 20 ns. The frequency of the high-speed clock CLK used for sampling needs to be at least 2 × 1/20 ns-100 MHz according to Nyquist's law. For a common integrated circuit process, a clock of 100MHz has difficulty in realization, and the pressure of the frequency of the high-speed clock CLK on circuit design is further improved; while reducing the frequency of the PWM signal P itself may result in a too slow response speed of the circuit, especially in mobile terminals.
From the above analysis, it can be known that in the prior art, the detection accuracy for the duty ratio of the PWM signal needs to be improved to meet higher requirements for the minimum brightness and consistency of the backlight driving in the mobile terminal.
In view of the above technical problems, an embodiment of the present invention provides a duty ratio detection method, which can effectively improve detection accuracy of a signal duty ratio, so as to optimize minimum dimming brightness and dimming consistency of a mobile terminal.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The embodiment of the invention provides a duty ratio detection method, which can be used in a mobile terminal. Specifically, the method can be used in a driving circuit of the mobile terminal, and the driving circuit adjusts the display brightness of the mobile terminal according to the duty ratio detection result.
As shown in fig. 2, the duty cycle detection method may include the steps of:
step S101, converting a PWM signal into an electric signal, wherein the amplitude of the electric signal is in direct proportion to the duty ratio of the PWM signal;
step S102, quantizing the amplitude of the electric signal to obtain a target digital code;
and step S103, determining the duty ratio of the PWM signal by utilizing the proportion of the numerical value represented by the target digital code to the full-scale numerical value during quantization.
The embodiment of the invention abandons the mode of detecting the duty ratio of the PWM signal by adopting high-speed clock counting in the prior art, and converts the duty ratio into electrical quantity for indirect measurement. In a specific implementation, the electrical signal may be a voltage signal or a current signal.
Preferably, the electrical signal is a voltage signal. In step S101, a low-pass filter with a low cut-off frequency may be used to convert the PWM signal into a voltage signal. For example, in the step S102, the quantization of the electrical signal (i.e., the voltage signal) may be implemented by a suitable quantization device or device, such as an Analog-to-Digital Converter (ADC). When the electrical signal is a current signal, it may be quantified using a corresponding current collection device or apparatus. Specifically, the current signal may be converted into a voltage signal through a conversion resistor, and then the voltage signal may be quantized.
The embodiment of the invention can determine the duty ratio of the PWM signal by utilizing the proportion of the numerical value represented by the target digital code to the full-scale numerical value during quantization. For example, when the electrical signal is a voltage signal, its amplitude is quantized by a 10-bit ADC, assuming that the target number of the ADC output is 1010100101, which characterizes a value of 677, and the full-scale of the ADC is 1111111111, which has a full-scale value of 2101023, the duty cycle of the PWM signal can therefore be determined with 677/1023 66.18%. A quantization accuracy of 10 bits means that the minimum duty cycle that can be detected is about (1/2)10-1) ≈ 0.098%. As the sampling resolution of the ADC increases to 12 bits or even higher, the minimum duty cycle that can be identified is correspondingly smaller.
Further, for the current Complementary Metal Oxide Semiconductor (CMOS) process, the quantization resolution of 10 bits or more of the quantization device or apparatus is not difficult to achieve, and can at least achieve 8-bit quantization accuracy. The higher the quantization resolution of the quantization device or apparatus, the smaller the minimum duty cycle that can be identified; the higher the quantization accuracy of the quantization device or apparatus, the higher the accuracy of the duty ratio detection. Compared with the prior art, the embodiment of the invention does not need to improve the detection precision of the duty ratio by improving the high-speed clock frequency or reducing the PWM signal frequency, only needs to improve the quantization precision of the electric signal, reduces the detection complexity, is easy to implement, and can effectively improve the detection precision and range of the signal duty ratio so as to optimize the minimum dimming brightness and dimming consistency of the mobile terminal.
In an embodiment of the present invention, the electrical signal may be a voltage signal. The step S102 may include the steps of: generating corresponding conversion voltage by using a Digital-to-Analog Converter (DAC) under the action of different Digital codes by taking the reference voltage as a reference; and respectively comparing the amplitude of the voltage signal with each conversion voltage to obtain a comparison result, wherein when the comparison result indicates that the amplitudes of the conversion voltage and the voltage signal are equal, the digital code corresponding to the conversion voltage is the target digital code. Those skilled in the art will appreciate that the DAC may generate different converted voltages according to the amplitude of the reference voltage under different digital codes. In this embodiment, the converted voltage having the same amplitude as the voltage signal may be locked by comparing the voltages for a plurality of times, and the corresponding digital code is the target digital code.
In a specific implementation, the switching voltage may be varied in an increasing or decreasing order, and the magnitude of each variation may be the same. For example, the resolution of the DAC is 10 bits, and the different digital codes may be sequentially incremented from 0000000001, that is, 0000000010, 0000000011, 0000000100, … … are sequentially output, and so on, so that the amplitude of the conversion voltage gradually increases. It is more advantageous to accurately lock the converted voltage equal to the amplitude of the voltage signal according to the gradual increase of the resolution of the DAC. Specifically, when the comparison result indicates that the converted voltage and the amplitude of the voltage signal are equal, the digital code corresponding to the converted voltage is the target digital code, and the method comprises the following steps: in two adjacent comparisons, when the logic levels of the comparison results are opposite, one of the digital codes corresponding to the conversion voltage adopted in the two comparisons is selected as the target digital code.
In a specific implementation, the conversion voltage equal to the amplitude of the voltage signal can be locked according to a dichotomy so as to improve the operation efficiency. Specifically, assuming that the resolution of the DAC is still 10 bits, it is possible to output the digital code 0111111111 for the first time (i.e., the value represented is 511), and if the corresponding conversion voltage is smaller than the amplitude of the voltage signal, it is determined that the digital code corresponding to the conversion voltage having the same amplitude as the voltage signal falls between 0000000001 and 0111111111, and if it is larger than the amplitude of the voltage signal, it is determined that the digital code corresponding to the conversion voltage having the same amplitude as the voltage signal falls between 0111111111 and 1111111111. And then, continuously outputting corresponding conversion voltage by adopting a bisection method, and continuously reducing the range of the digital code corresponding to the conversion voltage with the same amplitude as the voltage signal until the conversion voltage with the same amplitude as the voltage signal is finally locked.
When the target digital code is locked by using the DAC in combination with multiple voltage comparisons, the step S103 may include the following steps: and determining the duty ratio of the PWM signal according to the ratio of the value represented by the potential value when the PWM signal is at a logic high level and a logic low level, the reference voltage and the target digital code to the full-scale value of the DAC.
For example, when the potential value of the logic low level of the PWM signal is 0V, the potential value of the logic high level of the PWM signal is equal to the reference voltage (e.g., both are 3.3V and both are denoted by Vref), the ratio of the value represented by the target digital code to the full-scale value of the DAC is equal to the duty ratio of the PWM signal. Specifically, assuming that the duty ratio is D, the amplitude of the electrical signal is VLF, the target number is coded as AimCode, and the corresponding conversion voltage is D, then VLF is D × VREF, VD is AimCode × VREF, and D is AimCode because VLF is VD. If the resolution of the DAC is 10 bits, the AimCode is 0000000001, the characterization value is 1, and the full-scale value is 1023, then the duty ratio D of the PWM signal is 0.098%.
When the potential value of the logic low level of the PWM signal is not 0V, and the potential value of the logic high level of the PWM signal is equal to the reference voltage, the duty ratio of the PWM signal is in a proportional relation with the ratio of the value represented by the target digital code to the full-scale value of the digital-to-analog converter.
In another specific embodiment of the present invention, when the electrical signal is a voltage signal, the quantifying of the amplitude of the electrical signal in the step S102 may include the following steps: and quantizing the amplitude of the voltage signal by using an ADC (analog to digital converter) by taking the reference voltage as a reference so as to obtain the target digital code.
In a specific implementation, the duty ratio of the PWM signal may also be determined according to the ratio of the value represented by the reference voltage, the target digital code, and the potential value when the PWM signal is at the logic high level and the logic low level to the full scale value of the ADC.
The embodiment of the invention also discloses a duty ratio detection circuit. As shown in fig. 3 and 4, the duty cycle detection circuit 100 may include a conversion module 10, a quantization module 20, and a processor 30.
The conversion module 10 is adapted to convert the PWM signal PWM _ UT into an electrical signal VLF, wherein the amplitude of the electrical signal VLF is proportional to the duty cycle of the PWM signal PWM _ UT.
The quantization module 20 is connected to the reference electrical signal Vref and the electrical signal VLF, and is adapted to quantize the amplitude of the electrical signal VLF to obtain the target digital code AimCode.
The processor 30 is adapted to determine the duty cycle of the PWM signal PWM _ UT using the ratio of the value characterized by the target digital code AimCode to the full scale value of the quantization module 20.
In a specific implementation, the electrical signal VLF may be a voltage signal or a current signal.
Preferably, referring to fig. 4, the electrical signal VLF is a voltage signal VLF'. The conversion module 10 may comprise a low-pass filter 101, the low-pass filter 101 being adapted to convert the PWM signal PWM _ UT into the voltage signal VLF'. The cut-off frequency of the low-pass filter 101 is low. The present embodiment may use any suitable low-pass filter for the above conversion, and may be of a passive or active type, and the order and type of the filter may be configured according to actual requirements, and will not be described herein.
In an embodiment of the invention, when the electrical signal VLF is a voltage signal VLF ', the quantization module 20 may include an ADC (not shown) having a reference terminal connected to a reference voltage Vref, and the ADC is adapted to quantize the amplitude of the voltage signal VLF' to obtain the target digital code AimCode.
For example, the amplitude of the voltage signal VLF' is quantized by a 10-bit ADC whose output is assumed to be encoded with a target number of 1010100101, denoted as AimCode, of 677, and a full-scale number of 1111111111, of 2101023, the duty cycle of the PWM signal PWM _ UT can therefore be determined with 677/1023 66.18%. A quantization accuracy of 10 bits means that the minimum duty cycle that can be detected is about (1/2)10-1) ≈ 0.098%. As the sampling resolution of the ADC increases to 12 bits or even higher, the minimum duty cycle that can be identified is correspondingly smaller.
Further, for the current Complementary Metal Oxide Semiconductor (CMOS) process, the quantization module 20 has a quantization resolution of 10 bits or more, which can achieve at least 8 bits of quantization precision. The higher the quantization resolution is, the smaller the minimum duty ratio which can be identified; the higher the quantization accuracy, the higher the accuracy of duty cycle detection. Compared with the prior art, the duty ratio detection circuit 100 of the embodiment of the invention does not need to improve the detection precision of the duty ratio by improving the frequency of the high-speed clock or reducing the frequency of the PWM signal PWM _ UT, but only needs to improve the quantization precision of the electrical signal, thereby reducing the detection complexity, being easy to implement, and effectively improving the detection precision and range of the signal duty ratio, so that the minimum dimming brightness and the dimming consistency of the mobile terminal are also optimized.
In another embodiment of the present invention, when the electrical signal VLF is a voltage signal VLF', the quantization module 20 may include a DAC201 and a comparator 202. The reference terminal of the DAC201 is connected to the reference voltage Vref, and the DAC201 is adapted to generate corresponding conversion voltages VD under the action of different digital codes and output the conversion voltages VD via output terminals thereof, respectively. The comparator 202 is adapted to compare the amplitude of the voltage signal VLF 'with each of the conversion voltages VD, respectively, to obtain a comparison result Vcmp, and when the comparison result Vcmp indicates that the amplitudes of the conversion voltages VD and the voltage signal VLF' are equal, the digital Code corresponding to the conversion voltage VD is the target digital Code AimCode. In this embodiment, the converted voltage having the same amplitude as the voltage signal VLF' may be locked by comparing the voltages for a plurality of times, and the corresponding digital Code is the target digital Code AimCode.
In the present embodiment, the processor 30 is adapted to generate the respective digital Code such that the transition voltage VD varies in an increasing or decreasing order. For example, the resolution of the DAC201 is 10 bits, and the different digital Code codes may be sequentially increased from 0000000001, that is, 0000000010, 0000000011, 0000000100, … … are sequentially output, and so on, so that the amplitude of the conversion voltage VD gradually increases. In two adjacent comparisons, when the logic levels of the comparison result Vcmp are opposite, for example, the first comparison is a logic low level, the second comparison is a logic high level, and one of the digital codes corresponding to the conversion voltage VD used in the two comparisons is the target digital Code AimCode.
In a specific implementation, the conversion voltage VD having the same amplitude as the voltage signal VLF' may be locked according to a dichotomy to improve the operation efficiency.
The processor 30 is adapted to determine the duty cycle of the PWM signal PWM _ UT according to the ratio of the potential value of the PWM signal PWM _ UT at the logic high level and the logic low level, the reference voltage Vref, and the value represented by the target digital code AimCode to the full-scale value of the DAC 201.
For example, when the potential value of the logic low level of the PWM signal PWM _ UT is 0V, and the potential value of the logic high level of the PWM signal PWM _ UT is equal to the reference voltage Vref, the ratio of the value represented by the target digital code AimCode to the full-scale value of the DAC201 is equal to the duty ratio of the PWM signal PWM _ UT. For example, if the resolution of the DAC201 is 10 bits, the target digital code AimCode is 0000000001, the characterization value is 1, the full-scale value is 1023, and the duty ratio D of the PWM signal PWM _ UT is 0.098%.
In the embodiment of the present invention, the electrical signal VLF may also be a current signal. The conversion module 10 is adapted to convert the duty cycle of the PWM signal PWM _ UT into a current signal having a magnitude proportional to the duty cycle. The conversion module 10 may be any suitable duty cycle current conversion circuit, module or device. The quantization module 20 may quantize the current signal using a corresponding current acquisition device or apparatus. Specifically, the current signal may be converted into a voltage signal through a conversion resistor, and the voltage signal may be quantized.
For more information on the duty ratio detection circuit 100, please refer to the related description of the duty ratio detection method, which is not repeated herein.
The embodiment of the invention also discloses a driving circuit, which can comprise the duty ratio detection circuit 100 and the driving current generation circuit shown in fig. 3 or fig. 4. The driving current generating circuit is directly or indirectly coupled to the duty ratio detecting circuit 100, and the driving current generating circuit is adapted to generate a driving current (not shown) according to the obtained duty ratio of the PWM signal PWM _ UT.
The embodiment of the invention also discloses a mobile terminal which can comprise the driving circuit, the light-emitting device array and the display screen. Wherein the array of light emitting devices is adapted to emit light under the drive of the drive current; the display screen is suitable for displaying by taking the light emitting device array as a background light source.
The duty ratio detection circuit 100 improves the accuracy and range of duty ratio detection of the PWM signal PWM _ UT, so that the minimum dimming brightness and dimming consistency of the mobile terminal are optimized.
It should be noted that "high level" in this document refers to a level range that can be recognized as a digital signal "1", and "low level" refers to a level range that can be recognized as a digital signal "0", which are relative concepts, and the specific level range is not particularly limited.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A duty cycle detection method, comprising:
converting the PWM signal into an electrical signal, the amplitude of the electrical signal being proportional to the duty cycle of the PWM signal;
quantizing the amplitude of the electrical signal to obtain a target digital code;
determining the duty ratio of the PWM signal by utilizing the proportion of the value represented by the target digital code to the full-scale value during quantization;
the electrical signal is a voltage signal or a current signal, and when the electrical signal is a current signal, the duty cycle detection method further includes: converting the current signal into a voltage signal through a conversion resistor;
quantizing the voltage signal to obtain a target digital code comprises:
quantizing the amplitude of the voltage signal by using an analog-to-digital converter with reference voltage as a reference to obtain the target digital code;
or comprises the following steps:
taking the reference voltage as a reference, and generating corresponding conversion voltage by using a digital-to-analog converter under the action of different digital codes;
and respectively comparing the amplitude of the voltage signal with each conversion voltage to obtain a comparison result, wherein when the comparison result indicates that the amplitudes of the conversion voltage and the voltage signal are equal, the digital code corresponding to the conversion voltage is the target digital code.
2. The duty cycle detection method according to claim 1, wherein the conversion voltage is changed in an increasing or decreasing order;
when the comparison result indicates that the converted voltage and the amplitude of the voltage signal are equal, the digital code corresponding to the converted voltage is the target digital code, and the method comprises the following steps:
in two adjacent comparisons, when the logic levels of the comparison results are opposite, one of the digital codes corresponding to the conversion voltage adopted in the two comparisons is selected as the target digital code.
3. The duty cycle detection method of claim 1, wherein determining the duty cycle of the PWM signal using the ratio of the value characterized by the target digital code to the full scale value when quantized comprises:
and determining the duty ratio of the PWM signal according to the potential values when the PWM signal is at a logic high level and a logic low level, and the ratio of the value represented by the reference voltage and the target digital code to the full-scale value of the digital-to-analog converter.
4. The duty cycle detection method according to claim 3, wherein when the potential value of the logic low level of the PWM signal is 0V and the potential value of the logic high level of the PWM signal is equal to the reference voltage, the ratio of the value represented by the target digital code to the full-scale value of the digital-to-analog converter is equal to the duty cycle of the PWM signal.
5. A duty cycle detection circuit, comprising:
the conversion module is suitable for converting the PWM signal into an electric signal, and the amplitude of the electric signal is in direct proportion to the duty ratio of the PWM signal;
the quantization module is accessed to the reference electric signal and the electric signal and is suitable for quantizing the amplitude of the electric signal to obtain a target digital code; the quantization module comprises a quantization device or apparatus;
a processor adapted to determine a duty cycle of the PWM signal using a ratio of a value characterized by the target digital code to a full scale value of the quantization module;
the electrical signal is a voltage signal or a current signal, and when the electrical signal is a current signal, the duty cycle detection circuit further includes: a conversion resistor for converting the current signal into a voltage signal;
the quantization module comprises:
the reference end of the analog-to-digital converter is connected with a reference voltage, and the analog-to-digital converter is suitable for quantizing the amplitude of the voltage signal to obtain the target digital code;
or comprises the following steps:
the digital-to-analog converter is suitable for generating corresponding conversion voltages under the action of different digital codes and outputting the conversion voltages through output ends of the digital-to-analog converter;
and the comparator is suitable for respectively comparing the amplitude of the voltage signal with each conversion voltage to obtain a comparison result, and when the comparison result indicates that the amplitudes of the conversion voltage and the voltage signal are equal, the digital code corresponding to the conversion voltage is the target digital code.
6. The duty cycle detection circuit of claim 5, wherein the processor is adapted to generate respective digital codes such that the converted voltages vary in an increasing or decreasing order;
in two adjacent comparisons, when the logic levels of the comparison results are opposite, one of the digital codes corresponding to the conversion voltage adopted in the two comparisons is the target digital code.
7. The duty cycle detection circuit of claim 6, wherein the processor is adapted to determine the duty cycle of the PWM signal based on the potential values at which the PWM signal is at logic high and logic low levels, the ratio of the value characterized by the reference voltage and the target digital code to the full scale value of the digital-to-analog converter.
8. The duty cycle detection circuit according to claim 7, wherein when the potential value of the logic low level of the PWM signal is 0V and the potential value of the logic high level of the PWM signal is equal to the reference voltage, the ratio of the value represented by the target digital code to the full-scale value of the digital-to-analog converter is equal to the duty cycle of the PWM signal.
9. The duty cycle detection circuit of any one of claims 5 to 8, wherein the conversion module comprises: a low pass filter adapted to convert the PWM signal to the voltage signal.
10. A driver circuit, comprising:
the duty cycle detection circuit of any one of claims 5 to 9;
and the driving current generation circuit is directly or indirectly coupled with the duty ratio detection circuit and is suitable for generating driving current according to the obtained duty ratio of the PWM signal.
11. A mobile terminal, comprising:
the drive circuit of claim 10;
an array of light emitting devices adapted to emit light under the drive of the drive current;
and the display screen is suitable for displaying by taking the light emitting device array as a background light source.
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| CN109274356A (en) * | 2018-09-29 | 2019-01-25 | 上海华虹宏力半导体制造有限公司 | The test circuit of clock duty cycle |
| CN109194312B (en) * | 2018-10-31 | 2022-04-01 | 湖南菲尔斯特传感器有限公司 | Correcting system and method for realizing standard signal output value based on PWM signal |
| CN109738708B (en) * | 2019-03-01 | 2021-03-05 | 山东交通学院 | High-precision rectangular pulse duty ratio measuring method and circuit |
| CN114423117B (en) * | 2021-12-16 | 2024-09-13 | 广州裕芯电子科技有限公司 | LED brightness segmentation control circuit and LED brightness segmentation control method |
| CN119484173B (en) * | 2025-01-15 | 2025-04-08 | 营口新山鹰报警设备有限公司 | A fire power two-bus power supply and communication method and device based on PWM |
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