CN107346729A - Substrate of semiconductor devices and preparation method thereof and semiconductor devices - Google Patents

Abstract

The present invention provides a base of a semiconductor device, a manufacturing method thereof, and a semiconductor device, wherein the base of the semiconductor includes: a substrate; a gate oxide layer and a polysilicon layer formed on the substrate; wherein, the polysilicon layer and the substrate Contact; a discontinuity formed in the polysilicon layer. The substrate of the semiconductor device of the present invention and its manufacturing method and semiconductor device, because the substrate and the polysilicon layer are contacted and connected, therefore, the charge accumulated in the polysilicon layer can be introduced into the substrate when the polysilicon layer is etched, thereby avoiding The problem of device failure caused by the breakdown of the gate oxide layer caused by etching the polysilicon layer.

Description

Substrate of semiconductor device, manufacturing method thereof, and semiconductor device

technical field

The invention relates to semiconductor device technology, in particular to a substrate of a semiconductor device, a manufacturing method thereof and a semiconductor device.

Background technique

The base structure of the semiconductor device mainly includes a substrate layer, a gate oxide layer and a polysilicon layer formed on the gate oxide layer, and a discontinuity area is etched on the polysilicon layer. 1 is a schematic structural diagram of a substrate of a semiconductor device in the prior art. As shown in FIG.

In the prior art, dry etching is generally used when etching the discontinuity region 400 , that is, gas ion bombardment is used to etch the polysilicon layer 300 .

Since the gate oxide layer 200 is non-conductive, the polysilicon layer 300 and the substrate layer 100 can be equivalent to a capacitor. In the process of continuous bombardment with gas ions, the voltage difference between the two ends of the capacitor is equivalent to increasing, so it will be in the process of etching The gate oxide layer 200 is broken down during the process of forming the polysilicon layer 300 , for example, it is relatively easy to break down at the circled position 500 shown in FIG. 1 , resulting in device failure.

Contents of the invention

The invention provides a substrate of a semiconductor device, a manufacturing method thereof, and a semiconductor device to solve the problem in the prior art that a gate oxide layer is broken down when etching a polysilicon layer, resulting in device failure.

A first aspect of the present invention provides a method for manufacturing a substrate of a semiconductor device, comprising:

forming a gate oxide layer on the substrate;

forming a polysilicon layer on the gate oxide layer, wherein the polysilicon layer is in contact with the substrate;

A discontinuity region is formed in the polysilicon layer.

A second aspect of the present invention provides a substrate for a semiconductor device, comprising:

Substrate;

a gate oxide layer and a polysilicon layer formed on the substrate, wherein the polysilicon layer is in contact with the substrate;

A discontinuity region is formed in the polysilicon layer.

A third aspect of the present invention provides a semiconductor device, including: the substrate of the semiconductor device provided in the second aspect above.

It can be seen from the above-mentioned technical scheme that the base of the semiconductor device provided by the present invention, the manufacturing method of the base of the semiconductor device and the semiconductor device, because the substrate is in contact with the polysilicon layer, therefore, the charge accumulated in the polysilicon layer can be introduced into the polysilicon layer when the polysilicon layer is etched. To the substrate, so that the problem of device failure caused by the gate oxide layer breakdown caused when etching the polysilicon layer can be avoided.

Description of drawings

1 is a schematic structural view of a substrate of a semiconductor device in the prior art;

FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention;

3 is a top view of a semiconductor device in the prior art;

FIG. 4 is a schematic structural diagram of a substrate of a semiconductor device provided in Embodiment 2 of the present invention;

5A-5C are schematic top view structural diagrams of various manufacturing steps of the substrate of the semiconductor device provided by Embodiment 2 of the present invention;

6A-6D are schematic cross-sectional structural diagrams of various manufacturing steps of a semiconductor device provided by an embodiment of the present invention.

Reference signs:

100-substrate layer; 200-gate oxide layer;

300-polysilicon layer; 400-discontinuity region;

500-circle position; 1-substrate;

2-gate oxide layer; 3-polysilicon layer;

20-location area; 600-semiconductor device;

41-discontinuity zone; 21-connection zone;

22—Gate oxide layer on the alignment area of the substrate.

detailed description

This embodiment provides a method for manufacturing a substrate of a semiconductor device. It should be noted that the substrate in this implementation can be used to form multiple chips, as shown in Figure 2, Figure 2 is a flowchart of the method for manufacturing the substrate of the semiconductor device in Embodiment 1 of the present invention, the semiconductor device The method of making the base includes:

Step 101, forming a gate oxide layer on a substrate.

Step 102, forming a polysilicon layer on the gate oxide layer, wherein the polysilicon layer is in contact with the substrate.

Specifically, the polysilicon layer is formed on the gate oxide layer.

Step 103, forming a discontinuity region in the polysilicon layer.

Wherein, the polysilicon layer and the substrate only need to ensure that the charges accumulated in the polysilicon layer can be introduced into the substrate when the polysilicon layer is etched.

In addition, it should be noted that in the prior art, in order to distinguish different silicon wafers, the silicon wafers need to be provided with markings for distinguishing the silicon wafers. Fig. 3 is a top view of a semiconductor device in the prior art, as shown in Fig. 3 As shown, the area provided with the logo is the positioning area 20, and in the prior art, no devices are arranged in the positioning area 20. In addition, the positioning area 20 is also called a main flat edge in the art. The positioning area 20 is an area on the substrate where no device is installed, generally at a certain edge of the substrate. It can be seen that in the schematic diagram of FIG. 3 , a plurality of semiconductor devices 600 are included, and the positioning area 20 is located outside the plurality of semiconductor devices 600 , that is, the substrate area where no semiconductor device 600 is arranged.

Optionally, after forming the gate oxide layer, the gate oxide layer above the positioning area of the substrate is etched to form a connection area, and a polysilicon layer is formed in the connection area and on the gate oxide layer. In addition, the substrate can be a silicon substrate, and the gate oxide layer can be silicon dioxide. The gate oxide layer can be deposited on the substrate by chemical vapor deposition. Of course, the substrate can also be directly oxidized to form silicon dioxide. .

The substrate of the semiconductor device provided by this embodiment, because the substrate is connected to the polysilicon layer, can lead the charge accumulated in the polysilicon layer into the substrate when the polysilicon layer is etched, thereby avoiding damage caused when the polysilicon layer is etched. The problem of device failure caused by gate oxide breakdown.

Embodiment two

On the basis of the first embodiment above, this embodiment specifically provides implementations of two substrate manufacturing methods. Fig. 4 is a schematic structural diagram of the substrate of the semiconductor device provided by Embodiment 2 of the present invention, as shown in Fig. 4, one of the embodiments is as follows:

A groove for accommodating the gate oxide layer 2 is etched on the substrate 1. Further, the gate oxide layer 2 is grown in the groove. Preferably, the gate oxide layer 2 is deposited by chemical vapor deposition. A polysilicon layer 3 is formed on the layer 2 and the substrate 1 , and finally a discontinuity region 41 is etched in the polysilicon layer 3 .

Wherein, it should be noted that in this embodiment, preferably, the unetched region of the substrate 1 corresponds to the positioning area 12 of the substrate 1, that is, the positioning area 12 of the polysilicon layer 3 and the substrate 1 on the substrate 1 contact connection, so that the area of the substrate 1 can be effectively utilized.

Since the substrate 1 is exposed to the air for a long time, it is easy to cause oxidation. If the above method of etching the substrate 1 is used to fabricate the substrate, the oxide film caused by oxidation must be removed first, and the fabrication method is relatively cumbersome.

A more preferred implementation mode can refer to the implementation mode given in FIGS. 5A-5C and 6A-6D. FIGS. 5A-5C are schematic top view structural diagrams of various manufacturing steps of the substrate of the semiconductor device provided by Embodiment 2 of the present invention. 6A-6D are schematic cross-sectional structural diagrams of various manufacturing steps of the substrate of the semiconductor device provided by Embodiment 2 of the present invention.

FIG. 5A is a top view of the substrate of the semiconductor device provided in Embodiment 2 of the present invention in step 201, and FIG. 6A is a cross-sectional view along the line A-A of FIG. 5A.

As shown in FIGS. 5A and 6A , in step 201 , a gate oxide layer 2 is formed on a substrate 1 .

Wherein, the gate oxide layer 2 can be formed by oxidizing the substrate 1 . In this embodiment, the substrate 1 is silicon for illustration. In order to enhance the conductivity of the substrate, the substrate 1 may be doped with metal ions, and the specific type and concentration of the metal ions are not limited. Optionally, the temperature for forming the gate oxide layer 2 is 900°C to 1000°C.

FIG. 5B is a top view of the substrate of the semiconductor device provided in the second embodiment of the present invention in step 202, and FIG. 6B is a cross-sectional view along the line A-A of FIG. 5B.

As shown in FIG. 5B and FIG. 6B , step 202 , wet etching the gate oxide layer 22 on the positioning area of the substrate 1 to form the connection area 21 .

Preferably, the positioning area of the substrate 1 and the gate oxide layer 22 on the positioning area of the substrate 1 are immersed in an etching solution, and the etching solution etches away the gate oxide layer 22 on the positioning area of the substrate 1 .

Specifically, the substrate 1 and the gate oxide layer 2 are suspended, and further, the positioning area of the substrate 1 and the gate oxide layer 22 on the positioning area of the substrate 1 are immersed in an etching groove, and the etching solution in the etching groove The gate oxide layer 22 on the alignment area of the substrate 1 is etched away, thereby forming a connection area 21 .

For the convenience of description, the device after the gate oxide layer 2 is formed on the substrate 1 in step 201 is called a "silicon wafer". The specific suspension method can refer to Figure 3, that is, the entire silicon wafer is suspended in the manner shown in Figure 3 , and then immerse the positioning region 20 into the etching solution. It should be noted that, since FIG. 3 is a schematic diagram of a semiconductor device in the prior art, it is only to illustrate how the silicon wafer is immersed in the etching solution, but it does not mean that the silicon wafer in this embodiment is Silicon wafers in the prior art.

Of course, there can also be other ways to etch the gate oxide layer 22 on the positioning region of the substrate 1. For example, a mask layer can be formed on the gate oxide layer 2, and the gate oxide layer 22 can be etched using the mask layer as a mask. Layer 2 is etched.

Suspending the silicon wafer and adopting a wet etching process does not need to form an additional mask layer, the process is simple, and the material of the mask layer is saved.

Wherein, compared with dry etching, wet etching of the connection region 21 can reduce the impact of ion bombardment on the substrate 1 . In addition, wet etching has excellent selectivity and will not damage the substrate 1 .

In addition, the gate oxide layer 22 on the positioning area of the substrate 1 is wet etched, that is, the polysilicon layer 3 is in contact with the positioning area of the substrate 1. Since the positioning area is not arranged with semiconductor devices, the substrate can be effectively used. The area of base 1. Optionally, for the silicon substrate, hydrofluoric acid solution may be used for wet etching.

Fig. 5C is a top view of the substrate of the semiconductor device provided in the second embodiment of the present invention in step 203

As shown in FIG. 5C , in step 203 , a polysilicon layer 3 is formed in the connection region 21 and on the gate oxide layer 2 .

FIG. 6D is a cross-sectional view of the substrate of the semiconductor device provided in the second embodiment of the present invention in step 204 .

As shown in FIG. 6D , step 204 , etching the discontinuity region 41 in the polysilicon layer 3 .

Specifically, a photoresist is formed on the polysilicon layer 3, and a preset area of the photoresist is exposed and developed to form a development mask with a preset pattern. Under the cover of the development mask, the polysilicon layer 3 is etch to etch the discontinuity region 41 in the polysilicon layer 3 .

Wherein, the thickness of the gate oxide layer 2 is 0.01 micron to 1.0 micron. The temperature for forming the polysilicon layer 30 is 500° C. to 1000° C., and the thickness of the polysilicon layer 3 is 0.01 μm to 2.0 μm. The polysilicon layer 3 here refers to the thickness of the polysilicon layer 3 formed on the upper surface of the gate oxide layer 2 .

The manufacturing method of the substrate of the semiconductor device provided by this embodiment can not only introduce the charges accumulated in the polysilicon layer 3 into the substrate 1 when the polysilicon layer 3 is etched, so as to avoid gate failure caused when the polysilicon layer 3 is etched. In addition, since the polysilicon layer 3 is in contact with the substrate 1 through the positioning area of the substrate 1 , the area of the substrate 1 can be effectively utilized.

Embodiment Three

This embodiment provides a substrate of a semiconductor device, which can be manufactured by using the method provided in the above-mentioned embodiment 1 or embodiment 2.

Wherein, as shown in FIG. 6D, the base of the semiconductor device includes: a substrate 1, a gate oxide layer 2 formed on the substrate 1, a polysilicon layer 3, and a discontinuity region 41 formed in the polysilicon layer 3, wherein the polysilicon Layer 3 is in contact with substrate 1 .

Preferably, the polysilicon layer 3 is connected to the substrate 1 at the location area of the substrate 1 .

In addition, the substrate 1 can be a silicon substrate, and the gate oxide layer 2 can be silicon dioxide. The gate oxide layer 2 can be deposited on the substrate 1 by chemical vapor deposition. Of course, the substrate 1 can also be oxidized directly. to produce silicon dioxide.

Optionally, the gate oxide layer 2 has a thickness of 0.01 micron to 1.0 micron. The polysilicon layer 3 has a thickness of 0.01 microns to 2.0 microns.

The base of the semiconductor device provided in this embodiment, because the substrate 1 and the polysilicon layer 3 are contacted and connected, the charges accumulated in the polysilicon layer can be introduced into the substrate 1 when the polysilicon layer 3 is etched, thereby avoiding The breakdown of the gate oxide layer 2 caused by the polysilicon layer 3 causes device failure.

Embodiment four

This embodiment also provides a semiconductor device, which includes the substrate of the semiconductor device described in the third embodiment. The substrate can be manufactured by the method in the above-mentioned embodiment 1 or embodiment 2.

It should be noted that, other technical features of the semiconductor device may be implemented using technical means in the prior art, which will not be repeated here.

The semiconductor device provided in this embodiment adopts the base in the above-mentioned embodiments, and the substrate and the polysilicon layer are contacted and connected. Therefore, the charges accumulated in the polysilicon layer can be introduced into the substrate when the polysilicon layer is etched, thereby avoiding The problem of device failure caused by the breakdown of the gate oxide layer caused by etching the polysilicon layer.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A kind of 1. preparation method of the substrate of semiconductor devices, it is characterised in that including：

   Gate oxide is formed on substrate；

   Polysilicon layer is formed on the gate oxide, wherein, the polysilicon layer and the substrate contact；

   Unconnected area is formed in the polysilicon layer.
2. 2. according to the method for claim 1, it is characterised in that after the gate oxide is formed, And before polysilicon layer is formed, in addition to：

   Gate oxide on the positioning area of substrate described in wet etching, form bonding pad；

   Correspondingly, polysilicon layer is formed on the gate oxide includes：

   In the bonding pad and form polysilicon layer on the gate oxide.
3. 3. according to the method for claim 2, it is characterised in that substrate determines described in the wet etching Gate oxide in the area of position, forming bonding pad includes：

   Gate oxide on the positioning area of the positioning area of substrate and the substrate is immersed in etching solution, etching solution Etch away the gate oxide on the positioning area of the substrate.
4. 4. according to the method for claim 1, it is characterised in that form the temperature of the polysilicon layer For 500 DEG C to 1000 DEG C, the temperature for forming the gate oxide is 900 DEG C to 1000 DEG C.
5. 5. according to the method described in claim any one of 1-4, it is characterised in that the thickness of the polysilicon layer Spend for 0.01 micron to 2.0 microns, the thickness of the gate oxide is 0.01 micron to 1.0 microns.
6. A kind of 6. substrate of semiconductor devices, it is characterised in that including：

   Substrate；

   The gate oxide and polysilicon layer formed over the substrate, wherein, the polysilicon layer and the lining Bottom contacts；

   The unconnected area formed in the polysilicon layer.
7. 7. substrate according to claim 6, it is characterised in that the polysilicon layer and the substrate Positioning area contact.
8. 8. the substrate according to claim 6 or 7, it is characterised in that the thickness of gate oxide is 0.01 Micron is to 1.0 microns.
9. 9. substrate according to claim 6, it is characterised in that the thickness of the polysilicon layer is 0.01 Micron is to 2.0 microns.
10. A kind of 10. semiconductor devices, it is characterised in that including：Half described in the claims any one of 6-9 The substrate of conductor device.