CN107331610A - The method for improving silicon wafer epi-layer surface flatness - Google Patents
The method for improving silicon wafer epi-layer surface flatness Download PDFInfo
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- CN107331610A CN107331610A CN201610278896.9A CN201610278896A CN107331610A CN 107331610 A CN107331610 A CN 107331610A CN 201610278896 A CN201610278896 A CN 201610278896A CN 107331610 A CN107331610 A CN 107331610A
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- silicon wafer
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 79
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 79
- 239000010703 silicon Substances 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 238000009826 distribution Methods 0.000 claims abstract description 11
- 238000001312 dry etching Methods 0.000 claims abstract description 11
- 238000000227 grinding Methods 0.000 claims abstract description 11
- 238000001514 detection method Methods 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 238000005259 measurement Methods 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 16
- 238000005192 partition Methods 0.000 claims description 14
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 5
- 238000007654 immersion Methods 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 229910001868 water Inorganic materials 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 238000005498 polishing Methods 0.000 abstract description 9
- 239000013078 crystal Substances 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000007547 defect Effects 0.000 description 11
- 238000012545 processing Methods 0.000 description 5
- 238000009499 grossing Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229960002050 hydrofluoric acid Drugs 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 210000005056 cell body Anatomy 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000019771 cognition Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000010445 mica Substances 0.000 description 1
- 229910052618 mica group Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Weting (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Drying Of Semiconductors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention provides a kind of method for improving silicon wafer epi-layer surface flatness, including：The section of the monocrystal silicon of thin round plate shape is carried out to wet etching, grinding, polishing successively；The concavo-convex situation of pending silicon wafer surface is detected using detection unit；According to the data of the concavo-convex situation, calculate and obtain silicon wafer zone temperature control distribution map；According to the distribution map, with subregion resistance heating and the temperature of the crystal silicon substrate is controlled, and planarized the silicon wafer with plasma dry etching；And finally polished；Wherein, when the silicon wafer surface carries out extension to grow epitaxial wafer, surface flatness measurement is carried out to gained epitaxial wafer piece integral surface, the nanotopography of the silicon wafer surface flatness is less than 25nm.
Description
Technical field
It is more particularly to a kind of to improve silicon wafer epi-layer surface flatness the present invention relates to field of semiconductor manufacture
Method.
Background technology
In known extension layer manufacturing method, blob-like shapes are obtained by cutting off the two ends of monocrystal silicon,
Integral diameter is set unanimously to obtain block (block body) to being ground on the outside of silicon ingot, to the block shape
Specific crystal orientation is indicated into directional plane or orientation breach (orientation notch), then with to axle
The block is cut into slices in the mode of predetermined angular to direction.Peripheral part of section gained wafer is through chamfering
(chamfered) to avoid the fragment of fragmentation or wafer peripheral part.Then, smoothing step is completed,
Wafer twin grinding (DDSG) is carried out, the surface of the Silicon Wafer both sides is ground, wafer one side is then carried out and grinds
Grind (SDSG).Then wafer twin polishing (DSP) is carried out, can be while the surface of wafer polishing both sides, connects
Carry out wafer single-sided polishing (SMP).Then, when the epitaxial layer of monocrystalline silicon is formed at epitaxial growth regime
During the crystal column surface, you can obtain epitaxial silicon wafer.
It is well known, however, that manufacture method there is following point：
Machining processing procedure (such as section, grinding) will necessarily form mechanical damage on the wafer or machinery is scraped
Trace.Because the epitaxial layer forming step based on epitaxial growth can amplify the scratch or damage (crystalline substance of crystal column surface
Lattice are distorted), therefore, in the epitaxial layer, using the rejected region caused by the machining such as grinding as starting point, meeting
Occur such as poor row or storehouse mistake crystal defect, and in some cases, such a defect can cause epitaxial layer
The surface defect on surface.Also, when be machined processing procedure caused by scratch or mechanical damage than it is more serious when,
Sliding can be formed in the epitaxial layer formed.
Prior art is that wafer is immersed in etchant after grinding, chemically etches wafer both sides table
Face, can reduce the incidence of the scratch defects caused by the bump defects on monocrystalline silicon epitaxial film surface, and can
Reduce the height of such a bump defects.However, because immersion etching can etch whole wafer surface simultaneously,
The removal quantity control of crystal column surface can influence shape to control, it is impossible to obtain predetermined crystal column surface shape, may
So that surface state (such as flatness) is difficult to improve, in some instances it may even be possible to more even worse than before grinding.Also, with machinery
Smoothing step based on (as ground) is carried out before the vapor phase growth of monocrystalline silicon thin film, on the wafer
Will necessarily occur mechanical damage or processing scratch, can not also have even if follow-up water polishing or using abrasive polishing
Surface defect or sliding on effect reduction epitaxial layer are formed.
Although prior art controls smoothing step to control etching solution, etching solution easily is allowed in wafer
Upper surface overstays so that wafer plane and outer rim shape are uncontrollable, cause the deterioration of wafer planarization degree.
Therefore, how to improve wafer and epi-layer surface flatness is the one of those skilled in the art's urgent need to resolve
Individual problem.
The content of the invention
It is an object of the invention to provide a kind of method for improving silicon wafer epi-layer surface flatness, it can increase
The smoothness of silicon wafer surface, the surface defect on epitaxial layer and sliding when reducing epitaxial growth.
The technical scheme is that a kind of method for improving silicon wafer epi-layer surface flatness, including：
Obtained silicon wafer that monocrystal silicon is cut into slices carries out wet etching, grinding and polished successively；
The concavo-convex situation of the pending silicon wafer surface of detection；
According to the data of the concavo-convex situation, calculate and obtain temperature controlled distribution map；
According to the distribution map, the temperature of partition heating and silicon wafer described in zonal control, and with dry etching
Planarized；
Polish the silicon wafer；And
In silicon wafer surface formation epitaxial layer；
Wherein, surface flatness measurement, the epitaxial silicon wafer are carried out to gained epitaxial silicon wafer integral surface
The nanotopography of surface flatness is less than 25nm.
Further, in the method for the raising silicon wafer epi-layer surface flatness, the dry etching is
Plasma dry etch.
Further, in the method for the raising silicon wafer epi-layer surface flatness, the plasma soma
Method etching, which is used, includes CF4、C2F6、SF6Or Cl2Etching gas.
Further, in the method for the raising silicon wafer epi-layer surface flatness, the wet etching is
The two-sided etching of immersion.
Further, in the method for the raising silicon wafer epi-layer surface flatness, the wet etching
Etching solution is the mixed liquor of hydrofluoric acid, nitric acid, phosphoric acid and water.
Further, in the method for the raising silicon wafer epi-layer surface flatness, the silicon wafer surface
Concavo-convex situation is detected with a detection unit.
Further, it is described raising silicon wafer epi-layer surface flatness method, the partition heating with
Subregion resistance heater is carried out.
Further, it is described raising silicon wafer epi-layer surface flatness method, the partition heating with
Logical micro-partition temperature control unit is carried out.
The method for the raising silicon wafer epi-layer surface flatness that the present invention is provided, the pending silicon by detecting
The concavo-convex situation of wafer surface calculates and obtains temperature controlled distribution map, and according to distribution map, partition heating is simultaneously
The temperature of zonal control silicon wafer, and planarized with dry etching, the smooth of silicon wafer surface can be increased
Degree, when the silicon wafer surface uses epitaxy technique grown epitaxial layer, when can reduce growth on epitaxial layer
Surface defect and sliding generation.
Brief description of the drawings
Fig. 1 is the flow chart of the method for raising silicon wafer epi-layer surface flatness provided by the present invention.
The stream of the method for the raising silicon wafer epi-layer surface flatness that Fig. 2 is provided by one embodiment of the invention
Cheng Tu.
Embodiment
The method of the present invention is described in more detail below in conjunction with schematic diagram, wherein listing the present invention
Preferred embodiment, it should be understood that those skilled in the art can repair to the present invention described herein
Change, and still realize beneficial effects of the present invention.Therefore, description below should be understood that for this area
The extensive cognition of technical staff, and it is not intended as limitation of the present invention.
In order to clearly describe whole features of practical embodiments, in the following description, many institutes are not described in detail
Known function and structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that
In the exploitation of any practical embodiments, it is necessary to make a large amount of implementation details to realize the specific objective of developer,
For example according to about system or about the limitation of business, another embodiment is changed into by one embodiment.Separately
Outside, it will be understood that this development is probably complicated and time-consuming, but for the common skill in this area
It is only routine work for art personnel.
The present invention is more specifically described by way of example referring to the drawings in the following passage.According to following explanation
And claim, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is using non-
Often simplified form and use non-accurately ratio, only to it is convenient, lucidly to aid in illustrating the present invention real
Apply the purpose of example.
It refer to shown in Fig. 1, the present invention proposes a kind of method for improving silicon wafer epi-layer surface flatness,
Comprise the following steps：
S101：The section of the monocrystal silicon of thin round plate shape is carried out to Wet-type etching, polishing successively；
S102：The concavo-convex situation of pending silicon wafer surface is detected using detection unit；
S103：According to the data of the concavo-convex situation, calculate and obtain temperature controlled distribution map；
S104：According to the distribution map, with subregion resistance heating and the temperature of the silicon wafer is controlled, and with
Dry etching planarizes the silicon wafer；
S105：It is polished；And
S106：In silicon wafer surface formation epitaxial layer.
It refer to shown in Fig. 2, in the present embodiment more detailed description method provided by the present invention.
First there is provided a monocrystal silicon (S201), carry out successively round as a ball grinding, positioning side or positioning V grooves,
The steps such as section, chamfering, twin grinding, one side grinding (S202~S207), are made silicon wafer.Then,
Silicon wafer surface mechanical damage (S208) is eliminated with the two-sided corrosion of immersion, and carries out twin polishing (S209)
And edge polishing (S210).
The concavo-convex situation of pending silicon wafer surface is detected using detection unit, and preserves detection data (S211),
The detection unit can use such as Wafersight 2 (can be bought by KLA-Tencor), LSW-3020FE
(can be bought by Kobelco), Nanometro 300TT-A (can be bought by Kuroda) etc., detect data
It can be stored in memory.Receive the detection unit detect the concavo-convex situation of silicon wafer surface data,
Calculate silicon wafer electrostatic chuck zone temperature control distribution map and etching period (S212).
Then, with electrostatic chuck zonal control resistance heating silicon substrates, silicon substrates temperature described in zonal control
Degree, and silicon wafer planarization process (S213) is carried out with plasma dry etch, silicon wafer can be realized accordingly
The lifting of surface smoothness.
Logical micro-partition temperature control unit (micro-zone temperature control unit) can be used in above-mentioned steps
Carry out.The logical micro-partition temperature control unit is the number by Peltier (Peltier) device and/or resistance heater
Group is constituted, and the resistance heater can be polyimides heater, silica gel heating device, mica heater, gold
Category heater (such as tungsten, ni cr alloy, molybdenum, tantalum), ceramic heater (such as tungsten carbide), semiconductor add
Hot device, carbon heater or other any appropriate heating/cooling components.The temperature control unit may be incorporated into
Different designs or configuration, such as screen painting formula heater, wrapped wire heater, etching foil heater,
Or other any appropriate designs.Each subregion of the logical micro-partition temperature control unit can independent control temperature,
The scope for controlling circuit is 0~20W.The entire area of the logical micro-partition temperature control unit can be the silicon wafer
The 90% to 120% of substrate area.
Silicon wafer after the processing of plasma dry etching carries out the mirror finish (S214) of one side.Then,
Epitaxial growth (S215) is carried out on the silicon wafer surface Jing Guo above-mentioned processing, epitaxial growth can be effectively reduced
When epitaxial layer on surface defect and sliding occur.
In the above-described embodiments, the wet etching is the two-sided etching of immersion, and used etching solution is hydrogen
Fluoric acid, nitric acid, the mixed liquor of phosphoric acid and water.
In the above-described embodiments, the dry etching is plasma dry etch, used etching gas
Including CF4、C2F6、SF6Or Cl2Deng.
Via the step, Neng Gouyou such as above-mentioned wet etching, partition heating and zone temperature control, dry etching
The smoothness of effect lifting silicon wafer surface.Therefore, grown in such a surface smoothness more preferably silicon wafer surface
During epitaxial layer, the surface defect of epitaxial layer and the generation of sliding can be reduced, so as to improve follow up device performance.
Foregoing description is only the description to present pre-ferred embodiments, not to any limit of the scope of the invention
Calmly, the those of ordinary skill in field of the present invention does according to the disclosure above content any change, modification, belong to
In the protection domain of claims.
Claims (8)
1. a kind of method for improving silicon wafer epi-layer surface flatness, including：
Obtained silicon wafer that monocrystal silicon is cut into slices carries out wet etching, grinding and polished successively；
The concavo-convex situation of the pending silicon wafer surface of detection；
According to the data of the concavo-convex situation, calculate and obtain temperature controlled distribution map；
According to the distribution map, the temperature of partition heating and silicon wafer described in zonal control, and with dry etching
Planarized；
Polish the silicon wafer；And
In silicon wafer surface formation epitaxial layer；
Wherein, surface flatness measurement, the epitaxial silicon wafer are carried out to gained epitaxial silicon wafer integral surface
The nanotopography of surface flatness is less than 25nm.
2. the method for silicon wafer epi-layer surface flatness is improved as claimed in claim 1, it is characterised in that
The dry etching is plasma dry etch.
3. the method for silicon wafer epi-layer surface flatness is improved as claimed in claim 2, it is characterised in that
The plasma dry etching, which is used, includes CF4、C2F6、SF6Or Cl2Etching gas.
4. the method for silicon wafer epi-layer surface flatness is improved as claimed in claim 1, it is characterised in that
The wet etching is the two-sided etching of immersion.
5. the method for silicon wafer epi-layer surface flatness is improved as claimed in claim 1, it is characterised in that
The etching solution of the wet etching is the mixed liquor of hydrofluoric acid, nitric acid, phosphoric acid and water.
6. the method for silicon wafer epi-layer surface flatness is improved as claimed in claim 1, it is characterised in that
The concavo-convex situation of the silicon wafer surface is detected with a detection unit.
7. the method for silicon wafer epi-layer surface flatness is improved as claimed in claim 1, it is characterised in that
The partition heating is carried out with subregion resistance heater.
8. the method for silicon wafer epi-layer surface flatness is improved as claimed in claim 1, it is characterised in that
The partition heating is carried out with logical micro-partition temperature control unit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610278896.9A CN107331610A (en) | 2016-04-28 | 2016-04-28 | The method for improving silicon wafer epi-layer surface flatness |
| TW105129501A TWI600071B (en) | 2016-04-28 | 2016-09-10 | Process for enhancing surface flatness of epitaxy layer of silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610278896.9A CN107331610A (en) | 2016-04-28 | 2016-04-28 | The method for improving silicon wafer epi-layer surface flatness |
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| Publication Number | Publication Date |
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| CN107331610A true CN107331610A (en) | 2017-11-07 |
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| CN201610278896.9A Pending CN107331610A (en) | 2016-04-28 | 2016-04-28 | The method for improving silicon wafer epi-layer surface flatness |
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| TW (1) | TWI600071B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110634759A (en) * | 2019-09-03 | 2019-12-31 | 武汉新芯集成电路制造有限公司 | Method for detecting wet etching defects |
| CN110648909A (en) * | 2019-09-30 | 2020-01-03 | 福建北电新材料科技有限公司 | Backgrinding method, substrate wafer, and electronic device |
| CN113178382A (en) * | 2020-12-30 | 2021-07-27 | 集美大学 | Polishing method of wafer-level diamond substrate and wafer-level diamond substrate |
| TWI844269B (en) * | 2022-12-08 | 2024-06-01 | 大陸商西安奕斯偉材料科技股份有限公司 | Method and system for improving silicon wafer surface flatness |
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| US6338805B1 (en) * | 1999-07-14 | 2002-01-15 | Memc Electronic Materials, Inc. | Process for fabricating semiconductor wafers with external gettering |
| CN101276747A (en) * | 2006-12-29 | 2008-10-01 | 斯尔瑞恩公司 | Method for manufacturing high flatness silicon wafer |
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- 2016-09-10 TW TW105129501A patent/TWI600071B/en active
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| US6338805B1 (en) * | 1999-07-14 | 2002-01-15 | Memc Electronic Materials, Inc. | Process for fabricating semiconductor wafers with external gettering |
| CN101276747A (en) * | 2006-12-29 | 2008-10-01 | 斯尔瑞恩公司 | Method for manufacturing high flatness silicon wafer |
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| CN110634759A (en) * | 2019-09-03 | 2019-12-31 | 武汉新芯集成电路制造有限公司 | Method for detecting wet etching defects |
| CN110634759B (en) * | 2019-09-03 | 2022-02-25 | 武汉新芯集成电路制造有限公司 | Method for detecting wet etching defects |
| CN110648909A (en) * | 2019-09-30 | 2020-01-03 | 福建北电新材料科技有限公司 | Backgrinding method, substrate wafer, and electronic device |
| CN110648909B (en) * | 2019-09-30 | 2022-03-18 | 福建北电新材料科技有限公司 | Back grinding method, substrate wafer and electronic device |
| CN113178382A (en) * | 2020-12-30 | 2021-07-27 | 集美大学 | Polishing method of wafer-level diamond substrate and wafer-level diamond substrate |
| TWI844269B (en) * | 2022-12-08 | 2024-06-01 | 大陸商西安奕斯偉材料科技股份有限公司 | Method and system for improving silicon wafer surface flatness |
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| TWI600071B (en) | 2017-09-21 |
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