CN107329154B - Method and device for realizing bit synchronization - Google Patents
Method and device for realizing bit synchronization Download PDFInfo
- Publication number
- CN107329154B CN107329154B CN201610285333.2A CN201610285333A CN107329154B CN 107329154 B CN107329154 B CN 107329154B CN 201610285333 A CN201610285333 A CN 201610285333A CN 107329154 B CN107329154 B CN 107329154B
- Authority
- CN
- China
- Prior art keywords
- sequence
- cyclic convolution
- rectangular
- bit
- data segment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 125000004122 cyclic group Chemical group 0.000 claims abstract description 108
- 238000004364 calculation method Methods 0.000 claims description 11
- 230000000875 corresponding effect Effects 0.000 description 14
- 238000007476 Maximum Likelihood Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/35—Constructional details or hardware or software details of the signal processing chain
- G01S19/37—Hardware or software details of the signal processing chain
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
A method of implementing bit synchronization, comprising: calculating a cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary; wherein N is an integer greater than or equal to 1; calculating the energy value of each candidate position according to the cyclic convolution sequence; and determining a bit flipping boundary according to the energy values of all the candidate positions.
Description
Technical Field
The present disclosure relates to, but not limited to, navigation technologies, and more particularly, to a method and apparatus for implementing bit synchronization.
Background
After the Global Positioning System (Global Positioning System) receiver finishes capturing the received signal, the receiver tracks the received signal and simultaneously performs bit synchronization, frame synchronization, demodulation and decoding on the received signal, so as to obtain the transmission time and navigation messages of the signal from the received signal and finally realize GPS navigation Positioning.
The bit synchronization is also called bit synchronization, that is, the receiver determines the bit start bit of the received signal according to a certain algorithm. For a navigation message modulated on a corresponding carrier wave at 50 bits per second (bps), each navigation message corresponds to 20C/a code periods (i.e., 1-bit data), each C/a code period includes a signal segment of 1 millisecond (ms), and a boundary point between two adjacent navigation messages is a bit flipping boundary. The bit synchronization is the position of the bit flipping boundary of the navigation message, and is the basis for demodulating the navigation message, measuring the pseudo range and realizing high-sensitivity tracking. Therefore, the receiver must estimate the position of the bit flip boundary, i.e., achieve bit synchronization.
Related methods for implementing bit synchronization include a histogram method, a Maximum Likelihood (ML) method, and the like.
The receiver correlates the received signal with the generated C/A code, mixes the correlated signal with the generated I-path local carrier signal and Q-path local carrier signal respectively to obtain an I-path mixed signal and a Q-path mixed signal, and integrates the 1 millisecond (ms) I-path mixed signal and the 1ms Q-path mixed signal respectively to obtain an I-path integrated signal and a Q-path integrated signal. The histogram method is to process the signal after I path integration or the signal after Q path integration.
Fig. 1 is a schematic diagram of a histogram method, and as shown in fig. 1, the histogram method is a very basic bit synchronization algorithm. The method comprises the steps that 20 integrated signals (one integrated signal is obtained by integrating a mixed signal of 1ms) are taken as a period to carry out statistics on symbol changes of 20 candidate positions, each candidate position corresponds to a counter, and when the symbol of the ith integrated signal changes to the (i +1) th integrated signal, the counter corresponding to the candidate position of the (i +1) th integrated signal is added with 1; when the sign of the signal after the ith integration is not changed to the sign of the signal after the (i +1) th integration, the counter corresponding to the candidate position corresponding to the signal after the (i +1) th integration is not increased by 1.
Every time 20 integrated signals are counted, whether one counter of the 20 counters reaches a threshold N is judged1And if so, the candidate position corresponding to the counter is the bit flipping boundary. The counter corresponding to the 4 th candidate position in fig. 1 reaches the threshold N1Then the 4 th candidate position is the bit flip boundary. Namely, the signal of 1-3 ms belongs to one bit, and the signal of 4-23 ms belongs to the next bit.
If at least two of the 20 counters reach the threshold N2Then the 20 counters are cleared and bit synchronization is resumed.
The histogram method essentially performs hard decision on the integrated signal, and then examines whether the symbols of two adjacent C/a code periods change to implement bit synchronization, which has the disadvantages that the performance of the integrated signal becomes worse and worse as the strength of the integrated signal becomes weaker, and the time required for synchronization becomes longer and longer.
The ML method is to accumulate 20 continuous integrated signals after each candidate position, calculate the bit energy of the accumulated signals, and then perform incoherent accumulation on the bit energy for a period of time, so that the candidate position corresponding to the maximum incoherent accumulation result in the 20 candidate positions is the bit flipping boundary.
Assume that the integrated model of the signal received by the receiver at the kth epoch (i.e., 1ms) is as shown in equation (1).
rk＝Abk+nk(1)
Where, when k is epoch, rkIs the signal integrated during the kth epoch, A is the signal power, bkFor the integrated signal assumed at the k epoch, nkThe k epoch is the mean 0 and the variance is
White additive gaussian noise.
A likelihood function comprising a vector of N integrated signals may be represented by the product of the likelihood functions of each correlated signal, as shown in equation (2).
Wherein, bkThe integrated signal, assumed for the k epoch, is a candidate bit flip boundary,
to round down, σ0Is the noise variance, N is the number of integrated signals, and a is the signal power.
To find the bit-flipping boundary, equation (2) requires maximization under a, b variable. Obviously, the first term in equation (2) is independent of the variables, a, b, and can be ignored. The latter two terms can be viewed as 2 | A | f (r, b) + N | A |2Therefore, to maximize the formula (2), it is sufficient to maximize f (r, b), wherein,
wherein, K is N/20+ 1.
By observation, it can be easily found that when bkAnd
when the signs are equal, equation (3) reaches a maximum. According to the formula x · sign (x) ═ x |, the maximization of the formula (3) is equivalent to the maximization of the formula (4).
The maximum likelihood method can then be summarized as obtaining the bit flipping boundary using equation (5).
Wherein,
the boundary is bit flipped.
The ML method only requires several seconds to achieve good bit synchronization at signal strengths above 20 decibel-hertz (dB-Hz). The method usually needs to fix a longer data segment to ensure the synchronization performance under the condition of low signal-to-noise ratio, but for a fixed-length data segment, if the data segment is very long, the storage capacity is correspondingly required to be large, the processing complexity is improved, the processing time is long, and the real-time processing cannot be obtained.
Disclosure of Invention
The embodiment of the invention provides a method and a device for realizing bit synchronization, which can reduce the processing complexity and shorten the processing time so as to obtain real-time processing.
The embodiment of the invention provides a method for realizing bit synchronization, which comprises the following steps:
calculating a cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary; wherein N is an integer greater than or equal to 1;
calculating the energy value of each candidate position according to the cyclic convolution sequence;
and determining a bit flipping boundary according to the energy values of all the candidate positions.
Optionally, N is an integer multiple of 20, and the rectangular sequence is a sequence with a length of 20 and an amplitude of 1.
Optionally, the calculating a cyclic convolution sequence of the N integrated signals used for determining the bit flipping boundary and the rectangular sequence includes:
according to the formula
Calculating the cyclic convolution sequence;
wherein y (n1) is the n1 th element of the cyclic convolution sequence, rlIs the l-th integrated signal.
Optionally, the calculating an energy value of each candidate position according to the cyclic convolution sequence includes:
according to the formula
Calculate the [ (+ 1)% 20]An energy value for each candidate location;
wherein y (20k +) is the (20k +) th element of the cyclic convolution sequence, CC[(+1)％20]Is [ (+ 1)% 20]An energy value of each candidate location.
Optionally, the determining the bit flipping boundary according to the energy values of all the candidate positions includes:
and determining the candidate position with the maximum energy value as the bit flipping boundary.
The embodiment of the invention also provides a method for realizing bit synchronization, which comprises the following steps:
calculating a cyclic convolution sequence of the data segments and the rectangular sequence; continuously calculating a cyclic convolution sequence of the next data segment and the rectangular sequence until the length of all the data segments is N; wherein N is an integer greater than or equal to 1;
calculating the energy value of each candidate position according to the cyclic convolution sequence of all the data segments and the rectangular sequence;
and determining a bit flipping boundary according to the energy values of all the candidate positions.
Optionally, N is an integer multiple of 20, the rectangular sequence is a sequence with a length of 20 and an amplitude of 1, and the length of each data segment is an integer multiple of 20.
Optionally, the calculating a cyclic convolution sequence of the data segment and the rectangular sequence includes:
according to the formula
Calculating a cyclic convolution sequence of the mth data segment and the rectangular sequence;
where M is the number of the integrated signals in the mth data segment, rlIs the l-th integrated signal, ym(n2) is the n2 th element of the cyclic convolution sequence of the m-th data segment and the rectangular sequence.
Optionally, the calculating an energy value of each candidate position according to the cyclic convolution sequence of all the data segments and the rectangular sequence includes:
according to the formula
Calculating an energy value of [ (+ 1)% 20] th candidate position;
wherein, CC[(+1)％20]Is [ (+ 1)% 20]Energy value of each candidate position, y0(+20l) is the (+20l) th element, y, of the cyclic convolution sequence of the 0 th data segment with the rectangular sequencem(+ (M +1) M) is the (+ (M +1) M) th element, y, of the cyclic convolution sequence of the mth data segment and the rectangular sequencem+1(+ (M +1) M) is the (+ (M +1) M element of the cyclic convolution sequence of the (M +1) th data segment and the rectangular sequence, yNM-1(+20l + N) is the (+20l + N) th element of the cyclic convolution sequence of the (N/M-1) th data segment and the rectangular sequence。
Optionally, the determining the bit flipping boundary according to the energy values of all the candidate positions includes:
and determining the candidate position corresponding to the maximum energy value as the bit flipping boundary.
The embodiment of the present invention further provides a device for implementing bit synchronization, including:
a first calculation module, configured to calculate a cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary; wherein N is an integer greater than or equal to 1; calculating the energy value of each candidate position according to the cyclic convolution sequence;
a first determining module for determining a bit flipping boundary according to the cyclic convolution of all candidate positions.
Optionally, the first calculating module is specifically configured to calculate a cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary in the following manner:
according to the formula
Calculating the cyclic convolution sequence;
wherein y (n1) is the n1 th element of the cyclic convolution sequence, rlIs the l-th integrated signal.
Optionally, the first calculating module is specifically configured to implement the calculating the energy value of each candidate position according to the cyclic convolution sequence by using the following method:
according to the formula
Calculate the [ (+ 1)% 20]An energy value for each candidate location;
wherein y (20k +) is the (20k +) th element of the cyclic convolution sequence, CC[(+1)％20]Is [ (+ 1)% 20]An energy value of each candidate location.
Optionally, the first determining module is specifically configured to:
and determining the candidate position with the maximum energy value as the bit flipping boundary.
The embodiment of the present invention further provides a device for implementing bit synchronization, including:
the second calculation module is used for calculating a cyclic convolution sequence of the data segment and the rectangular sequence; continuously calculating a cyclic convolution sequence of the next data segment and the rectangular sequence until the length of all the data segments is N; wherein N is an integer greater than or equal to 1;
the third calculation module is used for calculating the energy value of each candidate position according to the cyclic convolution sequence of all the data segments and the rectangular sequence;
and the second determining module is used for determining the bit flipping boundary according to the energy values of all the candidate positions.
Optionally, the second calculating module is specifically configured to:
according to the formula
Calculating a cyclic convolution sequence of the mth data segment and the rectangular sequence;
where M is the number of the integrated signals in the mth data segment, rlIs the l-th integrated signal, ym(n2) is the n2 th element of the cyclic convolution sequence of the m-th data segment and the rectangular sequence.
Optionally, the third computing module is specifically configured to:
according to the formula
Calculating an energy value of [ (+ 1)% 20] th candidate position;
wherein, CC[(+1)％20]Is [ (+ 1)% 20]Energy value of each candidate position, y0(+20l) is the (+20l) th element, y, of the cyclic convolution sequence of the 0 th data segment with the rectangular sequencem(+ (M +1) M) is the (+ (M +1) M) th element of the cyclic convolution sequence of the mth data segment and the rectangular sequence,ym+1(+ (M +1) M) is the (+ (M +1) M element of the cyclic convolution sequence of the (M +1) th data segment and the rectangular sequence, yNM-1(+20l + N) is the (+20l + N) th element of the cyclic convolution sequence of the (N/M-1) th data segment and the rectangular sequence.
Optionally, the second determining module is specifically configured to:
and determining the candidate position corresponding to the maximum energy value as the bit flipping boundary.
Compared with the related art, the technical scheme of the embodiment of the invention comprises the following steps: calculating a cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary; wherein N is an integer greater than or equal to 1; calculating the energy value of each candidate position according to the cyclic convolution sequence; and determining a bit flipping boundary according to the energy values of all the candidate positions. According to the scheme of the embodiment of the invention, the energy value of each candidate position is calculated by calculating the cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit reversal boundary, so that the bit reversal boundary is determined.
The technical scheme of the embodiment of the invention also comprises the following steps: calculating a cyclic convolution sequence of the data segments and the rectangular sequence; continuously calculating a cyclic convolution sequence of the next data segment and the rectangular sequence until the length of all the data segments is N; wherein N is an integer greater than or equal to 1; calculating the energy value of each candidate position according to the cyclic convolution sequence of all the data segments and the rectangular sequence; and determining a bit flipping boundary according to the energy values of all the candidate positions. According to the scheme of the embodiment of the invention, the N integrated signals are divided into a plurality of data segments, the cyclic convolution sequence of each data segment and the rectangular sequence is independently calculated, the N integrated signals do not need to be stored, and only each data segment needs to be stored, so that the storage capacity is reduced, the processing complexity is reduced, and the real-time processing is realized.
Drawings
The accompanying drawings in the embodiments of the present invention are described below, and the drawings in the embodiments are provided for further understanding of the present invention, and together with the description serve to explain the present invention without limiting the scope of the present invention.
FIG. 1 is a schematic diagram of a related art histogram method;
FIG. 2 is a flow chart of a method for implementing bit synchronization according to an embodiment of the present invention;
FIG. 3 is a flowchart of another method for implementing bit synchronization according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of an apparatus for implementing bit synchronization according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another apparatus for implementing bit synchronization according to an embodiment of the present invention.
Detailed Description
The following further description of the present invention, in order to facilitate understanding of those skilled in the art, is provided in conjunction with the accompanying drawings and is not intended to limit the scope of the present invention. In the present application, the embodiments and various aspects of the embodiments may be combined with each other without conflict.
Referring to fig. 2, an embodiment of the present invention provides a method for implementing bit synchronization, including:
In this step, N is an integer greater than or equal to 1.
Optionally, N is an integer multiple of 20, and the rectangular sequence is a sequence with a length of 20 and an amplitude of 1.
Wherein the rectangular sequence
D is the length of the bit (e.g., 20 ms).
In this step, calculating a cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary includes:
the cyclic convolution sequence is calculated according to equation (6).
Wherein y (n1) is the n1 th element of the cyclic convolution sequence, rlIs the l-th integrated signal. Step 201, calculating an energy value of each candidate position according to the cyclic convolution sequence. The method comprises the following steps:
calculating an energy value of [ (+ 1)% 20] th candidate position according to formula (7);
wherein y (20k +) is the (20k +) th element of the cyclic convolution sequence, CC[(+1)％20]Is [ (+ 1)% 20]An energy value of each candidate location.
In this step, determining the bit flipping boundary according to the energy values of all candidate positions includes:
and determining the candidate position corresponding to the maximum energy value as a bit flipping boundary.
Referring to fig. 3, an embodiment of the present invention further provides a method for implementing bit synchronization, including:
In this step, N is an integer greater than or equal to 1.
Optionally, N is an integer multiple of 20, the rectangular sequence is a sequence with a length of 20 and a magnitude of 1, and the length of each data segment is an integer multiple of 20.
In this step, a cyclic convolution sequence of the mth data segment and the rectangular sequence is calculated according to formula (8).
Where M is the number of integrated signals in the mth data segment, rlIs the l-th integrated signal, ym(n2) is the n2 th element of the cyclic convolution sequence of the m-th data segment with the rectangular sequence.
When n2 takes other values, ym(n2)＝0。
the energy value of the [ (+ 1)% 20] th candidate position is calculated according to formula (9).
Wherein, CC[(+1)％20]Is [ (+ 1)% 20]Energy value of each candidate position, y0(+20l) is the (+20l) th element, y, of the circular convolved sequence of the 0 th data segment with the rectangular sequencem(+ (M +1) M) is the (+ (M +1) M) th element, y, of the cyclic convolution sequence of the mth data segment and the rectangular sequencem+1(+ (M +1) M) is the (+ (M +1) M element of the cyclic convolution sequence of the (M +1) th data segment and the rectangular sequence, yN/M-1(+20l + N) is the (+20l + N) th element of the (N/M-1) th data segment and rectangular sequence of cyclic convolutions.
and determining the candidate position corresponding to the maximum energy value as a bit flipping boundary.
To better illustrate the above method, an example is given below in which N is 60 and M is 20:
first, a cyclic convolution sequence of 3(N/M) data segments and a rectangular sequence is calculated, respectively, wherein,
r0(n)＝(r0,r1,…,r19)，r1(n)＝(r20,r21,…,r39)，r2(n)＝(r40,r41,…,r59) The integrated signals for three data segments, each data segment comprising 20 integrated signals.
Then, a cyclic convolution sequence y of each data segment and the rectangular sequence is calculated according to the time sequence0(n2)，y1(n2)，y2(n2)。
Wherein,
i.e. y0(0)＝r0，y0(1)＝r0+r1，y0(2)＝r0+r1+r2，……，y0(18)＝r0+r1+r2+…r18；
y0(19)＝r0+r1+r2+…+r19，y0(20)＝r1+r2+…+r19，y0(21)＝r2+r3+…+r19，……，y0(38)＝r19。
I.e. y1(20)＝r20，y1(21)＝r20+r21，y1(22)＝r20+r21+r22，……，y1(38)＝r20+r21+r22+…+r38；
y1(39)＝r20+r21+r22+…+r39，y1(40)＝r21+r22+…+r39，y1(41)＝r22+r23+…+r39，……，y1(58)＝r39。
I.e. y2(40)＝r40，y2(41)＝r40+r41，y2(42)＝r40+r41+r42，……，y2(58)＝r40+r41+r42+…+r58；
y2(59)＝r40+r41+r42+…+r59，y2(60)＝r41+r42+r43+…+r59，y2(61)＝r42+r43+r44+…+r59，……，y2(78)＝r39。
Then calculate the energy value of each candidate position, i.e.
Then it is determined that,
CC0＝|y0(19)+|y0(19+20)+y1(19+20)|+|y1(19+40)+y2(19+40)|+|y2(19+60)
CC1＝|y0(0)|+|y0(20)+y1(20)+|y1(40)+y2(40)|+|y2(60)
CC2＝|y0(1)|+|y0(1+20)+y1(1+20)|+|y1(1+40)+y2(1+40)|+|y2(1+60)|
CC3＝|y0(2)|+|y0(2+20)+y1(2+20)|+|y1(2+40)+y2(2+40)|+|y2(2+60)|
CC4＝|y0(3)|+|y0(3+20)+y1(3+20)|+|y1(3+40)+y2(3+40)|+|y2(3+60)|
CC5＝|y0(4)|+|y0(4+20)+y1(4+20)|+|y1(4+40)+y2(4+40)|+|y2(4+60)|CC6＝|y0(5)|+|y0(5+20)+y1(5+20)|+|y1(5+40)+y2(5+40)+|y2(5+60)|CC7＝|y0(6)|+|y0(6+20)+y1(6+20)|+|y1(6+40)+y2(6+40)|+|y2(6+60)……
CC19＝|y0(18)+|y0(18+20)+y1(18+20)|+|y1(18+40)+y2(18+40)|+|y2(18+60)|
and finally, determining the candidate position corresponding to the maximum energy value as a bit flipping boundary. .
The method adopts a mode of inputting while calculating and outputting, does not require large storage capacity, and greatly reduces the operation amount and the processing time delay. If the processing operation speed is fast, real-time processing can be realized.
Referring to fig. 4, an embodiment of the present invention further provides an apparatus for implementing bit synchronization, including:
a first calculation module, configured to calculate a cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary; wherein N is an integer greater than or equal to 1; calculating the energy value of each candidate position according to the cyclic convolution sequence;
a first determining module for determining a bit flipping boundary according to the cyclic convolution of all candidate positions.
In the apparatus according to the embodiment of the present invention, the first calculating module is specifically configured to calculate a cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary in the following manner:
according to the formula
Calculating a cyclic convolution sequence;
wherein y (n1) is the n1 th element of the cyclic convolution sequence, rlIs the l-th integrated signal.
In the apparatus according to the embodiment of the present invention, the first calculating module is specifically configured to calculate the energy value of each candidate position according to the cyclic convolution sequence in the following manner:
according to the formula
Calculate the [ (+ 1)% 20]An energy value for each candidate location;
wherein y (20k +) is the (20k +) th element of the cyclic convolution sequence, CC[(+1)％20]Is [ (+ 1)% 20]An energy value of each candidate location.
In the apparatus according to the embodiment of the present invention, the first determining module is specifically configured to:
and determining the candidate position corresponding to the maximum energy value as a bit flipping boundary.
Referring to fig. 5, an embodiment of the present invention further provides an apparatus for implementing bit synchronization, including:
the second calculation module is used for calculating a cyclic convolution sequence of the data segment and the rectangular sequence; continuously calculating a cyclic convolution sequence of the next data segment and the rectangular sequence until the length of all the data segments is N; wherein N is an integer greater than or equal to 1;
the third calculation module is used for calculating the energy value of each candidate position according to the cyclic convolution sequence of all the data segments and the rectangular sequence;
and the second determining module is used for determining the bit flipping boundary according to the energy values of all the candidate positions.
In the apparatus according to the embodiment of the present invention, the second calculation module is specifically configured to:
according to the formula
Calculating a cyclic convolution sequence of the mth data segment and the rectangular sequence;
where M is the number of integrated signals in the mth data segment, rlIs the l-th integrated signal, ym(n2) is the n2 th element of the cyclic convolution sequence of the m-th data segment with the rectangular sequence.
In the apparatus according to the embodiment of the present invention, the third calculating module is specifically configured to:
according to the formula
Calculating an energy value of [ (+ 1)% 20] th candidate position;
wherein, CC[(+1)％20]Is [ (+ 1)% 20]Energy value of each candidate position, y0(+20l) is the (+20l) th element, y, of the circular convolved sequence of the 0 th data segment with the rectangular sequencem(+ (M +1) M) is the (+ (M +1) M) th element, y, of the cyclic convolution sequence of the mth data segment and the rectangular sequencem+1(+ (M +1) M) is the (+ (M +1) M element of the cyclic convolution sequence of the (M +1) th data segment and the rectangular sequence, yN/M-1(+20l + N) is the (+20l + N) th element of the (N/M-1) th data segment and rectangular sequence of cyclic convolutions.
In the apparatus according to the embodiment of the present invention, the second determining module is specifically configured to:
and determining the candidate position corresponding to the maximum energy value as a bit flipping boundary.
It should be noted that the above-mentioned embodiments are only for facilitating the understanding of those skilled in the art, and are not intended to limit the scope of the present invention, and any obvious substitutions, modifications, etc. made by those skilled in the art without departing from the inventive concept of the present invention are within the scope of the present invention.
Claims (12)
1. A method for implementing bit synchronization, comprising:
calculating a cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary; where N is an integer greater than or equal to 1, rectangular sequence
D is the length of the bit;
calculating the energy value of each candidate position according to the cyclic convolution sequence;
determining a bit flipping boundary according to the energy values of all candidate positions;
wherein said calculating an energy value for each candidate location from the cyclic convolution sequence comprises:
according to the formula
Calculate the [ (+ 1)% 20]An energy value for each candidate location;
wherein y (20k +) is the (20k +) th element of the cyclic convolution sequence, CC[(+1)％20]Is [ (+ 1)% 20]An energy value for each candidate position, K ═ N/20+ 1; the boundary is flipped for the candidate bit.
2. The method of claim 1, wherein computing a cyclic convolution sequence of the N integrated signals used to determine the bit-flipping boundaries with a rectangular sequence comprises:
according to the formula
Calculating the cyclic convolution sequence;
wherein y (n1) is the n1 th element of the cyclic convolution sequence, rlIs the l-th integrated signal.
3. The method of claim 1, wherein determining the bit flipping boundary according to the energy values of all candidate locations comprises:
and determining the candidate position with the maximum energy value as the bit flipping boundary.
4. A method for implementing bit synchronization, comprising:
calculating a cyclic convolution sequence of each data segment and the rectangular sequence; wherein each data segment comprises M integrated signals, and the total length of all data segments is N; m and N are integers which are more than or equal to 1; rectangular sequence
D is the length of the bit;
calculating the energy value of each candidate position according to the cyclic convolution sequence of all the data segments and the rectangular sequence;
determining a bit flipping boundary according to the energy values of all candidate positions;
wherein the calculating an energy value for each candidate location from a cyclic convolution sequence of all data segments and a rectangular sequence comprises:
according to the formula
Calculating an energy value of [ (+ 1)% 20] th candidate position;
wherein, CC[(+1)％20]Is [ (+ 1)% 20]Energy value of each candidate position, y0(+20l) is the (+20l) th element, y, of the cyclic convolution sequence of the 0 th data segment with the rectangular sequencem(+ (M +1) M) is the (+ (M +1) M) th element, y, of the cyclic convolution sequence of the mth data segment and the rectangular sequencem+1(+ (M +1) M) is the (+ (M +1) M element of the cyclic convolution sequence of the (M +1) th data segment and the rectangular sequence, yN/M-1(+20l + N) is the (+20l + N) th element of the (N/M-1) th data segment and the cyclic convolution sequence of the rectangular sequence, l is the serial number of the integrated signal, and M is the number of the integrated signal in the mth data segment; the boundary is flipped for the candidate bit.
5. The method of claim 4, wherein computing the sequence of circular convolutions of the data segments with the rectangular sequence comprises:
according to the formula
Calculating a cyclic convolution sequence of the mth data segment and the rectangular sequence;
where M is the number of the integrated signals in the mth data segment, rlIs the l-th integrated signal, ym(n2) is the m-thAn nth 2 element of a cyclic convolution sequence of a data segment and the rectangular sequence.
6. The method of claim 4, wherein determining the bit flipping boundary according to the energy values of all candidate locations comprises:
and determining the candidate position corresponding to the maximum energy value as the bit flipping boundary.
7. An apparatus for implementing bit synchronization, comprising:
a first calculation module, configured to calculate a cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary; where N is an integer greater than or equal to 1, rectangular sequence
D is the length of the bit; calculating the energy value of each candidate position according to the cyclic convolution sequence;
a first determining module, configured to determine a bit flipping boundary according to the cyclic convolution of all candidate positions;
the first calculating module is specifically configured to implement the calculating of the energy value of each candidate position according to the cyclic convolution sequence by using the following method:
according to the formula
Calculate the [ (+ 1)% 20]An energy value for each candidate location;
wherein y (20k +) is the (20k +) th element of the cyclic convolution sequence, CC[(+1)％20]Is [ (+ 1)% 20]An energy value for each candidate position, K ═ N/20+ 1; the boundary is flipped for the candidate bit.
8. The apparatus of claim 7, wherein the first computing module is specifically configured to implement the computing of the cyclic convolution sequence of the N integrated signals and the rectangular sequence for determining the bit flipping boundary by:
according to the formula
Calculating the cyclic convolution sequence;
wherein y (n1) is the n1 th element of the cyclic convolution sequence, rlIs the l-th integrated signal.
9. The apparatus of claim 7, wherein the first determining module is specifically configured to:
and determining the candidate position with the maximum energy value as the bit flipping boundary.
10. An apparatus for implementing bit synchronization, comprising:
the second calculation module is used for calculating a cyclic convolution sequence of each data segment and the rectangular sequence; wherein each data segment comprises M integrated signals, and the total length of all data segments is N; m and N are integers which are more than or equal to 1; rectangular sequence
D is the length of the bit;
the third calculation module is used for calculating the energy value of each candidate position according to the cyclic convolution sequence of all the data segments and the rectangular sequence;
the second determining module is used for determining a bit flipping boundary according to the energy values of all the candidate positions;
wherein the third computing module is specifically configured to:
according to the formula
Calculating an energy value of [ (+ 1)% 20] th candidate position;
wherein, CC[(+1)％20]Is [ (+ 1)% 20]A candidate positionEnergy value of y0(+20l) is the (+20l) th element, y, of the cyclic convolution sequence of the 0 th data segment with the rectangular sequencem(+ (M +1) M) is the (+ (M +1) M) th element, y, of the cyclic convolution sequence of the mth data segment and the rectangular sequencem+1(+ (M +1) M) is the (+ (M +1) M element of the cyclic convolution sequence of the (M +1) th data segment and the rectangular sequence, yN/M-1(+20l + N) is the (+20l + N) th element of the (N/M-1) th data segment and the cyclic convolution sequence of the rectangular sequence, l is the serial number of the integrated signal, and M is the number of the integrated signal in the mth data segment; the boundary is flipped for the candidate bit.
11. The apparatus of claim 10, wherein the second computing module is specifically configured to:
according to the formula
Calculating a cyclic convolution sequence of the mth data segment and the rectangular sequence;
where M is the number of the integrated signals in the mth data segment, rlIs the l-th integrated signal, ym(n2) is the n2 th element of the cyclic convolution sequence of the m-th data segment and the rectangular sequence.
12. The apparatus of claim 10, wherein the second determining module is specifically configured to:
and determining the candidate position corresponding to the maximum energy value as the bit flipping boundary.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610285333.2A CN107329154B (en) | 2016-04-29 | 2016-04-29 | Method and device for realizing bit synchronization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610285333.2A CN107329154B (en) | 2016-04-29 | 2016-04-29 | Method and device for realizing bit synchronization |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107329154A CN107329154A (en) | 2017-11-07 |
| CN107329154B true CN107329154B (en) | 2020-09-18 |
Family
ID=60192404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610285333.2A Active CN107329154B (en) | 2016-04-29 | 2016-04-29 | Method and device for realizing bit synchronization |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107329154B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0413325A (en) * | 1990-05-01 | 1992-01-17 | Nippon Telegr & Teleph Corp <Ntt> | Bit phase synchronizing circuit |
| CN1419654A (en) * | 2000-01-21 | 2003-05-21 | 艾利森公司 | Method, mobile stations and systems for acquiring global positioning system timing information |
| CN102355279A (en) * | 2011-11-17 | 2012-02-15 | 中国航天科工信息技术研究院 | Method and system for diversity maximum likelihood spread spectrum communication bit synchronization |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7042930B2 (en) * | 2002-06-06 | 2006-05-09 | The Aerospace Corporation | Spread spectrum bit boundary correlation search acquisition system |
| US8542714B2 (en) * | 2005-07-29 | 2013-09-24 | U-Blox Ag | Method and system for reconstructing time of transmit from assisted or weak signal GPS observations |
-
2016
- 2016-04-29 CN CN201610285333.2A patent/CN107329154B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0413325A (en) * | 1990-05-01 | 1992-01-17 | Nippon Telegr & Teleph Corp <Ntt> | Bit phase synchronizing circuit |
| CN1419654A (en) * | 2000-01-21 | 2003-05-21 | 艾利森公司 | Method, mobile stations and systems for acquiring global positioning system timing information |
| CN102355279A (en) * | 2011-11-17 | 2012-02-15 | 中国航天科工信息技术研究院 | Method and system for diversity maximum likelihood spread spectrum communication bit synchronization |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107329154A (en) | 2017-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20050250466A1 (en) | Method and apparatus for improving MLSE in the presence of co-channel interferer for GSM/GPRS systems | |
| US20170041175A1 (en) | Co-channel spatial separation using matched doppler filtering | |
| WO2007133156A2 (en) | Delay-doppler channel response demodulation method | |
| JP2011504052A (en) | Suppressing multipath effects on received SPS signals | |
| US10313172B2 (en) | System and method for enhanced channel estimation using tap-dependent frequency offset (FO) estimation | |
| EP3621259B1 (en) | Method and device for fsk/gfsk demodulation | |
| CN108512791A (en) | Satellite-borne AIS demodulation method based on timing frequency offset compensation | |
| CN111918214A (en) | Device for determining a distance based on a transmission signal | |
| CN104459734A (en) | Beidou satellite navigation signal capturing method based on NH code element jumping detection | |
| CN108196274A (en) | Be applicable in BOC (n, n) signal without fuzziness catching method and device | |
| CN103941269A (en) | PN code capturing method used for satellite navigation system | |
| WO2013140911A1 (en) | Signal search method, signal search program, signal search device, global navigation satellite system (gnss) signal receiver, and information terminal | |
| CN106656304B (en) | Correlation-based satellite-borne AIS signal receiving and processing method and device | |
| CN107329154B (en) | Method and device for realizing bit synchronization | |
| EP3945700B1 (en) | Method and system for adjusting the bandwidth of a frequency domain smoothing filter for channel tracking loop in ofdm communication system | |
| CN103763233A (en) | GSM external radiation radar signal processing method based on digital modulation and demodulation | |
| CN115296698B (en) | Signal Capture Method for High Dynamic Satellite Communication System | |
| US9942061B2 (en) | Multipath selection method and device, and storage medium | |
| US9973368B2 (en) | Fine timing | |
| CN106896382B (en) | A kind of navigation signal catching method and device | |
| CN111796308B (en) | Method and device for capturing satellite signal, storage medium and electronic equipment | |
| CN107305254B (en) | Method and device for realizing bit synchronization | |
| CN112731484A (en) | Satellite navigation positioning receiver and bit synchronization method of receiver | |
| CN109547129B (en) | A Step-Weighted Tong Detection Method | |
| CN1535506A (en) | Method and apparatus for bandwidth estimation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |