CN107317569A - Data trigger device - Google Patents
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- CN107317569A CN107317569A CN201710455286.6A CN201710455286A CN107317569A CN 107317569 A CN107317569 A CN 107317569A CN 201710455286 A CN201710455286 A CN 201710455286A CN 107317569 A CN107317569 A CN 107317569A
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- 230000005540 biological transmission Effects 0.000 claims description 37
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- 230000001413 cellular effect Effects 0.000 description 13
- 238000010276 construction Methods 0.000 description 13
- 238000013461 design Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
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- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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Abstract
It is integrated in the invention discloses a kind of data trigger device in digital integrated circuit chip and data trigger device includes first module structure, first module structure includes：The master-slave register element circuit of more than two and a shared clock phase generation circuit；The structure of every master-slave register element circuit is identical and handles the input and output of a data respectively；Clock phase generation circuit provides the positive phase signals of clock and clock inversion signal to each master-slave register element circuit simultaneously, and the data output signal of every master-slave register element circuit switches to data input signal in the rising edge of the positive phase signals of clock and latched；By in first module structure common clock phase generation circuit reduce in digital integrated circuit chip the total quantity of included clock phase generation circuit, so as to save chip area, reduction chip power-consumption and reduce clock offset between every data.
Description
Technical field
The present invention relates to semiconductor integrated circuit design field, more particularly to a kind of data trigger (DFF) device.
Background technology
Data trigger is in the design of modern large-scale digital ic, particularly in synchronous sequence IC design
The middle very important role of performer, it is the execution unit of timeticks device.At present, data trigger is in digital integrated electronic circuit
In area accounting can reach 30%~50%.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of data trigger device, can reduce data trigger in number
The dynamic power consumption that area accounting and reduction in word integrated circuit are brought by clock upset.
In order to solve the above technical problems, the data trigger device that the present invention is provided is integrated in digital integrated circuit chip
And data trigger device includes first module structure, the first module structure includes：
The master-slave register element circuit of more than two and a shared clock phase generation circuit.
The structure of everybody the master-slave register element circuit is identical and handles the input and output of a data respectively.
The clock phase generation circuit provides the positive phase signals of clock and clock inversion signal to each master-slave register simultaneously
Device element circuit, the rising edge of the data output signal of everybody the master-slave register element circuit in the positive phase signals of the clock
Switch to data input signal and latch.
The digital integrated electronic circuit is reduced by sharing the clock phase generation circuit in the first module structure
The total quantity of included clock phase generation circuit in chip, so as to save chip area, reduction chip power-consumption and reduce each
Clock offset between the data of position.
Further improve is that the clock phase generation circuit includes the first CMOS inverter and the second CMOS inverter,
The input connection clock input signal of first CMOS inverter, the output end connection of first CMOS inverter is described
The input of second CMOS inverter simultaneously exports the clock inversion signal, the output end output institute of second CMOS inverter
State the positive phase signals of clock.
Further improve is that everybody includes the master-slave register element circuit：
3rd CMOS inverter, its input connects the data input signal.
First cmos transmission gate, its input connects the output end of the 3rd CMOS inverter；First CMOS is passed
The grid of defeated door PMOS in parallel connects the positive phase signals of clock, the grid of NMOS tube connects the clock inversion signal.
First latch, including the 4th CMOS inverter and first band clock control CMOS inverter；4th CMOS
The input of phase inverter connects the output end of the first band clock control CMOS inverter and connects the first CMOS transmission
The output end of door, the output end of the 4th CMOS inverter connects the input of the first band clock control CMOS inverter
End；Include the first PMOS, the second PMOS, the first NMOS tube and the 2nd NMOS of series connection with clock control CMOS inverter
Pipe, the source electrode connection supply voltage of first PMOS, drain electrode connection second PMOS of first PMOS
Source electrode, the source ground of first NMOS tube, the source electrode of drain electrode connection second NMOS tube of first NMOS tube, institute
State the drain electrode of drain electrode connection second PMOS of the second NMOS tube and as the output end with clock control CMOS inverter,
The grid of first PMOS connects the grid of first NMOS tube and is used as the input with clock control CMOS inverter
The grid of end, the grid of second PMOS and second NMOS tube is used to connect a pair of clock signals anti-phase each other；
The grid connection clock inversion signal of second PMOS of the first band clock control CMOS inverter, the first band
The grid connection positive phase signals of clock of second NMOS tube of clock control CMOS inverter.
Second cmos transmission gate, its input connects the output end of the 4th CMOS inverter；2nd CMOS is passed
The grid of defeated door PMOS in parallel connects the clock inversion signal, the grid of NMOS tube connects the positive phase signals of clock.
Second latch, including the 5th CMOS inverter and the second band clock control CMOS inverter, during second band
Clock CMOS inverter is identical with the structure of the first band clock control CMOS inverter；5th CMOS inverter
Input connects the output of the described second output end with clock control CMOS inverter and connection second cmos transmission gate
End, the output end of the 5th CMOS inverter connects the described second input with clock control CMOS inverter；Described
The grid connection positive phase signals of clock of two second PMOSs with clock control CMOS inverter, clock during second band
The grid connection clock inversion signal of second NMOS tube of CMOS inverter processed.
Hex inverter, its input connects the output end of the 5th phase inverter, the output end of the hex inverter
Export the data output signal.
The cellular construction of data trigger device of the present invention is the master-slave register that first module structure uses more than two
Element circuit and a shared clock phase generation circuit of the master-slave register element circuit of more than two, relative to existing number
It is that second unit structure combines a clock phase using a master-slave register element circuit according to the cellular construction of trigger device
Often increasing a master-slave register element circuit in the structure type of generation circuit, first module structure of the invention will be reduced
One clock phase generation circuit, can thus reduce the area shared by clock phase generation circuit, so as to reduce data-triggered
Area accounting of the device in digital integrated electronic circuit, the total bit of the data trigger employed in digital integrated electronic circuit is more
When, the area of the clock phase generation circuit of reduction of the present invention is also bigger, the reduction to the area of whole digital integrated electronic circuit
Can be bigger.
Further, since the present invention can reduce the quantity of the clock phase generation circuit in digital integrated electronic circuit, therefore it can reduce
Dynamic power consumption produced by being overturn due to clock phase generation circuit, therefore can effectively reduce chip power-consumption.
In addition, data bit different in the cellular construction of data trigger device of the present invention, which shares a clock, mutually produces electricity
Road, can effectively reduce Clock Tree distribution unit so that the synchronised clock offset of different pieces of information position is reduced so that sequential is easy
Convergence.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the cellular construction i.e. block diagram of second unit structure of available data trigger device；
Fig. 2 is the circuit diagram of the clock phase generation circuit in Fig. 1；
Fig. 3 is the circuit diagram of the master-slave register element circuit in Fig. 1；
Fig. 4 is the circuit diagram of CMOS inverter；
Fig. 5 is the circuit diagram of cmos transmission gate；
Fig. 6 is the circuit diagram with clock control CMOS inverter；
Fig. 7 is the cellular construction i.e. block diagram of first module structure of data trigger device of the embodiment of the present invention；
Fig. 8 is structural representation when data bit transmission process is realized using existing two second unit structures；
Fig. 9 is structural representation when data bit transmission process is realized using first module structure of the embodiment of the present invention.
Embodiment
As shown in figure 1, being the cellular construction i.e. block diagram of second unit structure 101 of available data trigger device；Second
Cellular construction 101 includes a master-slave register element circuit 103 and a clock phase generation circuit 102.
The master-slave register element circuit 103 handles the input and output of a data.
The clock phase generation circuit 102 simultaneously provide clock positive phase signals CLKpos and clock inversion signal CLKneg to
The master-slave register element circuit 103, the data output signal Q of the master-slave register element circuit 103 is in the clock
Positive phase signals CLKpos rising edge switches to data input signal D and latched.
As shown in Fig. 2 being the circuit diagram of the clock phase generation circuit in Fig. 1；The clock phase generation circuit 102 includes the
One CMOS inverter 201 and the second CMOS inverter 202, the input connection clock input of first CMOS inverter 201
Signal CLK, the output end of first CMOS inverter 201 connects input and the output of second CMOS inverter 202
The clock inversion signal CLKneg, the output end of second CMOS inverter 202 exports the positive phase signals of clock
CLKpos。
As shown in figure 3, being the circuit diagram of the master-slave register element circuit in Fig. 1；The master-slave register element circuit
103 include：
3rd CMOS inverter 203, its input connects the data input signal D.
First cmos transmission gate 204, its input connects the output end and the output end of the 3rd CMOS inverter 203
Signal be signal D inversion signal DB.The grid of first cmos transmission gate 204 PMOS in parallel connects the clock
Positive phase signals CLKpos, the grid of NMOS tube connect the clock inversion signal CLKneg.
First latch, including the 4th CMOS inverter 205 and first band clock control CMOS inverter 206；Described
The input of four CMOS inverters 205 connects the output end of the first band clock control CMOS inverter 206 and connection is described
The output end of first cmos transmission gate 204 and the signal of the output end are signal M0, the output of the 4th CMOS inverter 205
The input and the input end signal that end connects the first band clock control CMOS inverter 206 are signal M1.
As shown in figure 4, being the circuit diagram of CMOS inverter；Namely in the CMOS inverter 201 and 202 and Fig. 3 in Fig. 2
CMOS inverter 203,205,208 and 210 all using the circuit structure of the CMOS inverter shown in Fig. 4, show CMOS in Fig. 4
Phase inverter includes the PMOS MP101 and NMOS tube MN101 of series connection.
As shown in figure 5, being cmos transmission gate 204 and 207 in the circuit diagram of cmos transmission gate, Fig. 3 all using shown in Fig. 5
Cmos transmission gate circuit structure, show that cmos transmission gate includes PMOS MP102 and NMOS tube MN102 in parallel in Fig. 5.
As shown in fig. 6, being the circuit diagram with clock control CMOS inverter；Band clock control CMOS inverter in Fig. 3
206 and 209 all using the circuit structure of the cmos transmission gate shown in Fig. 6, includes the of series connection with clock control CMOS inverter
One PMOS MP1, the second PMOS MP2, the second NMOS tube MN2MN1 and the second NMOS tube, the source of the first PMOS MP1
Pole connects supply voltage, drain electrode connection the second PMOS MP2 of the first PMOS MP1 source electrode, described second
NMOS tube MN2MN1 source ground, the source electrode of drain electrode connection second NMOS tube of the second NMOS tube MN2MN1, institute
State drain electrode connection the second PMOS MP2 of the second NMOS tube drain electrode and as the output with clock control CMOS inverter
End, the grid of the first PMOS MP1 connects the grid of the second NMOS tube MN2MN1 and as band clock control CMOS
The input of phase inverter, the grid of the second PMOS MP2 and the grid of second NMOS tube are used to connect a pair each other
Anti-phase clock signal.
Return to as shown in figure 3, the second PMOS MP2 of the first band clock control CMOS inverter 206 grid
Pole connects clock inversion signal CLKneg, the grid of second NMOS tube of the first band clock control CMOS inverter 206
The pole positive phase signals CLKpos of connection clock.
Second cmos transmission gate 207, its input connects the output end of the 4th CMOS inverter 205；Described second
The grid of the PMOS in parallel of cmos transmission gate 207 connects the clock inversion signal CLKneg, the grid connection institute of NMOS tube
State the positive phase signals CLKpos of clock.
Second latch, including the 5th CMOS inverter 208 and the second band clock control CMOS inverter 209, described the
Two is identical with the structure of the first band clock control CMOS inverter 206 with clock control CMOS inverter 209；Described 5th
The input of CMOS inverter 208 connects the described second output end with clock control CMOS inverter 209 and connects described the
The output end and the output end signal of two cmos transmission gates 207 are signal S0, and the output end of the 5th CMOS inverter 208 connects
Connect the described second input with clock control CMOS inverter 209；Described second institute with clock control CMOS inverter 209
The the second PMOS MP2 grid connection positive phase signals CLKpos of clock is stated, described second with clock control CMOS inverter 209
The grid connection clock inversion signal CLKneg of second NMOS tube.
Hex inverter 210, the output end and the output end signal that its input connects the 5th phase inverter 208 is letter
Number S1, the output end of the hex inverter 210 exports the data output signal Q.
Only include a master-slave register element circuit in the cellular construction of available data trigger device as described above
103, and this master-slave register element circuit 103 also needs to that, with a unification clock phase generation circuit 102, larger face can be taken
Product.
Data trigger device of the embodiment of the present invention is integrated in digital integrated circuit chip, be done in prior art into
What the improvement of one step was formed, further improvement mainly has been done to the cellular construction of data trigger device, as shown in fig. 7,
It is the cellular construction i.e. block diagram of first module structure 1 of data trigger device of the embodiment of the present invention；Data of the embodiment of the present invention
The first module structure 1 of trigger device includes：
The master-slave register element circuit of more than two and a shared clock phase generation circuit 102.In Fig. 7 exemplified with
The first module structure 1 includes two master-slave register element circuits and marked respectively with 103a and 103b.
Everybody the master-slave register element circuit 103a is identical with 103b structure and processing a data respectively defeated
Enter and export.
The clock phase generation circuit 102 simultaneously provide clock positive phase signals CLKpos and clock inversion signal CLKneg to
Each master-slave register the element circuit 103a and 103b, everybody master-slave register the element circuit 103a and 103b data
Output signal Q switches to data input signal D in the positive phase signals CLKpos of clock rising edge and latched.
The digital integration is reduced by sharing the clock phase generation circuit 102 in the first module structure 1
The total quantity of included clock phase generation circuit 102 in circuit chip, thus save chip area, reduction chip power-consumption and
Reduce the clock offset between every data.
Everybody master-slave register the element circuit 103a and 103b in the embodiment of the present invention are respectively adopted such as Fig. 3 institutes
The structure of the master-slave register element circuit 103 shown, the master-slave register element circuit 103 includes：
3rd CMOS inverter 203, its input connects the data input signal D.
First cmos transmission gate 204, its input connects the output end and the output end of the 3rd CMOS inverter 203
Signal be signal D inversion signal DB.The grid of first cmos transmission gate 204 PMOS in parallel connects the clock
Positive phase signals CLKpos, the grid of NMOS tube connect the clock inversion signal CLKneg.
First latch, including the 4th CMOS inverter 205 and first band clock control CMOS inverter 206；Described
The input of four CMOS inverters 205 connects the output end of the first band clock control CMOS inverter 206 and connection is described
The output end of first cmos transmission gate 204 and the signal of the output end are signal M0, the output of the 4th CMOS inverter 205
The input and the input end signal that end connects the first band clock control CMOS inverter 206 are signal M1.
As shown in figure 4, being the circuit diagram of CMOS inverter；Namely in the CMOS inverter 201 and 202 and Fig. 3 in Fig. 2
CMOS inverter 203,205,208 and 210 all using the circuit structure of the CMOS inverter shown in Fig. 4, show CMOS in Fig. 4
Phase inverter includes the PMOS MP101 and NMOS tube MN101 of series connection.
As shown in figure 5, being cmos transmission gate 204 and 207 in the circuit diagram of cmos transmission gate, Fig. 3 all using shown in Fig. 5
Cmos transmission gate circuit structure, show that cmos transmission gate includes PMOS MP102 and NMOS tube MN102 in parallel in Fig. 5.
As shown in fig. 6, being the circuit diagram with clock control CMOS inverter；Band clock control CMOS inverter in Fig. 3
206 and 209 all using the circuit structure of the cmos transmission gate shown in Fig. 6, includes the of series connection with clock control CMOS inverter
One PMOS MP1, the second PMOS MP2, the second NMOS tube MN2MN1 and the second NMOS tube, the source of the first PMOS MP1
Pole connects supply voltage, drain electrode connection the second PMOS MP2 of the first PMOS MP1 source electrode, described second
NMOS tube MN2MN1 source ground, the source electrode of drain electrode connection second NMOS tube of the second NMOS tube MN2MN1, institute
State drain electrode connection the second PMOS MP2 of the second NMOS tube drain electrode and as the output with clock control CMOS inverter
End, the grid of the first PMOS MP1 connects the grid of the second NMOS tube MN2MN1 and as band clock control CMOS
The input of phase inverter, the grid of the second PMOS MP2 and the grid of second NMOS tube are used to connect a pair each other
Anti-phase clock signal.
Return to as shown in figure 3, the second PMOS MP2 of the first band clock control CMOS inverter 206 grid
Pole connects clock inversion signal CLKneg, the grid of second NMOS tube of the first band clock control CMOS inverter 206
The pole positive phase signals CLKpos of connection clock.
Second cmos transmission gate 207, its input connects the output end of the 4th CMOS inverter 205；Described second
The grid of the PMOS in parallel of cmos transmission gate 207 connects the clock inversion signal CLKneg, the grid connection institute of NMOS tube
State the positive phase signals CLKpos of clock.
Second latch, including the 5th CMOS inverter 208 and the second band clock control CMOS inverter 209, described the
Two is identical with the structure of the first band clock control CMOS inverter 206 with clock control CMOS inverter 209；Described 5th
The input of CMOS inverter 208 connects the described second output end with clock control CMOS inverter 209 and connects described the
The output end and the output end signal of two cmos transmission gates 207 are signal S0, and the output end of the 5th CMOS inverter 208 connects
Connect the described second input with clock control CMOS inverter 209；Described second institute with clock control CMOS inverter 209
The the second PMOS MP2 grid connection positive phase signals CLKpos of clock is stated, described second with clock control CMOS inverter 209
The grid connection clock inversion signal CLKneg of second NMOS tube.
Hex inverter 210, the output end and the output end signal that its input connects the 5th phase inverter 208 is letter
Number S1, the output end of the hex inverter 210 exports the data output signal Q.
Compare and understood shown in Fig. 7 and Fig. 1, multidigit master-slave register is employed in the second unit structure 1 of the embodiment of the present invention
The structure of device element circuit and the shared clock phase generation circuit 102 of every master-slave register element circuit, when whole numeral
When the digit of processing data required for integrated circuit is identical, it is clear that the embodiment of the present invention can reduce clock phase generation circuit 102
Usage quantity, so as to reduce the area shared by clock phase generation circuit, also so as to reducing data trigger in numeral
Area accounting in integrated circuit, and and then reduce the area of whole digital integrated electronic circuit, improve the integrated of digital integrated electronic circuit
Degree.
Further, since the embodiment of the present invention can reduce the quantity of the clock phase generation circuit in digital integrated electronic circuit, therefore energy
Enough power consumptions reduced produced by being overturn due to clock phase generation circuit, therefore chip power-consumption can be reduced.As shown in Figure 2 and Figure 4, often save
About clock phase generation circuit 102, then can save the area of 4 transistors, at the same can also save corresponding quiescent dissipation and
The dynamic power consumption of clock upset.
In addition, data bit different in the cellular construction of data trigger device of the embodiment of the present invention shares a clock phase
Generation circuit so that the distributed point of Clock Tree is reduced, and advantageously reduces the offset between clock phase so that sequential easily restrains.
As shown in figure 8, being structural representation when data bit transmission process is realized using two existing second unit structures；Such as Fig. 9 institutes
Show, be structural representation when data bit transmission process is realized using first module structure of the embodiment of the present invention.In Fig. 8, each
Pass through logic communication network (Logic between two cellular construction 101a and 101b output signal and input signal
Propagation) 301 transmitting signal, second unit structure 101a and 101b here are using the second unit shown in Fig. 1
Structure 101；In order to drive clock signal, and balanced between each clock signal, reduce offset, typically can also be each second
Clock buffer 302 is inserted between cellular construction 101a and 101b clock signal, such result also may proceed to increase clock
Area and power consumption on path.In Fig. 9, passed between the output signal and input signal of same first module structure 1 by logic
The transmitting signal of network 302 is broadcast, but the clock signal between the two bits of same first module structure 1 is identical, is not deposited
Buffer insertion 302, further reduce the area and power consumption on clock path in fig. 8.Simultaneously as sharing a clock
Phase generation circuit, eliminates the clock offset that local data position is seen, on the whole the sequential of data transfer path is easily received
Hold back.
The present invention is described in detail above by specific embodiment, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (3)
1. a kind of data trigger device, it is characterised in that：It is integrated in digital integrated circuit chip and data trigger device
Including first module structure, the first module structure includes：
The master-slave register element circuit of more than two and a shared clock phase generation circuit；
The structure of everybody the master-slave register element circuit is identical and handles the input and output of a data respectively；
The clock phase generation circuit provides the positive phase signals of clock and clock inversion signal to each master-slave register list simultaneously
First circuit, the data output signal of everybody the master-slave register element circuit switches in the rising edge of the positive phase signals of the clock
For data input signal and latch；
The digital integrated circuit chip is reduced by sharing the clock phase generation circuit in the first module structure
In included clock phase generation circuit total quantity, so as to save chip area, reduction chip power-consumption and reduce each digit
Clock offset between.
2. data trigger device as claimed in claim 1, it is characterised in that：The clock phase generation circuit includes first
CMOS inverter and the second CMOS inverter, the input connection clock input signal of first CMOS inverter, described the
The output end of one CMOS inverter connects the input of second CMOS inverter and exports the clock inversion signal, described
The output end of second CMOS inverter exports the positive phase signals of clock.
3. data trigger device as claimed in claim 1, it is characterised in that：Everybody master-slave register element circuit bag
Include：
3rd CMOS inverter, its input connects the data input signal；
First cmos transmission gate, its input connects the output end of the 3rd CMOS inverter；First cmos transmission gate
The grid of PMOS in parallel connects the positive phase signals of clock, the grid of NMOS tube connects the clock inversion signal；
First latch, including the 4th CMOS inverter and first band clock control CMOS inverter；4th CMOS is anti-phase
The input of device connects the output end of the first band clock control CMOS inverter and connects first cmos transmission gate
Output end, the output end of the 4th CMOS inverter connects the input of the first band clock control CMOS inverter；Band
Clock control CMOS inverter includes the first PMOS, the second PMOS, the first NMOS tube and the second NMOS tube of series connection, described
The source electrode connection supply voltage of first PMOS, the source electrode of drain electrode connection second PMOS of first PMOS, institute
State the source ground of the first NMOS tube, the source electrode of drain electrode connection second NMOS tube of first NMOS tube, described second
The drain electrode of drain electrode connection second PMOS of NMOS tube and as the output end with clock control CMOS inverter, described the
The grid of one PMOS connects the grid of first NMOS tube and as the input with clock control CMOS inverter, described
The grid of second PMOS and the grid of second NMOS tube are used to connect a pair of clock signals anti-phase each other；Described first
The grid connection clock inversion signal of second PMOS with clock control CMOS inverter, the first band clock control
The grid connection positive phase signals of clock of second NMOS tube of CMOS inverter；
Second cmos transmission gate, its input connects the output end of the 4th CMOS inverter；Second cmos transmission gate
The grid of PMOS in parallel connects the clock inversion signal, the grid of NMOS tube connects the positive phase signals of clock；
Second latch, including the 5th CMOS inverter and the second band clock control CMOS inverter, clock during second band
CMOS inverter processed is identical with the structure of the first band clock control CMOS inverter；The input of 5th CMOS inverter
The output end of end the described second output end with clock control CMOS inverter of connection and connection second cmos transmission gate, institute
The output end for stating the 5th CMOS inverter connects the described second input with clock control CMOS inverter；During second band
The grid connection positive phase signals of clock of second PMOS of clock CMOS inverter, the second band clock control CMOS
The grid connection clock inversion signal of second NMOS tube of phase inverter；
Hex inverter, its input connects the output end of the 5th phase inverter, the output end output of the hex inverter
The data output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710455286.6A CN107317569A (en) | 2017-06-16 | 2017-06-16 | Data trigger device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710455286.6A CN107317569A (en) | 2017-06-16 | 2017-06-16 | Data trigger device |
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| CN107317569A true CN107317569A (en) | 2017-11-03 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1846351A (en) * | 2003-09-03 | 2006-10-11 | 皇家飞利浦电子股份有限公司 | A static latch |
| CN101534109A (en) * | 2009-03-30 | 2009-09-16 | 浙江大学 | Orthogonal signal frequency-multiplication phase-demodulation logic circuit with filter function |
| CN103269213A (en) * | 2013-04-11 | 2013-08-28 | 南京互信系统工程有限公司 | Clockless buffer trigger |
| CN105191127A (en) * | 2013-05-08 | 2015-12-23 | 高通股份有限公司 | Flip-flop for reducing dynamic power |
| JP2017055332A (en) * | 2015-09-11 | 2017-03-16 | 株式会社東芝 | Semiconductor integrated circuit |
-
2017
- 2017-06-16 CN CN201710455286.6A patent/CN107317569A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1846351A (en) * | 2003-09-03 | 2006-10-11 | 皇家飞利浦电子股份有限公司 | A static latch |
| CN101534109A (en) * | 2009-03-30 | 2009-09-16 | 浙江大学 | Orthogonal signal frequency-multiplication phase-demodulation logic circuit with filter function |
| CN103269213A (en) * | 2013-04-11 | 2013-08-28 | 南京互信系统工程有限公司 | Clockless buffer trigger |
| CN105191127A (en) * | 2013-05-08 | 2015-12-23 | 高通股份有限公司 | Flip-flop for reducing dynamic power |
| JP2017055332A (en) * | 2015-09-11 | 2017-03-16 | 株式会社東芝 | Semiconductor integrated circuit |
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