CN107316858A - High dielectric film layer structure and its application and preparation method - Google Patents

Abstract

The invention provides a high dielectric film layer structure and its application and preparation method. The structure includes: a laminated dielectric structure, including at least one first dielectric layer and at least one second dielectric layer, and the second dielectric layer The forbidden band width is greater than the forbidden band width of the first dielectric layer, the thickness of the single-layer second dielectric layer is less than or equal to the thickness of the single-layer first dielectric layer, and the quantum tunneling suppression layer is arranged on the stacked dielectric layer On the surface of the structure, or between the first dielectric layer and the second dielectric layer of the stacked dielectric structure, the dielectric constant of the quantum tunneling suppression layer is greater than the dielectric constant of the first dielectric layer and greater than the dielectric constant of the second dielectric layer. The dielectric constant of the second dielectric layer. Through the scheme of the present invention, the high dielectric film layer structure can reduce the thickness of the equivalent oxide layer under the condition that the thickness of the capacitor dielectric layer remains unchanged, and can also maintain or reduce the thickness of the equivalent oxide layer while having sufficient physical The thickness is used to limit the influence of quantum tunneling effect and prevent the increase of leakage current which will lead to device failure.

Description

High dielectric film structure and its application and preparation method

technical field

The invention belongs to the technical field of semiconductor device manufacturing, and in particular relates to a high-dielectric film layer structure and a preparation method thereof, and a capacitor structure containing the high-dielectric film layer structure and a preparation method thereof.

Background technique

A capacitor is a passive electronic component that stores energy in the form of an electrostatic field. In its simplest form, a capacitor consists of two conducting plates separated by an insulating material called a dielectric. The capacitance of a capacitor is proportional to the surface area of the plates and inversely proportional to the distance between the plates. The capacitance of a capacitor also depends on the dielectric constant of the substance separating the plates. The standard unit of capacitance is farad (abbreviated as F), which is a large unit, and the more common units are microfarad (abbreviated as μF) and picofarad (picofarac, abbreviated as PF), where 1μF=10 ^-6 F, 1pF= ^10-12F .

Capacitors can be fabricated on integrated circuit (IC) chips. In dynamic random access memory (DRAM for short), capacitors are usually used to connect with transistors. Capacitors help maintain the contents of memory. Due to their tiny physical size, these components have low capacitance. They must be recharged thousands of times per second, otherwise, the DRAM will lose data. The basic structure of a capacitor is a sandwich structure, including a lower plate, a high-K dielectric, and an upper plate. For DRAM capacitors, the high-K dielectric is a key factor.

At present, as the feature size of semiconductor devices such as dynamic random access memory (DRAM) shrinks continuously, the thickness of the oxide layer is close to the limit of the quantum tunneling effect (Quantum tunneling effect), causing the leakage current to decrease with the oxide thickness. Exponential growth. The high dielectric constant oxide can maintain sufficient driving current, and can increase the actual physical thickness of the oxide layer while maintaining the same equivalent oxide thickness (EOT), effectively suppressing the quantum tunneling effect. In the prior art, some materials have a higher dielectric constant, but their forbidden band width is narrow, which has the disadvantage of high leakage. In order to solve the problem of leakage, the thickness of the capacitor dielectric layer must be increased. In this way, it will Sacrifice the capacitance value of the part; other materials have a lower dielectric constant and a wider band gap, which has the advantage of low leakage, but too many material layers will lead to a decrease in the effective dielectric constant, thus limiting its charge storage capacity.

Therefore, how to design the film structure of high-K dielectric and its capacitor so that the feature size of the device can continue to be reduced under the condition of maintaining the driving current and prevent the increase of leakage current has become an important technical problem to be solved urgently by those skilled in the art. .

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a high dielectric film layer structure and its application and preparation method, which are used to solve the problems of small charge storage and high leakage current in the prior art.

In order to achieve the above purpose and other related purposes, the present invention provides a high dielectric film structure, including:

A laminated dielectric structure, comprising at least one first dielectric layer and at least one second dielectric layer, the forbidden band width of the second dielectric layer is greater than the forbidden band width of the first dielectric layer, And the thickness of the single layer of the second dielectric layer is less than or equal to the thickness of the single layer of the first dielectric layer; and

The quantum tunneling suppression layer is disposed on the surface of the stacked dielectric structure, or between the first dielectric layer and the second dielectric layer of the stacked dielectric structure, so The dielectric constant of the quantum tunneling suppression layer is greater than that of the first dielectric layer and greater than that of the second dielectric layer.

As a preferred solution of the present invention, the quantum tunneling suppression layer is a titanium dioxide layer.

As a preferred solution of the present invention, the first dielectric layer is a zirconium dioxide layer, and the second dielectric layer is an aluminum oxide layer.

As a preferred solution of the present invention, the laminated dielectric structure is selected from the laminated structure in which zirconium dioxide and aluminum oxide are stacked in sequence, zirconium dioxide, aluminum oxide and zirconium dioxide in sequence One of the stacked laminated structures and the stacked laminated structures of aluminum oxide, zirconium dioxide, and aluminum oxide in sequence.

As a preferred solution of the present invention, the first dielectric layer has a dielectric constant greater than or equal to 10, and the second dielectric layer has a forbidden band width greater than or equal to 8.

As a preferred solution of the present invention, the stacked dielectric structure is doped with at least one of silicon nitride and silicon oxynitride.

As a preferred solution of the present invention, the thickness of the high dielectric film layer structure is 4-10 nm.

As a preferred solution of the present invention, the high dielectric film layer structure further includes a leakage barrier layer, and the number of the stacked dielectric structures is at least two, wherein the leakage barrier layer is located in the laminated layer between dielectric structures.

As a preferred solution of the present invention, the material of the leakage barrier layer includes silicon dioxide, and the thickness of the leakage barrier layer is smaller than the thickness of a single layer of the second dielectric layer in the stacked dielectric structure. .

The present invention also provides a capacitor structure, comprising:

The lower plate is connected with the lower electrode;

an upper plate connected to an upper electrode; and

The high dielectric film layer structure according to any one of the solutions above is located between the upper plate and the lower plate.

As a preferred solution of the present invention, the quantum tunneling suppression layer is located between the stacked dielectric structure and the lower plate.

As a preferred solution of the present invention, the number of the stacked dielectric structures is four, which are composed of stacked dielectric structures of zirconium dioxide and aluminum oxide in sequence, and the four stacked dielectric structures The layered dielectric structure is stacked sequentially from bottom to top; the quantity of the quantum tunneling suppression layer is 2 layers, which are respectively arranged between the lower electrode plate and the bottom layer of zirconium dioxide, and the top layer of zirconium dioxide between the aluminum layer and the upper plate.

As a preferred solution of the present invention, at least one section of the lower plate is U-shaped, and the corresponding sections of the high dielectric film structure and the upper plate are both M-shaped, forming a double-sided capacitor structure.

The present invention also provides a method for preparing a high dielectric film structure, the high dielectric film structure is a structure composed of N layers, wherein N is an integer greater than or equal to 3, and the preparation method includes:

forming at least one stacked dielectric structure, and the stacked dielectric structure includes at least one first dielectric layer and at least one second dielectric layer, and the forbidden band width of the second dielectric layer is greater than the forbidden band width of the first dielectric layer, and the unit thickness of the second dielectric layer is less than or equal to the unit thickness of the first dielectric layer; and

forming at least one quantum tunneling suppression layer, and it is formed on the surface of the stacked dielectric structure, or formed on the first dielectric layer and the second dielectric layer of the stacked dielectric structure between dielectric layers, and the dielectric constant of the quantum tunneling suppression layer is greater than the dielectric constant of the first dielectric layer and greater than the dielectric constant of the second dielectric layer.

As a preferred solution of the present invention, the quantum tunneling suppression layer is a titanium dioxide layer, the first dielectric layer is a zirconium dioxide layer, and the second dielectric layer is an aluminum oxide layer.

As a preferred solution of the present invention, the process of forming the high dielectric film structure composed of N film layers includes the steps of forming the second film layer to the Nth film layer, and the specific steps include:

Forming a layer of hydroxide ion layer on the upper surface of the provided first film layer, and reacting the simple substance corresponding to the oxide contained in the hydroxide ion layer and the second layer film layer, to forming said second film layer; and

Forming a layer of hydroxide ion layer on the upper surface of the formed N-1th film layer, and making the hydroxide ion layer react with the elemental substance corresponding to the oxide contained in the N-th film layer, so as to Form the Nth film layer.

As a preferred version of the present invention, in the process of forming the second film layer and the Nth film layer, its process gas is selected from zirconium (Zr), silicon (Si), aluminum (Al), niobium ( At least one of the group consisting of Nb), hafnium (Hf) and titanium (Ti), the process pressure is 0.1-2 Torr, and the process temperature is 200-400°C.

As a preferred solution of the present invention, it is characterized in that the method for forming the hydroxide ion layer comprises: in the reaction furnace, the gas is fed into one of water vapor and ozone, and heated The structure to be formed with a hydroxide ion layer is processed to form a layer of hydroxide ions on the upper surface of the structure to be formed with a hydroxide ion layer.

The present invention also provides a method for preparing a capacitor structure, comprising the steps of:

1) Provide the following plates;

2) forming a layer of hydroxide ion layer on the upper surface of the lower plate, allowing the hydroxide ion layer to react with the elemental substance corresponding to the oxide contained in the first layer of the film layer to form the first layer of film Floor;

3) Prepare the second layer to the Nth film layer on the surface of the first film layer according to the method described in any of the above-mentioned schemes, so as to form a high dielectric film layer structure composed of N film layers, wherein, N is an integer greater than or equal to 3; and

4) Forming an upper pole plate on the surface of the structure obtained in step 3).

As mentioned above, the high dielectric film structure of the present invention and its application and preparation method have the following beneficial effects:

1) The high dielectric film layer structure of the present invention can reduce the thickness of the equivalent oxide layer under the condition that the thickness of the capacitor dielectric layer is constant;

2) The high dielectric film structure of the present invention can maintain or reduce the equivalent oxide layer thickness while having sufficient physical thickness to limit the influence of quantum tunneling effect and prevent device failure from increasing leakage current.

Description of drawings

FIG. 1 to FIG. 5 show schematic diagrams of the structure of the high dielectric film layer provided for the first embodiment of the present invention.

6 to 8 are schematic diagrams of a stacked dielectric structure provided in Embodiment 1 of the present invention.

FIG. 9 to FIG. 11 are schematic diagrams showing the structure of the high dielectric film layer provided with the leakage protection layer according to Embodiment 1 of the present invention.

FIG. 12 to FIG. 16 show the structural schematic diagrams of each step in the process of preparing the capacitor structure provided by Embodiment 2 of the present invention.

FIG. 17 to FIG. 18 show schematic diagrams of other two capacitor structures provided for Embodiment 2 of the present invention.

Figure 19 shows a comparative graph of the dielectric constant of each material.

FIG. 20 is a schematic diagram showing the relationship between the dielectric constant of each material and the forbidden band width.

Component designation description

1 High dielectric film structure

11 Stacked Dielectric Structure

111 first dielectric layer

112 second dielectric layer

12 Quantum tunneling suppression layer

13 Leakage barrier layer

2 capacitor structure

21 lower plate

22 upper plate

23 Bottom electrode

24 upper electrode

25 insulation layer

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 20. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the shape, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the layout of the components may also be more complicated.

Embodiment one

The present invention provides a high dielectric film structure, as shown in Figures 1 to 5, the high dielectric film structure 1 includes:

A stacked dielectric structure 11, the stacked dielectric structure includes at least one first dielectric layer 111 and at least one second dielectric layer 112, the forbidden band width of the second dielectric layer 112 is greater than The forbidden band width of the first dielectric layer 111, and the thickness of the single layer of the second dielectric layer 112 is less than or equal to the thickness of the single layer of the first dielectric layer 111; and

Quantum tunneling suppression layer 12, disposed on the surface of the stacked dielectric structure 11, or located on the first dielectric layer 111 and the second dielectric layer of the stacked dielectric structure 11 112 , the dielectric constant of the quantum tunneling suppression layer 12 is greater than the dielectric constant of the first dielectric layer 111 and greater than the dielectric constant of the second dielectric layer 112 .

Specifically, in the present invention, K represents a dielectric constant, and a high K represents a dielectric constant greater than 3.9. In addition, taking the stacked dielectric structure 11 consisting of only one layer of first dielectric layer 111 and one layer of second dielectric layer 112 as an example, the quantum tunneling suppression layer 12 may be located in the stacked The lower surface or the upper surface of the dielectric structure 11. At this time, the quantum tunneling suppression layer 12 is only in contact with one layer of the stacked dielectric structure 11, that is, the quantum tunneling suppression layer and the first A dielectric layer 111 or a second dielectric layer 112 are in contact, as shown in FIG. 1 and FIG. In other words, the quantum tunneling suppression layer 12 can be in contact with the first dielectric layer 111 and the second dielectric layer 112 at the same time, as shown in FIG. 3 , it is the case of being in contact with both types of film layers.

Furthermore, when the number of the stacked dielectric structures 11 is two or more, the quantum tunneling suppression layer 12 may be located between each of the stacked dielectric structures 11, of course, it may also be Located on the upper surface or the lower surface of the stacked structure formed by two or more stacked dielectric structures 11, as shown in FIG. A schematic diagram of the structure of the quantum tunneling suppression layer 12 located on its lower surface.

At the same time, the quantity of the quantum tunneling suppression layer 12 can also be two or more layers, as shown in FIG. Dielectric film layer structure, which consists of a stacked dielectric structure 11 and a layer of quantum tunneling suppression layer 12 located on the lower surface of the stacked dielectric structure 11 to form a loop structure, two or more loops The structures are stacked in sequence to form the high dielectric film layer structure.

It should be noted that, in other embodiments of the present invention, in order to reduce the thickness of the equivalent oxide layer more effectively, and maintain or reduce the thickness of the equivalent oxide layer while having sufficient physical thickness to limit the quantum tunneling effect influence, to prevent the leakage current from increasing and causing device failure, the number of the stacked dielectric structures 11 can be set according to actual needs, such as 3 to 100, in this embodiment, preferably 4, the quantum The number of tunneling inhibiting layers 12 can also be any number of layers. In this embodiment, it is preferably 2 layers. Of course, it can also be 3-100 layers, which is not specifically limited here.

As an example, the quantum tunneling suppression layer 12 is a titanium dioxide layer.

Of course, in other embodiments, the quantum tunneling suppression layer 12 can also be at least one of a hafnium dioxide (HfO ₂ ) layer and a niobium dioxide (NbO ₂ ) layer, and the quantum tunneling suppression layer 12 Because of its high dielectric constant, on the one hand, it can provide sufficient capacitance capacity for the capacitor structure, on the other hand, it can also reduce the thickness of the equivalent oxide layer, thereby reducing device leakage while adapting to the reduction of device feature size.

As an example, the first dielectric layer 111 is a zirconium dioxide layer (ZrO ₂ ), and the second dielectric layer 112 is an aluminum oxide layer (Al ₂ O ₃ ).

As an example, the stacked dielectric structure 11 is selected from a stacked structure in which zirconium dioxide and aluminum oxide are stacked in sequence, as shown in FIG. 6, which is a ZA structure; zirconium dioxide and aluminum oxide The stacked structure stacked with zirconium dioxide in sequence, as shown in Figure 7, is a ZAZ structure; the stacked structure with aluminum oxide, zirconium dioxide, and aluminum oxide stacked in sequence, as shown in Figure 8 It is any one of the AZA structure, of course, in other embodiments, it can also be selected from the combination of any two or more of the above structures, wherein, "any two or more" refers to any two A combination of species or any combination of two or more.

As an example, the first dielectric layer has a dielectric constant greater than or equal to 10, and the second dielectric layer has a band gap greater than or equal to 8.

Specifically, the quantum tunneling suppression layer 12 includes but is not limited to a titanium dioxide (TiO ₂ ) layer, a hafnium dioxide (HfO ₂ ) layer, and a niobium dioxide (NbO ₂ ) layer, which can be used to realize the quantum tunneling suppression layer 12 Functional arbitrary quantum tunneling suppression layer in the present invention. Wherein, when the laminated dielectric structure 11 is selected from the zirconia/aluminum oxide structure, the quantum tunneling suppression layer 12 can be located only on the surface of the zirconia layer, or only on the aluminum oxide layer surface, or between the zirconium dioxide layer and the aluminum oxide layer; when the laminated dielectric structure 11 is selected from the zirconium dioxide/aluminum oxide/zirconium dioxide structure, the quantum tunneling suppression Layer 12 can be located only on the surface of the zirconium dioxide layer, that is, the upper surface or the lower surface; it can also be located between the zirconium dioxide layer and the aluminum oxide layer. Between the interfaces, the quantum tunneling suppression layer 12 may also be provided between all the zirconia/aluminum oxide interfaces. Other examples are similar, and will not be listed here.

In addition, the first dielectric layer has a dielectric constant greater than or equal to 10, the second dielectric layer has a band gap greater than or equal to 8, and the thickness of a single layer of the second dielectric layer is less than or equal to a single layer The thickness of the first dielectric layer, in this embodiment, compared with ZrO2, Al ₂ O ₃ has a lower dielectric constant and a wider forbidden band, which has the advantage of low leakage, but too much _{Al 2} O ₃ will lead to a decrease in the effective dielectric constant, thereby limiting its charge storage capacity. ZrO ₂ has a high dielectric constant, but its forbidden band width is narrow, and it has the disadvantage of high leakage. In order to solve the leakage problem, the capacitor dielectric The thickness of the layer must be increased. In this way, part of the capacitance value will be sacrificed instead. Based on the above-mentioned characteristics of the two, the first dielectric layer 111 and the second dielectric layer 112 in this embodiment are set. It has obvious advantages in leakage current and stability.

As an example, the stacked dielectric structure 11 is doped with at least one of silicon nitride and silicon oxynitride.

Specifically, the stacked dielectric structure 11 is further doped with at least one of silicon nitride (SiN) and silicon oxynitride (SiON). Wherein, the doped silicon nitride or silicon oxynitride only occupies part of the vacancies in the zirconium dioxide layer or the aluminum oxide layer, and does not constitute a complete film. In the present invention, the laminated dielectric structure 11 The doping of silicon nitride or silicon oxynitride can further reduce leakage in the high-K dielectric circulation unit.

As an example, the thickness of the high dielectric film layer structure 1 is 4-10 nm.

Specifically, the thickness of the high dielectric film layer structure 1 is preferably 6-9 nm, and in this embodiment, it is selected as 8 nm. In addition, the thickness of the first dielectric layer 111 may be 1.5-10 nm. In this embodiment The choice is 4nm; the thickness of the second dielectric layer 112 can be 0.1-5nm, which is 2nm in this embodiment; the thickness of the quantum tunneling suppression layer 12 can be 0.1-8nm, preferably 0.2-5nm, In this embodiment, it is selected as 2nm, which depends on the actual demand for capacitance capacity, and no specific limitation is made here. The quantum tunneling suppression layer 12 is intended to provide a capacitor structure with a high dielectric constant because of its high dielectric constant. Sufficient capacitance capacity, on the other hand, can also reduce the thickness of the equivalent oxide layer, thereby reducing device leakage while adapting to the reduction of device feature size.

As an example, the high dielectric film structure 1 further includes a leakage barrier layer 13, and the number of the stacked dielectric structures 11 is at least two, wherein the leakage barrier layer 13 is located in the stacked dielectric structure Between electrical structures 11.

As an example, the material of the leakage blocking layer 13 includes silicon dioxide, and the thickness of the leakage blocking layer 13 is smaller than the thickness of a single layer of the second dielectric layer 112 in the stacked dielectric structure 11 .

Specifically, the leakage current blocking layer 13 can be a continuous or discontinuous atomic layer, preferably a thermally diffused discontinuous atomic layer. The material of the leakage current blocking layer 13 includes but is not limited to silicon oxide, which has The higher forbidden band width can effectively prevent leakage, and the thickness range of the leakage current blocking layer is 0.5-2.5nm. As shown in FIGS. 9-11, the leakage blocking layer 13 is located between the stacked dielectric structures 11, including the situation when there is no quantum tunneling suppression layer 12 between the stacked dielectric structures 11. , as shown in FIG. 9, also includes the case where a layer of quantum tunneling suppression layer 12 is formed between the stacked dielectric structures 11. At this time, the leakage blocking layer 13 is located between the stacked dielectric structures Between the electrical structures 11 and further between the quantum tunneling suppression layer 12 and the stacked dielectric structure 11 above it, or between the quantum tunneling suppression layer 12 and the stacked dielectric structure below it Between the electrical structures 11, of course, in other embodiments, there are many solutions that can realize this function, which are not specifically limited here.

The present invention also provides a method for preparing a high dielectric film structure, wherein the preparation method is a method for preparing the high dielectric film structure protected by the present invention, specifically, the high dielectric film structure is composed of N layers A structure composed of film layers, wherein N is an integer greater than or equal to 3, and the preparation method includes:

At least one stacked dielectric structure 11 is formed, and the stacked dielectric structure 11 includes at least one first dielectric layer 111 and at least one second dielectric layer 112, the second dielectric layer 112 The forbidden band width is greater than the forbidden band width of the first dielectric layer 111, and the unit thickness of the second dielectric layer 112 is less than or equal to the unit thickness of the first dielectric layer 111; and

forming at least one quantum tunneling suppression layer 12, and it is formed on the surface of the stacked dielectric structure 11, or formed on the first dielectric layer 111 and the stacked dielectric structure 11 Between the second dielectric layer 112, and the dielectric constant of the quantum tunneling suppression layer 12 is greater than the dielectric constant of the first dielectric layer 111 and greater than the dielectric constant of the second dielectric layer 112 constant.

Specifically, the high dielectric film layer structure 1 is formed by low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) (not limited to single-chip or batch reaction chambers).

As an example, the quantum tunneling suppression layer 12 is a titanium dioxide layer, the first dielectric layer 111 is a zirconium dioxide layer, and the second dielectric layer 112 is an aluminum oxide layer.

As an example, the process of forming the high dielectric film structure composed of N film layers includes the steps of forming the second film layer to the Nth film layer, and the specific steps include:

Form a layer of hydroxide ion layer on the upper surface of the provided first layer of film layer, and make the hydroxide ion layer react with the simple substance corresponding to the oxide contained in the second layer of film layer to form the first layer of film layer two layers of film; and

Forming a layer of hydroxide ion layer on the upper surface of the formed N-1th film layer, and making the hydroxide ion layer react with the elemental substance corresponding to the oxide contained in the N-th film layer, so as to Form the Nth film layer.

Specifically, in this embodiment, the first film layer may be provided directly, and may be an aluminum oxide layer, a zirconium dioxide layer, or a quantum tunneling suppression layer, such as a TiO ₂ layer.

As an example, in the process of forming the second film layer and the Nth film layer, the process gas is at least one of Zr, Si, Al, Nb, Hf or Ti, and the process pressure is 0.1-2 Torr ( torr), preferably 0.1 to 1 torr, 0.5 torr is selected in this embodiment, and the process temperature is 200 to 400° C., preferably 250 to 350° C., and 300° C. is selected in this embodiment.

As an example, the method for forming the hydroxide ion layer includes: in a reaction furnace, the structure to be formed with the hydroxide ion layer is treated by feeding H ₂ O or O ₃ and heating, so as to form the hydroxide ion layer in the reactor. A hydroxide ion layer is formed on the upper surface of the structure where the hydroxide ion layer is to be formed.

Specifically, the structure to be formed with a hydroxide ion layer is placed in a reaction furnace (such as a furnace tube), and H ₂ O or O ₃ is introduced into the reaction furnace to heat the reaction furnace, so that the structure to be treated A layer of hydroxide ion layer is formed on the surface, and then, the simple substance corresponding to the oxide contained in the film layer to be formed is passed through to react with the hydroxide ion layer as a precursor to form the required oxide film layer.

Embodiment two

The present invention also provides a capacitor structure, which includes the high dielectric film layer structure 1 described in Embodiment 1, as shown in Figures 16-18, including:

The lower plate 21 is connected with the lower electrode 23;

The upper plate 22 is connected with the upper electrode 24;

The high-dielectric film structure 1 is located between the upper plate 22 and the lower plate 21, wherein the high-dielectric film structure 1 is the high-dielectric film structure described in any one of the solutions above.

It should be noted that the calculation formula of capacitor capacitance is: C=Kε _o A/t _ox (wherein, K: the dielectric constant of the dielectric layer, ε _o : the vacuum dielectric constant, A: the area of the dielectric layer, t _ox : thickness of the dielectric layer), without causing quantum tunneling effect, the capacitance can be increased by reducing the thickness of the dielectric layer or increasing the dielectric constant of the dielectric layer. In addition, the equivalent oxide thickness (EOT) is: when the high dielectric constant dielectric layer keeps the capacitance constant, the thickness of the _SiO2 dielectric layer with the same capacitance per unit area is converted. The specific conversion formula is:

C＝(K _{high k} ε _o A)/(t _{high k} )＝3.9ε _o A/teq;

EOT=teq=(3.9t _{high k} )/(K _{high k} );

Here, under the condition that the thickness of t _{high k} remains unchanged, since the dielectric constant of the high dielectric constant dielectric layer is larger than that of SiO ₂ , its EOT is small, which can make the feature size of the device continue to shrink under the condition of maintaining the driving current , in the present application, the quantum tunneling suppression layer 12 is further adopted, such as the TiO ₂ layer, which has a very high dielectric constant, and the dielectric constant of TiO ₂ is 80, which can also maintain or reduce the equivalent oxide layer at the same time In the case of thickness, sufficient physical thickness can be provided to limit the influence of quantum tunneling effect, prevent leakage current from increasing, and prevent device failure. Specifically, the comparison of parameters such as the dielectric constant value of each material is shown in Figure 19 and Figure 19. 20, where Band Gap(eV) refers to the forbidden band width of the material, and △Ec(eV)toSi refers to the conduction band energy difference between the material and silicon.

As an example, the quantum tunneling suppression layer 12 is located between the stacked dielectric structure 11 and the lower plate 21 .

Of course, in other embodiments, the quantum tunneling suppression layer 12 may be located between the stacked dielectric structure 11 and the upper plate 22, or the quantum tunneling suppression layer 12 may also be located in each Between the stacked dielectric structures 11, may also be located between the first dielectric layers and the second dielectric layers of the stacked dielectric structures 11, of course, may also be located in the above positions at the same time Two or more locations, not specifically limited here.

Specifically, the quantum tunneling suppression layer 12 is located between the laminated dielectric structure 11 and the upper plate or the lower plate, and is in contact with the upper and lower plates, thereby further ensuring that the high dielectric film layer structure is used to obtain more The large charge storage capacity is beneficial to reduce the leakage current, thereby reducing the refresh frequency of the dynamic random access memory and improving the data storage capacity of the dynamic random access memory.

As an example, the number of the stacked dielectric structures 11 is four, which are composed of a stacked dielectric structure in which zirconium dioxide and aluminum oxide are stacked in sequence, and the four stacked dielectric structures 11 are stacked sequentially from bottom to top; the quantum tunneling suppression layer 12 has two layers, wherein the quantum tunneling suppression layer 12 is respectively arranged between the lower plate 21 and the bottom zirconium dioxide layer between, and between the top aluminum oxide layer and the upper plate 22, as shown in FIG. 16 .

As an example, at least one section of the lower plate 21 is U-shaped, and the corresponding sections of the high dielectric film structure and the upper plate 22 are both M-shaped, forming a double-sided capacitor structure, as shown in Figure 18 .

Specifically, the high dielectric film structure 1 is formed on the inner surface and the outer surface of the U-shaped lower plate 21 at the same time, and the upper plate 22 is formed on the outer surface of the high dielectric film structure 1, forming a double-sided Capacitor structure, compared with single-sided capacitor structure, double-sided capacitor structure can achieve higher capacitance value. Of course, in other embodiments, the structure of the capacitor can also be designed according to actual needs, and the protection scope of the present invention should not be excessively limited here.

The present invention also provides a method for preparing a capacitor structure, as shown in Figures 12-17, wherein the preparation method is a method for preparing the capacitor structure protected by the present invention, comprising the following steps:

1) Provide the polar plate 21, as shown in Figure 12;

2) Form a layer of hydroxide ion layer on the surface of 21 on the lower plate, and make the hydroxide ion layer react with the simple substance corresponding to the oxide contained in the first film layer to form the first layer film layer, as shown in Figure 13;

3) Prepare the second layer to the Nth film layer on the surface of the first film layer according to the preparation method of the high dielectric film layer structure described in any one of the above-mentioned embodiments, so as to form an N-layer film A high dielectric film layer structure composed of layers, wherein N is an integer greater than or equal to 3, as shown in Figures 14-17;

4) Form an upper plate 22 on the surface of the structure obtained in step 3), as shown in FIG. 16 and FIG. 17 .

Specifically, the laminated dielectric structure 11 is a zirconium dioxide/alumina laminated structure, the quantum tunneling suppression layer 12 is a _TiO2 layer, and the quantum tunneling suppression layer 12 is located at the Take between the lower plate 21 and each of the laminated dielectric structures and between each of the laminated dielectric structures and the upper plate 22 as examples, and describe in detail the preparation method of the capacitor structure of this embodiment , in the preparation of the capacitor structure, first provide the lower plate 21, and form a layer of hydroxide ion layer on its surface, and then make it react with Ti to generate a TiO ₂ layer, as a layer between the upper and lower plates. The first layer of the high-dielectric film structure, then, according to the preparation method in Example 1, form a layer of hydroxide ion layer on the surface of the _TiO2 layer, and make it react with Zr by chemical adsorption and generate dioxide Zirconium layer, as the second layer of the high dielectric film layer structure, and so on, continue to generate Al2O3/ZrO2/Al2O3 film layers until the preparation of the Nth film layer is completed, and finally, in the The upper plate is deposited on the surface of the high dielectric film structure to complete the preparation of the capacitor structure. Of course, in other embodiments, different high-dielectric film layer structures can also be formed, which is not specifically limited here, and FIG. 17 shows an example thereof.

In summary, the present invention provides a high dielectric film structure and its application and preparation method. The high dielectric film structure includes: a laminated dielectric structure, including at least one first dielectric layer and at least one A second dielectric layer, the forbidden band width of the second dielectric layer is greater than the forbidden band width of the first dielectric layer, and the thickness of the single layer of the second dielectric layer is less than or equal to the thickness of the single layer of the first dielectric layer the thickness of a dielectric layer; and a quantum tunneling suppression layer disposed on a surface of the stacked dielectric structure, or between the first dielectric layer and the stacked dielectric structure Between the second dielectric layers, the dielectric constant of the quantum tunneling suppression layer is larger than the dielectric constant of the first dielectric layer and larger than the dielectric constant of the second dielectric layer. Through the solution of the present invention, the high dielectric film structure of the present invention can reduce the thickness of the equivalent oxide layer under the condition that the thickness of the capacitor dielectric layer remains unchanged, and while maintaining or reducing the thickness of the equivalent oxide layer, sufficient The physical thickness is used to limit the influence of quantum tunneling effect and prevent the increase of leakage current which will lead to device failure. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (19)

1. A high dielectric film structure, characterized in that, comprising: A laminated dielectric structure, comprising at least one first dielectric layer and at least one second dielectric layer, the forbidden band width of the second dielectric layer is greater than the forbidden band width of the first dielectric layer, And the thickness of the single layer of the second dielectric layer is less than or equal to the thickness of the single layer of the first dielectric layer; and The quantum tunneling suppression layer is disposed on the surface of the stacked dielectric structure, or between the first dielectric layer and the second dielectric layer of the stacked dielectric structure, so The dielectric constant of the quantum tunneling suppression layer is greater than that of the first dielectric layer and greater than that of the second dielectric layer. 2. The high dielectric film layer structure according to claim 1, characterized in that the quantum tunneling suppression layer is a titanium dioxide layer. 3. The high dielectric film layer structure according to claim 2, wherein the first dielectric layer is a zirconium dioxide layer, and the second dielectric layer is an aluminum oxide layer. 4. The high dielectric film layer structure according to claim 3, characterized in that, the stacked dielectric structure is selected from the stacked stacked structure of zirconium dioxide and aluminum oxide successively, zirconium dioxide One of the group consisting of a layered structure stacked with aluminum oxide and zirconium dioxide in sequence and a stacked structure with aluminum oxide, zirconium dioxide, and aluminum oxide stacked in sequence. 5. The high dielectric film structure according to claim 1, wherein the first dielectric layer has a dielectric constant greater than or equal to 10, and the second dielectric layer has a band gap greater than or equal to 8 . 6 . The high dielectric film structure according to claim 1 , wherein at least one of silicon nitride and silicon oxynitride is doped in the stacked dielectric structure. 7. The high dielectric film structure according to claim 1, characterized in that the thickness of the high dielectric film structure is 4-10 nm. 8. The high-dielectric film structure according to any one of claims 1 to 7, wherein the high-dielectric film structure also includes a leakage barrier layer, and the number of the stacked dielectric structures is At least two, wherein the leakage blocking layer is located between the stacked dielectric structures. 9. The high-dielectric film structure according to claim 8, wherein the material of the leakage barrier layer comprises silicon dioxide, and the thickness of the leakage barrier layer is smaller than that of a single layer in the stacked dielectric structure. layer the thickness of the second dielectric layer. 10. A capacitor structure, characterized in that it comprises: The lower plate is connected with the lower electrode; an upper plate connected to an upper electrode; and The high dielectric film structure according to claim 1, located between the upper plate and the lower plate. 11. The capacitor structure according to claim 10, wherein the quantum tunneling suppression layer is located between the stacked dielectric structure and the lower plate. 12. The capacitor structure according to claim 10, wherein the number of the stacked dielectric structures is four, which are composed of stacked dielectric structures in which zirconium dioxide and aluminum oxide are stacked in sequence , and the four stacked dielectric structures are stacked sequentially from bottom to top; the number of the quantum tunneling suppression layer is 2 layers, which are respectively arranged between the lower electrode plate and the bottom layer of zirconium dioxide , and between the top aluminum oxide layer and the upper plate. 13. The capacitor structure according to any one of claims 10 to 12, wherein at least one section of the lower plate is U-shaped, and the corresponding structure of the high dielectric film layer and the upper plate The sections are all M-shaped, forming a double-sided capacitor structure. 14. A method for preparing a high dielectric film structure, characterized in that, the high dielectric film structure is a structure composed of N layers of films, wherein N is an integer greater than or equal to 3, and the preparation method comprises: forming at least one stacked dielectric structure, and the stacked dielectric structure includes at least one first dielectric layer and at least one second dielectric layer, and the forbidden band width of the second dielectric layer is greater than the forbidden band width of the first dielectric layer, and the unit thickness of the second dielectric layer is less than or equal to the unit thickness of the first dielectric layer; and forming at least one quantum tunneling suppression layer, and it is formed on the surface of the stacked dielectric structure, or formed on the first dielectric layer and the second dielectric layer of the stacked dielectric structure between dielectric layers, and the dielectric constant of the quantum tunneling suppression layer is greater than the dielectric constant of the first dielectric layer and greater than the dielectric constant of the second dielectric layer. 15. The preparation method of the high dielectric film structure according to claim 14, characterized in that, the quantum tunneling suppression layer is a titanium dioxide layer, the first dielectric layer is a zirconium dioxide layer, and the second The dielectric layer is an aluminum oxide layer. 16. The preparation method of the high dielectric film structure according to claim 14, characterized in that, the process of forming the high dielectric film structure composed of N film layers comprises forming the second film layer to the Nth film layer The step of layer film layer, concrete steps comprise: Forming a layer of hydroxide ion layer on the upper surface of the provided first film layer, and reacting the simple substance corresponding to the oxide contained in the hydroxide ion layer and the second layer film layer, to forming said second film layer; and Forming a layer of hydroxide ion layer on the upper surface of the formed N-1th film layer, and making the hydroxide ion layer react with the elemental substance corresponding to the oxide contained in the N-th film layer, to Form the Nth film layer. 17. the preparation method of high dielectric film structure according to claim 16 is characterized in that, in the process of forming described second film layer and the Nth film layer, its process gas is selected from zirconium, silicon, At least one of the group consisting of aluminum, niobium, hafnium and titanium, the process pressure is 0.1-2 Torr, and the process temperature is 200-400°C. 18. according to the preparation method of claim 16 or 17 described high dielectric film structure, it is characterized in that, the method for forming described hydroxide ion layer comprises: in reaction furnace, to pass into gas and be selected from steam and One of the ozone, and the structure to be formed with the hydroxide ion layer is treated by heating, so as to form a layer of hydroxide ion layer on the upper surface of the structure to be formed with the hydroxide ion layer. 19. A method for preparing a capacitor structure, comprising the steps of: 1) Provide the following plates; 2) forming a layer of hydroxide ion layer on the upper surface of the lower plate, allowing the hydroxide ion layer to react with the elemental substance corresponding to the oxide contained in the first layer of the film layer to form the first layer of film Floor; 3) prepare the second layer to the Nth film layer on the surface of the first film layer according to the method according to claim 14, to form a high dielectric film layer structure composed of N film layers, wherein N is an integer greater than or equal to 3; and 4) Forming an upper pole plate on the surface of the structure obtained in step 3).