CN107316657B - Memory cell - Google Patents
Memory cell Download PDFInfo
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- CN107316657B CN107316657B CN201610263582.1A CN201610263582A CN107316657B CN 107316657 B CN107316657 B CN 107316657B CN 201610263582 A CN201610263582 A CN 201610263582A CN 107316657 B CN107316657 B CN 107316657B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 33
- 229920005591 polysilicon Polymers 0.000 claims description 33
- 238000003860 storage Methods 0.000 abstract description 6
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000002035 prolonged effect Effects 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
Abstract
The present invention provides a memory cell, including: a semiconductor substrate; the floating gate structure comprises a drain region, a connecting region and a source region which are arranged in the semiconductor substrate along a first direction in sequence, a selection gate arranged on the semiconductor substrate between the drain region and the connecting region, and a floating gate arranged on the semiconductor substrate between the connecting region and the source region, wherein the length of the floating gate extending along a second direction is greater than that of the selection gate; and a first end and a second end are formed on one side of the floating gate, which is far away from the selection gate in the second direction, a control gate is formed on the first end, a programming source region and a programming drain region are respectively formed in the semiconductor substrate on two sides of the second end, and the second end, the programming source region and the programming drain region form a programming transistor. In the invention, the programming region and the erasing region are separated, the programming operation is carried out on the programming transistor, the operating voltage required on the control grid is smaller, the storage unit can be better protected, and the power consumption of the storage unit is reduced, thereby improving the performance of the storage unit and prolonging the service life of the storage unit.
Description
Technical Field
The invention relates to the technical field of storage units, in particular to a storage unit.
Background
Memory cell devices are commonly provided as internal components, semiconductor integrated circuits, in computers or other electronic devices. Memory cells are classified into many different types, such as random access memory cells (RAM), read only memory cells (ROM), dynamic random access memory cells (DRAM), synchronous dynamic random access memory cells (SDRAM), and non-volatile flash memory cells. Flash memory cell devices have developed into a popular source of non-volatile memory cells for various electronic applications. Flash memory cell devices typically use single transistor memory cells that allow for high memory cell density, high reliability, and low power consumption. Common uses for flash memory cells include personal computers, Personal Digital Assistants (PDAs), digital cameras, and cellular telephones.
A prior art memory cell includes a source, a drain, a select gate, a floating gate, and a control gate on the floating gate. When operating a memory cell, the select gate is used to select one of the memory cells, and a higher operating voltage is applied to the control gate, and electrons (i.e., data) are stored in the floating gate. However, the higher operating voltage on the control gate makes the power consumption of the memory cell large, and therefore, the level of the operating voltage on the control gate determines the power consumption of the memory cell.
Disclosure of Invention
The present invention is directed to a memory cell, which solves the problem of power consumption caused by a higher operating voltage applied to a control gate in the prior art.
To solve the above technical problem, the present invention provides a memory cell, including: a semiconductor substrate; the semiconductor device comprises a drain region, a connecting region and a source region which are arranged in the semiconductor substrate along a first direction in sequence, a selection gate on the semiconductor substrate between the drain region and the connecting region, and a floating gate on the semiconductor substrate between the connecting region and the source region, wherein the length of the floating gate extending along a second direction is greater than that of the selection gate; and a first end and a second end are formed on one side of the floating gate, which is far away from the selection gate in the second direction, a control gate is formed on the first end, a programming source region and a programming drain region are respectively formed in the semiconductor substrate on two sides of the second end, and the second end, the programming source region and the programming drain region form a programming transistor.
Optionally, the select gate and the floating gate are formed of a first polysilicon.
Optionally, the control gate is formed of a second polysilicon.
Optionally, the second polysilicon further covers the drain region, the source region, and the connection region.
Optionally, the source region, the connection region, and the drain region are all doped P-type.
Optionally, a first through hole is formed on the second polysilicon covering the drain region, and a second through hole is formed on the second polysilicon covering the source region.
Optionally, the programming source region and the programming drain region are both doped N-type, and the programming transistor is an NMOS transistor.
Optionally, the second polysilicon further covers the programming source region and the programming drain region, and the programming source region and the programming drain region are connected through the second polysilicon.
Optionally, a third through hole is formed on the second polysilicon covering the programming source region or the second polysilicon covering the programming drain region.
Optionally, a fourth through hole is formed on the select gate, and a fifth through hole is formed on the control gate.
Optionally, the first direction and the second direction are perpendicular.
Optionally, during the programming operation, a voltage of 9V to 14V is applied to the control gate, and a voltage of 0V is applied to the second terminal.
Optionally, during the erasing operation, a voltage of 0V is applied to the control gate, and a voltage of 9V to 14V is applied to the source region.
Compared with the prior art, the memory cell provided by the invention comprises the programming transistor, the programming region and the erasing region of the memory cell are separated, the programming operation is carried out on the programming transistor of the memory cell to achieve the same programming window, the operating voltage required on the control grid is smaller, the power consumption of the memory cell can be reduced, and the memory cell can be better protected, so that the performance of the memory cell is improved, and the service life of the memory cell is prolonged.
Drawings
FIG. 1 is a schematic top view of a memory cell according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a memory cell according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a programming transistor in accordance with an embodiment of the present invention;
FIG. 4 illustrates threshold voltages of memory cells according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of threshold voltages of a memory cell for multiple cycles according to an embodiment of the present invention.
Detailed Description
The memory cell of the present invention will be described in more detail in the following with reference to the schematic drawings, in which preferred embodiments of the invention are shown, it being understood that a person skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The core idea of the invention is that a memory cell is provided comprising: a semiconductor substrate; the semiconductor device comprises a drain region, a connecting region and a source region which are arranged in the semiconductor substrate along a first direction in sequence, a selection gate on the semiconductor substrate between the drain region and the connecting region, and a floating gate on the semiconductor substrate between the connecting region and the source region, wherein the length of the floating gate extending along a second direction is greater than that of the selection gate; and a first end and a second end are formed on one side of the floating gate, which is far away from the selection gate in the second direction, a control gate is formed on the first end, a programming source region and a programming drain region are respectively formed in the semiconductor substrate on two sides of the second end, and the second end, the programming source region and the programming drain region form a programming transistor. In the invention, the memory cell is divided into a programming region and an erasing region, programming operation is carried out on the programming transistor to achieve the same programming window, the operating voltage required on the control grid is smaller, the memory cell can be better protected, and the power consumption of the memory cell is reduced, so that the performance of the memory cell is improved, and the service life of the memory cell is prolonged.
The memory cell of the present invention will be described in detail with reference to the accompanying drawings, wherein fig. 1 is a top view of the memory cell, fig. 2 is a schematic cross-sectional view along AA 'of fig. 1, and fig. 3 is a schematic cross-sectional view along BB' of fig. 1.
With reference to fig. 1 and 2, the memory cell includes: a semiconductor substrate 100; a drain region D, a connection region 160 and a source region S in said semiconductor substrate 100, a select gate SG on said semiconductor substrate 100 between said drain region D and said connection region 160, a floating gate FG (not shown in fig. 1) on said semiconductor substrate 100 between said connection region 160 and said source region S, arranged in sequence along a first direction (X-direction). In this embodiment, the select gate SG and the floating gate FG are formed by a first polysilicon 130, and the extension length of the first polysilicon 130 forming the floating gate FG in the second direction (Y direction) is longer than the extension length of the first polysilicon 130 forming the select gate FG in the second direction (Y direction), i.e., the extension length of the floating gate FG in the second direction (Y direction) is longer than that of the select gate SG, wherein the first direction (X direction) and the second direction (Y direction) are perpendicular. In addition, the floating gate FG is formed with a first end 131 and a second end 132 at a side away from the select gate SG in the second direction (Y direction), and a control gate CG is formed on the first end 131, and in this embodiment, the control gate CG is formed by a second polysilicon 140. It is understood that a dielectric layer (not shown in fig. 1) is formed as a gate dielectric layer between the select gate SG and the semiconductor substrate 100, between the floating gate FG and the semiconductor substrate 100, and between the floating gate FG and the control gate CG, the select gate SG is used for selecting one of the memory cells when the memory cell is operated, and an operating voltage is applied to the control gate CG, so that data is stored in the floating gate FG.
In this embodiment, the source region S, the connection region 160, and the drain region D are all doped P-type, and the source region S, the connection region 160, and the drain region D form a first active region (NW)110, and are formed by performing ion implantation on the first active region 110, respectively. It should be noted that the second polysilicon 140 further covers the drain region D, the source region S and the connection region 160, so that the drain region D, the source region S and the connection region 160 can be led out later, thereby reducing the area of the memory cell.
Referring to fig. 1 and 3, a programming source region S 'and a programming drain region D' are respectively formed in the semiconductor substrate 100 on both sides of the second end 132, and the second end 132, the programming source region S 'and the programming drain region D' form a programming transistor 170. Further, in this embodiment, the programming source region S 'and the programming drain region D' are both doped N-type, the programming source region S 'and the programming drain region D' are both formed in a second active region (P-well) 120, and the programming transistor 170 is an NMOS transistor. In this embodiment, the second polysilicon 140 further covers a portion of the second active region 120, the programming source region S 'and the programming drain region D', so that the programming source region S 'and the programming drain region D' and the second active region 120 can be conveniently led out, thereby reducing the area of the memory cell. In addition, the second polysilicon 140 covering the programming source region S ', the second polysilicon 140 covering the programming drain region D', and the second polysilicon 140 covering the second active region 120 are connected, that is, the programming source region S ', the programming drain region D', and the second active region 120 are connected by the second polysilicon 140, so that the source, the drain, and the substrate of the formed programming transistor 170 are all connected, and thus the programming transistor can be led out only by forming an extraction electrode subsequently, and the area of the memory cell is reduced.
With continued reference to fig. 1, a first via 151 is formed on the second polysilicon 140 covering the drain region D, a second via 152 is formed on the second polysilicon 140 covering the source region S, a third via 153 is formed on the second polysilicon covering the programming source region or the second polysilicon covering the programming drain region or the second polysilicon covering a portion of the second active region 120, a fourth via 154 is formed on the select gate SG, and a fifth via 155 is formed on the control gate CG. The first through hole 151, the second through hole 152, the third through hole 153, the fourth through hole 154, and the fifth through hole 155 are used to lead out the drain region D, the source region S, the programming transistor 170, the selection gate SG, and the control gate CG, respectively.
Referring to fig. 4, a relationship between control gate CG and threshold voltage during operation of the memory cell is shown in fig. 4, curve a representing a prior art memory cell and curve b representing a memory cell of the present invention. Comparing the curve a and the curve b, it can be seen that when the memory cell of the present invention is programmed, the voltage of 9V to 14V is applied to the control gate, and the voltage of 0V is applied to the programming transistor, and when the memory cell of the present invention and the memory cell of the prior art reach the same threshold voltage, the programming voltage required on the control gate CG is smaller, for example, reduced by 1.6V, so that the power consumption required during the operation of the memory cell is smaller. In the present invention, the program region and the erase region are separated, and when erasing the memory cell, a voltage of 0V is applied to the control gate, and a voltage of 9V to 14V is applied to the source region and the first active region 110.
Referring to fig. 5, a graph of the threshold voltage of the memory cell as a function of the number of erase/program cycles is shown in fig. 5, where a curve c represents the threshold voltage of a program operation of a memory cell of the prior art, a curve d represents the threshold voltage of a program operation of a memory cell of the present invention, a curve e represents the threshold voltage of an erase operation of a memory cell of the prior art, and a curve f represents the threshold voltage of an erase operation of a memory cell of the present invention. As can be seen from fig. 5, compared with the prior art, the addition of the programming transistor in the memory cell does not affect the use of erasing/programming of the memory cell.
In summary, the memory cell and the method for manufacturing the same provided by the invention include a programming transistor, the programming region and the erasing region are separated, the programming operation is performed on the programming transistor of the memory cell to achieve the same programming window, the operating voltage required on the control gate is smaller, the memory cell can be better protected, the power consumption of the memory cell is reduced, the performance of the memory cell is improved, and the service life of the memory cell is prolonged.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (12)
1. A memory cell, comprising: a semiconductor substrate; the semiconductor device comprises a drain region, a connecting region and a source region which are arranged in the semiconductor substrate along a first direction in sequence, a selection gate on the semiconductor substrate between the drain region and the connecting region, and a floating gate on the semiconductor substrate between the connecting region and the source region, wherein the length of the floating gate extending along a second direction is greater than that of the selection gate; a first end and a second end are formed on one side, far away from the selection gate, of the floating gate in the second direction, a control gate is formed on the first end, a programming source region and a programming drain region are formed in the semiconductor substrate on two sides of the second end respectively, and a programming transistor is formed by the second end, the programming source region and the programming drain region; wherein the first direction and the second direction are perpendicular.
2. The memory cell of claim 1 wherein said select gate and said floating gate are formed from a first polysilicon.
3. The memory cell of claim 2 wherein the control gate is formed of a second polysilicon.
4. The memory cell of claim 3, wherein the second polysilicon also covers the drain region, the source region, and the connection region.
5. The memory cell of claim 4, wherein the source region, the connection region, and the drain region are all P-type doped.
6. The memory cell of claim 4, wherein a first via is formed in the second polysilicon overlying the drain region and a second via is formed in the second polysilicon overlying the source region.
7. The memory cell of claim 4, wherein the program source region and the program drain region are both N-type doped, and the program transistor is an NMOS transistor.
8. The memory cell of claim 3 wherein said second polysilicon also covers a program source region and said program drain region, said program source region and said program drain region being connected by said second polysilicon.
9. The memory cell of claim 8, wherein a third via is formed on the second polysilicon overlying the program source region or the second polysilicon overlying the program drain region.
10. The memory cell of claim 1, wherein the select gate has a fourth via formed thereon and the control gate has a fifth via formed thereon.
11. The memory cell of claim 1 wherein during a program operation, the control gate is applied with a voltage of 9V to 14V, and the second terminal is applied with a voltage of 0V.
12. The memory cell of claim 1 wherein during an erase operation, the control gate is applied with a voltage of 0V and the source region is applied with a voltage of 9V to 14V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610263582.1A CN107316657B (en) | 2016-04-26 | 2016-04-26 | Memory cell |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610263582.1A CN107316657B (en) | 2016-04-26 | 2016-04-26 | Memory cell |
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| CN107316657A CN107316657A (en) | 2017-11-03 |
| CN107316657B true CN107316657B (en) | 2020-08-28 |
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| KR102252531B1 (en) | 2017-12-15 | 2021-05-14 | 청두 아날로그 써키트 테크놀로지 인코퍼레이티드 | Circuits and methods of programming into flash memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377701A (en) * | 2012-04-24 | 2013-10-30 | 华邦电子股份有限公司 | Semiconductor memory device |
| CN103824861A (en) * | 2014-01-15 | 2014-05-28 | 上海新储集成电路有限公司 | Fin-like back gate storage structure and automatic refreshing method of floating body cells |
| CN104617048A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101624980B1 (en) * | 2009-06-19 | 2016-05-27 | 삼성전자주식회사 | Non-Volatile Memory Device |
| US9312014B2 (en) * | 2013-04-01 | 2016-04-12 | SK Hynix Inc. | Single-layer gate EEPROM cell, cell array including the same, and method of operating the cell array |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377701A (en) * | 2012-04-24 | 2013-10-30 | 华邦电子股份有限公司 | Semiconductor memory device |
| CN104617048A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and forming method thereof |
| CN103824861A (en) * | 2014-01-15 | 2014-05-28 | 上海新储集成电路有限公司 | Fin-like back gate storage structure and automatic refreshing method of floating body cells |
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