CN107302004B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN107302004B CN107302004B CN201610206310.8A CN201610206310A CN107302004B CN 107302004 B CN107302004 B CN 107302004B CN 201610206310 A CN201610206310 A CN 201610206310A CN 107302004 B CN107302004 B CN 107302004B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
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- 238000007517 polishing process Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000015654 memory Effects 0.000 description 22
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract
A semiconductor device and a method of forming the same, wherein the method comprises: providing a semiconductor substrate; etching a semiconductor substrate to form a slope substrate, wherein the slope substrate is provided with a top surface, a bottom surface and a slope surface connecting the top surface and the bottom surface; forming a plurality of laminated composite layers on the slope substrate from bottom to top, wherein each composite layer comprises an insulating layer and a sacrificial layer positioned on the surface of the insulating layer; forming a first dielectric layer covering the composite layer; planarizing the first dielectric layer and the composite layer until the top surface is exposed, and enabling the top surface of the composite layer above the slope surface to be flush with the top surface; removing the sacrificial layer to form an opening; a control gate is formed in the opening. The method simplifies the process and reduces the cost.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
Flash memories (also called Flash memories) are mainly characterized by being capable of maintaining stored information for a long time without power up and having the advantages of high integration level, high access speed, easy erasing and rewriting and the like, and thus, Flash memories are mainstream memories of non-volatile memories. Flash memories are classified into NOR Flash memories (NOR Flash memories) and NAND Flash memories (NAND Flash memories) according to their structures. Compared with NOR Flash Memory, NAND Flash Memory can provide high unit density, can achieve high storage density, and has faster writing and erasing speed.
With the development of planar flash memories, the manufacturing process of semiconductors has made great progress. However, the development of planar flash memories currently encounters various challenges: physical limits such as exposure technology limits, development technology limits, and storage electron density limits. In this context, three-dimensional (3D) flash memory applications, such as 3D NAND flash memory, have been developed to address the difficulties encountered with planar flash memory and to pursue lower production costs per unit cell.
However, in the prior art, the process of the semiconductor device formed by the 3D NAND flash memory cell is complex and high in cost.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which aims to simplify the process and reduce the cost.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate; etching a semiconductor substrate to form a slope substrate, wherein the slope substrate is provided with a top surface, a bottom surface and a slope surface connecting the top surface and the bottom surface; forming a plurality of laminated composite layers on the slope substrate from bottom to top, wherein each composite layer comprises an insulating layer and a sacrificial layer positioned on the surface of the insulating layer; forming a first dielectric layer covering the composite layer; planarizing the first dielectric layer and the composite layer until the top surface is exposed, and enabling the top surface of the composite layer above the slope surface to be flush with the top surface; removing the sacrificial layer to form an opening; a control gate is formed in the opening.
Optionally, the process of etching the semiconductor substrate to form the slope substrate is as follows: forming a first mask layer on the semiconductor substrate, wherein the surface of the semiconductor substrate covered by the first mask layer defines the position of the top surface; and etching the semiconductor substrate by using the first mask layer as a mask and adopting an anisotropic dry etching process to form a slope substrate.
Optionally, the parameters of the anisotropic dry etching process are as follows: the adopted gas comprises etching gas and buffer gas, wherein the etching gas is Cl2、Br2One or more of HCl and HBr, and the buffer gas is N2And Ar, wherein the flow rate of the etching gas is 100-200 sccm, the flow rate of the buffer gas is 100-200 sccm, the source radio frequency power is 500-1000W, the bias radio frequency power is 500-1000W, and the pressure of the chamber is 10-50 mtorr.
Optionally, an included angle between the edge slope surface and the bottom surface is 120-150 degrees.
Optionally, the process of planarizing the first dielectric layer and the composite layer until the top surface is exposed is a chemical mechanical polishing process.
Optionally, the insulating layer is made of silicon oxide, silicon oxynitride or silicon oxycarbide; the sacrificial layer is made of silicon nitride, amorphous carbon or polycrystalline silicon.
Optionally, the number of the composite layers is 2 to 256.
Optionally, after planarizing the first dielectric layer and the composite layer until the top surface is exposed and before removing the sacrificial layer, the method further includes: forming a trench via in the first dielectric layer and the composite layer over the bottom surface; forming a channel layer in the channel via.
Optionally, the method further includes: forming a second dielectric layer covering the first dielectric layer, the control gate, the insulating layer and the slope substrate; and forming a plurality of word line plug holes in the second dielectric layer, wherein the word line plug holes are respectively exposed out of the top surface of each layer of control gate above the slope surface.
Optionally, the bottom surface and the side slope constitute a first surface; further comprising: forming a support through hole penetrating through the first dielectric layer and the composite layer, wherein the support through hole exposes out of the first surface; forming a support layer in the support through hole; planarizing the support layer while planarizing the first dielectric layer and composite layer until the top surface is exposed.
Optionally, the number of the support through holes is one or more.
Optionally, the support via exposes the bottom surface.
Optionally, the support through-hole exposes the edge slope.
Optionally, when the number of the support through holes is multiple, part of the support through holes are exposed out of the bottom surface, and part of the support through holes are exposed out of the side slope surface.
Optionally, the material of the support layer is silicon oxide, silicon oxynitride, or silicon oxycarbide.
Optionally, the process for forming the support through hole includes: forming a second mask layer on the surface of the first medium layer, wherein the second mask layer is provided with a supporting through hole pattern opening, and the supporting through hole pattern opening defines the position of a supporting through hole; etching the first dielectric layer and the composite layer by using the second mask layer as a mask through an anisotropic dry etching process until the first surface is exposed to form a support through hole; and removing the second mask layer.
Optionally, after etching the first dielectric layer and the composite layer by using the second mask layer as a mask and using an anisotropic dry etching process until the first surface is exposed, the method further includes: and continuously etching part of the slope substrate downwards by taking the second mask layer as a mask.
Optionally, before planarizing the first dielectric layer and the composite layer until the top surface is exposed, further comprising: forming a grinding blocking layer covering the first medium layer; planarizing the polish stop layer while planarizing the first dielectric layer and the composite layer until the top surface is exposed.
Optionally, in the process of planarizing the first dielectric layer, the composite layer, and the polishing stop layer until the top surface is exposed, the polishing rate of the polishing stop layer is less than the polishing rate of the first dielectric layer.
The present invention also provides a semiconductor device comprising: a slop substrate having a top surface, a bottom surface, and a slop surface connecting the top and bottom surfaces; the control gates are positioned on the bottom surface and the side slope surface and are stacked from bottom to top; the insulating layers are positioned between the slope substrate and the bottom control grid and between the adjacent control grids, are stacked from bottom to top, and are flush with the top surface of the control grid above the slope surface; and the first dielectric layer is positioned on the control gate and the insulating layer, and the top surface of the control gate above the slope surface is exposed out of the first dielectric layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
due to the formation of the slope substrate, after the composite layer is formed, part of the composite layer is positioned on the slope surface, so that the top surface of the composite layer above the slope surface can be exposed after the first dielectric layer and the composite layer are flattened until the top surface is exposed, and the top surface of the composite layer above the slope surface is flush with the top surface; after forming the control gate, making a top surface of the control gate above the slope, a top surface of the insulating layer above the slope, and the top surface flush; a second dielectric layer covering the first dielectric layer, the control gates, the insulating layer and the slope substrate is formed subsequently, word line plug holes are formed in the second dielectric layer, the top surfaces of the control gates above the slope surfaces are required to be exposed out of the word line plug holes, and the top surfaces of the control gates above the slope surfaces are consistent in height, so that the word line plug holes can be formed simultaneously in one step without forming the word line plug holes in steps, and the process steps are simplified; the process steps are simplified, so that the cost is reduced.
In addition, after the composite layer is formed, a stepped sacrificial layer is formed without adopting a plurality of etching processes, so that the process steps are further simplified; the process steps are further simplified, so that the cost is further reduced.
Drawings
FIG. 1 is a schematic diagram of a 3D NAND flash memory cell in the prior art;
fig. 2 to 13 are schematic structural views of a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the 3D NAND flash memory cell in the prior art has a complex process and high cost.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a 3D NAND flash memory cell, the 3D NAND flash memory cell including: a semiconductor substrate 100; a plurality of stacked control gates 110 on the semiconductor substrate 100; an insulating layer 120 between adjacent control gates 110, between the bottom control gate 110 and the semiconductor substrate 100; a first sub-dielectric layer 121 covering the control gate 110 and the insulating layer 120, wherein only a portion of the first sub-dielectric layer 121 is shown for convenience of illustration; a via (not shown) penetrating the thickness of the control gate 110, the insulating layer 120 and the first sub-dielectric layer 121; a substrate extension region 101 at the bottom of the via; the gate dielectric layer 130 is positioned on the side wall of the through hole on the substrate extension region 101 and on part of the surface of the substrate extension region 101; the channel layer 140 is positioned in the through hole and positioned on the surface of the gate dielectric layer 130; a channel dielectric layer 150 located in the via and wrapped by the channel layer 140; a second sub-dielectric layer 160 covering the first sub-dielectric layer 121, the gate dielectric layer 130, the channel layer 140 and the channel dielectric layer 150; a groove 170 penetrating the thicknesses of the second sub-dielectric layer 160, the first sub-dielectric layer 121, the insulating layer 120 and the control gate 110; a source line doping region 180 located in the semiconductor substrate 100 below the groove 170; a source line structure (not shown) filling the recess 170; several word line plugs 111 on the surface of each control gate 110; a plurality of word lines 112 on top of the plurality of word line plugs 111; a bit line plug 190 penetrating the thickness of the second sub-dielectric layer 160 and connected to the channel layer 140; and a plurality of discrete bit lines 191 positioned on the top surfaces of the plurality of bit line plugs 190 and crossing the source line structures.
The size of the pattern projected on the surface of the semiconductor substrate 100 by the plurality of layers of stacked control gates 110 is gradually increased from top to bottom; the control gates 110 of the upper layer can expose part of the control gates 110 of the lower layer, and the surface of the control gates 110 of the lower layer exposed by the control gates 110 of the upper layer is used for connecting with word line plugs 111, and the word line plugs 111 are connected with the control gates 110 of only one layer.
To form the stepped control gate 110 shown in fig. 1, in one embodiment, the process of forming the control gate 110 includes: providing a semiconductor substrate; forming a composite layer on the semiconductor substrate, wherein the composite layer comprises a plurality of insulating layers and a plurality of sacrificial layers which are stacked in a staggered mode, the bottom layer of the composite layer is an insulating layer, and the top layer of the composite layer is a sacrificial layer; forming a mask layer on the surface of the composite layer; etching the side wall and the top surface of the mask layer to expose the surface of the composite layer of the top layer around the mask layer; etching the exposed composite layer by taking the etched mask layer as a mask until the surface of the next insulating layer or the surface of the next sacrificial layer is exposed; repeating the steps of etching the mask layer and the composite layer until the plurality of stacked sacrificial layers are gradually increased from top to bottom in a step shape, wherein the graphic sizes of the plurality of stacked sacrificial layers projected on the surface of the semiconductor substrate are gradually increased from top to bottom; removing the sacrificial layer to form an opening; a control gate is formed in the opening.
It can be seen that in order to form the control gate 110, a sacrificial layer needs to be formed first, and the formation of the sacrificial layer adopts multiple steps (repeated etching of the mask layer and etching of the composite layer), which increases the complexity of the process and increases the cost.
In addition, in order to form the word line plugs 111, it is necessary to form word line plug holes penetrating the second sub-dielectric layer 160, the first sub-dielectric layer 121, and the composite layer, and then form the word line plugs 111 in the word line plug holes. Because the control gates 110 are in a ladder shape, the heights of the control gates 110 in each layer are not consistent, the heights of the word line plug holes on the surface of the control gate 110 in the next layer are larger than the heights of the word line plug holes on the surface of the control gate 110 in the previous layer, the word line plug holes need to be formed in steps in the process of forming the word line plug holes, generally, when the number of the control gates 110 is larger than 16, the word line plug holes corresponding to the control gates 110 in the 5-6 layers need to be formed by etching every 5-6 layers of the control gates 110, and therefore, the phenomenon that the word line plug holes penetrate through the corresponding control gates 110 to be connected in the process of forming the word line plug holes can be avoided.
Therefore, the word line plug hole needs to be formed in steps, which increases the complexity of the process and the corresponding cost.
On the basis, the invention provides a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate; etching a semiconductor substrate to form a slope substrate, wherein the slope substrate is provided with a top surface, a bottom surface and a slope surface connecting the top surface and the bottom surface; forming a plurality of laminated composite layers on the slope substrate from bottom to top, wherein each composite layer comprises an insulating layer and a sacrificial layer positioned on the surface of the insulating layer; forming a first dielectric layer covering the composite layer; planarizing the first dielectric layer and the composite layer until the top surface is exposed, and enabling the top surface of the composite layer above the slope surface to be flush with the top surface; removing the sacrificial layer to form an opening; a control gate is formed in the opening. The method simplifies the process and reduces the cost.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 13 are schematic structural views of a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 2, a semiconductor substrate 200 is provided.
The semiconductor substrate 200 may be single crystal silicon, polycrystalline silicon, or amorphous silicon; the semiconductor substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like, which is not illustrated. In this embodiment, the semiconductor substrate 200 is silicon.
Referring to fig. 3, a semiconductor substrate 200 is etched to form a slope substrate 210, the slope substrate 210 having a top surface 213, a bottom surface 211, and a slope 212 connecting the top surface 213 and the bottom surface 211.
The bottom surface 211 is lower than the top surface 213, and the height of the side slope 212 is between the height of the bottom surface 211 and the top surface 213.
Specifically, a first mask layer is formed on the semiconductor substrate 200, and the position of the top surface 213 is defined on the surface of the semiconductor substrate 200 covered by the first mask layer; and etching the semiconductor substrate 200 by using the first mask layer as a mask and adopting an anisotropic dry etching process to form a slope substrate 210.
In one embodiment, the angle θ between the slope surface 212 and the bottom surface 211 is an obtuse angle, and the angle between the slope surface 212 and the top surface 213 is an obtuse angle.
When the included angle θ between the slope surface 212 and the bottom surface 211 is an obtuse angle, and the included angle between the slope surface 212 and the top surface 213 is an obtuse angle, the process of forming the slope substrate 210 is as follows: in the process of etching the semiconductor substrate 200 by using the anisotropic dry etching process, a groove is formed; meanwhile, in the process of etching the semiconductor substrate 200, byproducts are generated, the accumulation of the byproducts can reduce the etching rate, the technological parameters of etching are adjusted to enable the byproducts to be accumulated on the side wall of the groove, and the etching rate of the side wall of the groove is reduced; in addition, since it is more difficult for etching gas to enter the bottom of the groove than for etching gas to enter the top of the groove in the process of etching the semiconductor substrate 200, the etching rate to the bottom of the groove is lower than that to the top of the groove. After the semiconductor substrate 200 is etched, the side wall of the groove is inclined, an included angle formed by the bottom surface of the groove and the side wall of the groove is an obtuse angle, the inclined side wall of the groove forms a slope surface 212, and the bottom surface of the groove forms a bottom surface 211.
The advantage of the obtuse angle θ formed between the slope surface 212 and the bottom surface 211 is that: the difficulty of forming a composite layer on the surface of the side slope 212 in the following process is reduced, and particularly when the number of the composite layers is greater than 16, the difficulty of forming the composite layer on the surface of the side slope 212 is reduced more obviously, and the process difficulty is reduced.
Specifically, the included angle between the side slope surface 212 and the bottom surface 211 may be 120 degrees to 150 degrees. The significance of the selected range of the included angle between the slope surface 212 and the bottom surface 211 is as follows: if the angle between the slope 212 and the bottom surface 211 is greater than 150 degrees, which results in an excessively small height difference between the top surface 213 and the bottom surface 211, after the composite layer is subsequently formed, the top surface of the composite layer above the bottom surface 211 is higher than the top surface 213, which results in polishing a portion of the composite layer above the bottom surface until the top surface 213 is exposed, thereby damaging the semiconductor device; if the included angle between the slope surface 212 and the bottom surface 211 is smaller than 120 degrees, the slope surface 212 has a too small inclination degree, which results in a too small area of the top surface of each layer of control gate formed above the slope surface 212, the word line plug is easily electrically connected to the top surfaces of the control gates of different layers at the same time, and when the inclination degree of the slope surface 212 is too small, the difficulty of forming a composite layer on the surface of the slope surface 212 increases.
In another embodiment, the angle θ between the slope surface 212 and the bottom surface 211 is right, and the angle between the slope surface 212 and the top surface 213 is right.
In yet another embodiment, the angle θ between the slope surface 212 and the bottom surface 211 is acute, and the angle between the slope surface 212 and the top surface 213 is acute.
In this embodiment, the anisotropy used for etching the semiconductor substrate 200The technological parameters of the dry etching process are as follows: the adopted gas comprises etching gas and buffer gas, wherein the etching gas is Cl2、Br2One or more of HCl and HBr, and the buffer gas is N2And Ar, wherein the flow rate of the etching gas is 100-200 sccm, the flow rate of the buffer gas is 100-200 sccm, the source radio frequency power is 500-1000W, the bias radio frequency power is 500-1000W, and the pressure of the chamber is 10-50 mtorr.
Referring to fig. 4, a plurality of laminated composite layers are formed on the slope substrate 210 from bottom to top.
Each composite layer includes an insulating layer 221 and a sacrificial layer 222 on the surface of the insulating layer 221. The number of layers of the composite layer is 2 to 256, and in a specific embodiment, the number of layers of the composite layer is 16 to 64. In actual process, the specific number of layers of the composite layer can be selected as required, and fig. 4 only illustrates 3 composite layers.
The direction in which the multilayer composite layers are stacked from bottom to top is a direction perpendicular to the bottom surface 211 or the top surface 213.
In the multilayer laminated composite layer, the sacrificial layer 222 is used for occupying the position for the control gate to be formed later, the sacrificial layer 222 is removed later, and the control gate is formed in the position left after the sacrificial layer 222 is removed; the insulating layer 221 is located between two adjacent sacrificial layers 222 and between the sacrificial layers 222 and the slope substrate 210, and after the position of the subsequent sacrificial layer 222 is replaced by a control gate, the insulating layer 221 is used for electrical isolation between the adjacent control gates and between the control gate and the slope substrate 210.
The insulating layer 221 and the sacrificial layer 222 are made of different materials, so that in the subsequent process of removing the sacrificial layer 222, the sacrificial layer 222 has a higher etching selection ratio relative to the insulating layer 221, thereby ensuring good appearance and accurate size of the insulating layer 221, and further ensuring good appearance and accurate size of a subsequently formed control gate. In addition, the sacrificial layer 222 needs to be selected to be easily removable. The insulating layer 221 is made of silicon oxide, silicon oxynitride, or silicon oxycarbide, in this embodiment, the insulating layer 221 is made of silicon oxide; the sacrificial layer 222 is made of silicon nitride, amorphous carbon or polysilicon, and in this embodiment, the sacrificial layer 222 is made of silicon nitride.
The process of forming the insulating layer 221 is a deposition process, such as a plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process, or a low pressure chemical vapor deposition process; the process for forming the sacrificial layer 222 is a deposition process, such as a plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process, or a low pressure chemical vapor deposition process.
Referring to fig. 5, a first dielectric layer 230 is formed overlying the composite layer.
The first dielectric layer 230 is made of silicon oxide, silicon oxynitride or silicon oxycarbide.
The process for forming the first dielectric layer 230 is as follows: a first dielectric material layer is formed to cover the composite layer by a deposition process, and the first dielectric material layer is planarized by a planarization process to form a first dielectric layer 230. In one embodiment, the entire surface of the first dielectric material layer is higher than the top surface of the composite layer above the top surface 213.
In this embodiment, the bottom surface 211 and the slope surface 212 constitute a first surface, and further include: a support via is formed through the thickness of the first dielectric layer 230 and the composite layer, the support via exposing the first surface. In other embodiments, the support through-hole may not be formed.
Specifically, the step of forming the support through-hole includes: with combined reference to fig. 6 and 7, fig. 6 is a schematic diagram formed on the basis of fig. 5, fig. 7 is a cross-sectional view taken along cutting line a-a1 in fig. 6, a second mask layer 240 is formed on the surface of the first dielectric layer 230, the second mask layer 240 has a support via pattern opening 241, and the support via pattern opening 241 defines the position of a support via to be formed; referring to fig. 8, fig. 8 is a schematic view formed on the basis of fig. 7, and the second mask layer 240 is used as a mask to etch the first dielectric layer 230 and the composite layer by using an anisotropic dry etching process until the first surface is exposed, so as to form a support via 231; referring to fig. 9, the second mask layer 240 (refer to fig. 8) is removed.
Specifically, the parameters of the anisotropic dry etching process used in the process of forming the support through hole 231 are as follows: the gas used is CF4And CH2F2，CF4The flow rate of (1) is 20sccm to 100sccm, CH2F2The flow rate of the gas source is 20-100 sccm, the source radio frequency power is 500-1500W, the bias radio frequency power is 500-1500W, and the pressure of the chamber is 10-50 mtorr.
The number of the support through-holes 231 is one or more. In this embodiment, fig. 8 only shows one supporting through hole 231, and in an actual process, the specific number of the supporting through holes 231 may be selected according to the process requirement.
In this embodiment, the supporting through hole 231 exposes the slope surface 212; in another embodiment, the support via 231 exposes the bottom surface 211; in still another embodiment, when the number of the support through holes 231 is plural, it may be: part of the support through holes 231 exposes the side slope surface 212, and part of the support through holes 231 exposes the bottom surface 211.
Further, after the second mask layer 240 is used as a mask and the first dielectric layer 230 and the composite layer are etched by using an anisotropic dry etching process until the first surface is exposed, the second mask layer 240 may be used as a mask to etch a part of the side-slope substrate 210 downward to form the support through hole 231. After the support layer is formed in the support through hole 231, the support layer is partially located in the first dielectric layer 230 and the composite layer, and partially located in the slope substrate 210, so that the support layer and the slope substrate 210 are combined more firmly.
Referring to fig. 10, a support layer 232 is formed in the support through-hole 231 (refer to fig. 9).
The material of the support layer 232 is silicon oxide, silicon oxynitride, or silicon oxycarbide.
The process of forming the support layer 232 includes: forming a support material layer (not shown) on the top surface of the first dielectric layer 230 and in the support via 231 by a deposition process; the layer of support material is planarized until the top surface of the first dielectric layer 230 is exposed, forming a support layer 232.
Referring to fig. 11, the first dielectric layer 230 and the composite layer are planarized until the top surface 213 (refer to fig. 3) is exposed, and the top surface of the composite layer above the edge slope 212 (refer to fig. 3) is flush with the top surface 213.
The process of planarizing the first dielectric layer 230 and the composite layer is a chemical mechanical polishing process.
In this embodiment, since the support layer 232 is formed, the support layer 232 is planarized while the first dielectric layer 230 and the composite layer are planarized.
In another embodiment, before planarizing the first dielectric layer 230, the composite layer until the top surface 213 is exposed, the method further comprises: forming a polishing stop layer (not shown) covering the first dielectric layer 230 and the support layer 232; the polish stop layer is planarized while the first dielectric layer 230 and composite layer are planarized until the top surface 213 is exposed. It should be noted that, when the supporting layer 232 is formed, the polishing stop layer and the supporting layer 232 are planarized while the first dielectric layer 230 and the composite layer are planarized until the top surface 213 is exposed.
When the surface flatness of the first dielectric layer 230 is poor, for the purpose of illustration, a recess is formed on the surface of the first dielectric layer 230, and after a polishing stop layer is formed, the polishing stop layer fills the recessed area; grinding the grinding barrier layer until the top surface of the first dielectric layer 230 and the top surface of the grinding barrier layer in the recess are exposed, the top surface of the first dielectric layer 230 and the top surface of the grinding barrier layer in the recess being flush; in continuing to polish the first dielectric layer 230, the polish stop, the composite layer, and the support layer 232 until the top surface 213 is exposed, the polish stop in the recess can reduce the extent of polishing of the first dielectric layer 230 below the recess, such that: upon planarizing the polish stop layer, first dielectric layer 230, and composite layer until the top surface 213 is exposed, the degree of planarization of the entire top surface of the semiconductor device increases.
Since the planarization degree of the entire top surface of the semiconductor device is increased when the polishing stop layer, the first dielectric layer 230 and the composite layer are planarized until the top surface 213 is exposed, the top surface of the composite layer above the edge slope 212 (refer to fig. 3) is more flush, and the sacrificial layer 222 is subsequently removed and the control gate is formed in the position left after the sacrificial layer 222 is removed, so that the top surface of the control gate above the edge slope 212 (refer to fig. 3) is more flush, which is favorable for electrical contact between the subsequently formed word line plug and the top surface of the control gate.
In planarizing the polish stop layer, the first dielectric layer 230, and the composite layer, the polish rate for the polish stop layer is less than the polish rate for the first dielectric layer 230.
The grinding blocking layer is made of silicon oxide, silicon oxynitride, silicon oxycarbide or silicon nitride; in one embodiment, the material of the polishing stop layer is different from the material of the first dielectric layer 230, and when the material of the first dielectric layer 230 is silicon oxide, silicon oxynitride or silicon oxycarbide, the material of the polishing stop layer is silicon nitride; the first dielectric layer 230 and the polishing stop layer are formed by a deposition process, such as a plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a high density plasma chemical vapor deposition process, or an atomic layer deposition process. In another embodiment, the material of the polishing stop layer is the same as the material of the first dielectric layer 230, and at this time, the forming process of the polishing stop layer is different from the forming process of the first dielectric layer 230, so that the polishing rate of the polishing stop layer is lower than the polishing rate of the first dielectric layer 230 during the planarization of the polishing stop layer, the first dielectric layer 230 and the composite layer, specifically, the material of the polishing stop layer is silicon oxide, silicon oxynitride or silicon oxycarbide.
When the materials of the polishing barrier layer and the first dielectric layer 230 are both silicon oxide, silicon oxynitride, or silicon oxycarbide, the forming process of the polishing barrier layer is a sub-atmospheric pressure chemical vapor deposition (SACVD) process, the forming process of the first dielectric layer 230 is a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or the forming process of the polishing barrier layer is a high density plasma chemical vapor deposition process, and the forming process of the first dielectric layer 230 is a plasma enhanced atomic layer deposition process.
After planarizing the first dielectric layer 230 and composite layer until the top surface 213 is exposed, further comprising: forming a trench via (not shown) in the composite layer, first dielectric layer 230, above bottom surface 211; forming a gate dielectric layer on the side wall of the channel through hole; a channel layer (not shown) is then formed in the channel via.
Next, referring to fig. 12, the sacrificial layer 222 is removed, and an opening 250 is formed.
The process of removing the sacrificial layer 222 is a dry etching process or a wet etching process.
Referring to fig. 13, a control gate 260 is formed in the opening 250.
The control gate 260 is made of metal, such as W (tungsten) or TiAl.
The process of forming the control gate 260 is a deposition process, such as a chemical vapor deposition process.
In this embodiment, before forming the control gate 260, a control gate isolation layer (not shown) and a blocking layer (not shown) are further formed on the inner wall of the opening 250 from outside to inside in sequence. The control gate isolation layer is made of silicon oxide; the barrier layer is made of titanium nitride.
In this embodiment, a gate dielectric layer is formed on the sidewall of the trench via; in other embodiments, it may be: before forming control gate 260, a gate dielectric layer is formed on the inner wall of opening 250, and then control gate 260 is formed.
When a gate dielectric layer is formed on the inner wall of the opening 250, if a gate isolation layer and a blocking layer are required to be formed, the blocking layer is located between the control gate 260 and the gate dielectric layer, and the gate dielectric layer is formed after the gate isolation layer is formed.
Since the top surface of the composite layer above the edge slope 212 is flush with said top surface 213, the top surface of the control gate 260 above the edge slope 212, the top surface of the insulating layer 221 above the edge slope 212 and said top surface 213 are flush after the control gate 260 is formed in the opening 250 formed after removing said sacrificial layer 222.
Forming a second dielectric layer covering the first dielectric layer 230, the control gate 260, the insulating layer 221, the slope substrate 210, the gate dielectric layer and the channel layer; a plurality of word line plug holes are formed in the second dielectric layer, and each word line plug hole exposes the top surface of each layer of control gates 260 above the edge slope 212. In this embodiment, since the supporting layer 232 is formed, the second dielectric layer further covers the supporting layer 232.
The second dielectric layer is made of silicon oxide, silicon oxynitride or silicon oxycarbide. The process for forming the second dielectric layer is a deposition process.
Because the top surfaces of the control gates 260 above the side slope surfaces 212 are consistent in height, the word line plug holes can be formed simultaneously in one step, and the word line plug holes do not need to be formed in steps, so that the process steps are simplified; the process steps are simplified, so that the cost is reduced.
In addition, after the composite layer is formed, the control gate 110 in a step shape as shown in fig. 1 does not need to be formed, so that a sacrificial layer in a step shape corresponding to the control gate 110 does not need to be formed by adopting a multi-time etching process, and the process steps are further simplified; the process steps are further simplified, so that the cost is further reduced.
The semiconductor device formed in the present embodiment, referring to fig. 13, includes: a slop substrate 210, the slop substrate 210 having a top surface 213 (refer to fig. 3), a bottom surface 211 (refer to fig. 3), and a slop surface 212 (refer to fig. 3) connecting the top surface 213 and the bottom surface 211; a plurality of control gates 260 located on the bottom surface 211 and the side slope 212 and stacked from bottom to top; a plurality of insulating layers 221, which are positioned between the slope substrate 210 and the bottom control gate 260 and between the adjacent control gates 260, are stacked from bottom to top, and the top surfaces of the control gates 260 above the slope surfaces 212 are flush with the top surface 213; a first dielectric layer 230 is disposed on the control gate 260 and the insulating layer 221, and the first dielectric layer 230 exposes the top surface of the control gate 260 above the edge slope 212.
The bottom surface 211 and the side slope 212 constitute a first surface.
In this embodiment, the method further includes: a support layer 232, the support layer 232 being located in an insulating layer 221 and a control gate 260 over the first surface.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate;
etching a semiconductor substrate to form a slope substrate, wherein the slope substrate is provided with a top surface, a bottom surface and a slope surface connecting the top surface and the bottom surface;
forming a plurality of laminated composite layers on the slope substrate from bottom to top, wherein each composite layer comprises an insulating layer and a sacrificial layer positioned on the surface of the insulating layer, and the insulating layers are positioned between the two adjacent sacrificial layers and between the sacrificial layer and the slope substrate; forming a first dielectric layer covering the composite layer;
the bottom surface and the side slope form a first surface, a support through hole penetrating through the first dielectric layer and the composite layer is formed, and the support through hole is exposed out of the first surface;
forming a support layer in the support through hole;
flattening the first dielectric layer, the composite layer and the support layer until the top surface is exposed, and enabling the top surface of the composite layer above the slope surface to be flush with the top surface;
removing the sacrificial layer to form an opening;
a control gate is formed in the opening.
2. The method of claim 1, wherein the etching of the semiconductor substrate to form a sloped substrate comprises:
forming a first mask layer on the semiconductor substrate, wherein the surface of the semiconductor substrate covered by the first mask layer defines the position of the top surface;
and etching the semiconductor substrate by using the first mask layer as a mask and adopting an anisotropic dry etching process to form a slope substrate.
3. The method of claim 2, wherein the parameters of the anisotropic dry etching process are: the adopted gas comprises etching gas and buffer gas, wherein the etching gas is Cl2、Br2One or more of HCl and HBr, and the buffer gas is N2And Ar, wherein the flow rate of the etching gas is 100-200 sccm, the flow rate of the buffer gas is 100-200 sccm, the source radio frequency power is 500-1000W, the bias radio frequency power is 500-1000W, and the pressure of the chamber is 10-50 mtorr.
4. The method of claim 1, wherein the angle between the slope and the bottom surface is 120-150 degrees.
5. The method of claim 1, wherein the step of planarizing the first dielectric layer and the composite layer until the top surface is exposed is a chemical mechanical polishing process.
6. The method for forming a semiconductor device according to claim 1, wherein a material of the insulating layer is silicon oxide, silicon oxynitride, or silicon oxycarbide; the sacrificial layer is made of silicon nitride, amorphous carbon or polycrystalline silicon.
7. The method of claim 1, wherein the number of the composite layers is 2 to 256.
8. The method of claim 1, further comprising, after planarizing the first dielectric layer and composite layer until the top surface is exposed and before removing the sacrificial layer:
forming a trench via in the first dielectric layer and the composite layer over the bottom surface;
forming a channel layer in the channel via.
9. The method for forming a semiconductor device according to claim 1, further comprising:
forming a second dielectric layer covering the first dielectric layer, the control gate, the insulating layer and the slope substrate;
and forming a plurality of word line plug holes in the second dielectric layer, wherein the word line plug holes are respectively exposed out of the top surface of each layer of control gate above the slope surface.
10. The method according to claim 1, wherein the number of the support via holes is one or more.
11. The method of claim 1, wherein the support via exposes a bottom surface.
12. The method of claim 1, wherein the support via exposes the edge slope.
13. The method of claim 1, wherein when the number of the support vias is plural, a portion of the support vias exposes the bottom surface, and a portion of the support vias exposes the edge slope.
14. The method for forming a semiconductor device according to claim 1, wherein a material of the support layer is silicon oxide, silicon oxynitride, or silicon oxycarbide.
15. The method of claim 1, wherein the process of forming the support via comprises:
forming a second mask layer on the surface of the first medium layer, wherein the second mask layer is provided with a supporting through hole pattern opening, and the supporting through hole pattern opening defines the position of a supporting through hole;
etching the first dielectric layer and the composite layer by using the second mask layer as a mask through an anisotropic dry etching process until the first surface is exposed to form a support through hole;
and removing the second mask layer.
16. The method of claim 15, wherein the step of etching the first dielectric layer and the composite layer by an anisotropic dry etching process using the second mask layer as a mask until the first surface is exposed further comprises:
and continuously etching part of the slope substrate downwards by taking the second mask layer as a mask.
17. The method of claim 1, further comprising, prior to planarizing the first dielectric layer and composite layer until the top surface is exposed: forming a grinding blocking layer covering the first medium layer;
planarizing the polish stop layer while planarizing the first dielectric layer and the composite layer until the top surface is exposed.
18. The method of claim 17, wherein a polishing rate of the polish stop layer is less than a polishing rate of the first dielectric layer during the planarizing the first dielectric layer, the composite layer, and the polish stop layer until the top surface is exposed.
19. A semiconductor device formed according to any one of claims 1 to 18, comprising:
a side slope substrate having a top surface, a bottom surface, and a side slope connecting the top surface and the bottom surface, the bottom surface and the side slope constituting a first surface;
the control gates are positioned on the bottom surface and the side slope surface and are stacked from bottom to top;
the insulating layers are positioned between the slope substrate and the bottom control grid and between the adjacent control grids, are stacked from bottom to top, and are flush with the top surface of the control grid above the slope surface; the first dielectric layer is positioned on the control gate and the insulating layer and exposes out of the top surface of the control gate above the slope surface;
and the supporting layer is positioned on the first surface and penetrates through the control gates and the insulating layers.
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