CN107302001A - A kind of single tube single capacitor memory unit and preparation method thereof - Google Patents

Abstract

The invention discloses a kind of single tube single capacitor memory unit, including transistor and capacitance structure, the Top electrode of the capacitance structure is connected with the drain electrode of the transistor by lead.Single tube single capacitor memory unit of the present invention uses β Ga₂O₃As channel material, a kind of heat endurance and chemical stability all good semiconductor material with wide forbidden band, and it is expected there is extraordinary radiation resistance, the capability of resistance to radiation at raceway groove position can be reinforced.Meanwhile, the invention also discloses a kind of preparation method of single tube single capacitor memory unit and include the memory of the single tube single capacitor memory unit.

Description

A single-tube single-capacitance storage unit device and its preparation method

technical field

The invention relates to a storage unit device and a preparation method thereof, in particular to a single-tube single-capacitance storage unit device and a preparation method thereof.

Background technique

Semiconductor memory based on metal-oxide-semiconductor (MOS) technology is one of the most important types of integrated circuit products. Ferroelectric memory represents the development direction of electronic information products towards high density, high read and write speed, low power consumption, and low cost. It is recognized by academia and industry as one of the most promising next-generation memories. Since 2001, Ferroelectric memory is listed in ITRS (International Technology Roadmap for Semiconductors), a guiding plan for the semiconductor industry.

The storage unit of ferroelectric memory mainly has structures such as 1T-1C, 2T-2C, 1T, and chain FeRAM. A typical 1T-1C ferroelectric memory storage cell, which contains a transistor and a ferroelectric capacitor. Almost all 1T-1C ferroelectric memories are used in the current market. This type of memory reads data destructively. When the logic value is "1", the pulse used in the read operation of the ferroelectric capacitor is opposite to that of the write operation, so the polarization state of the ferroelectric film is reversed, which is a destructive read operation. After the amplifier outputs the signal, the ferroelectric capacitor should be rewritten to restore the destroyed polarization state. When the logic value is "0", the pulse signal used in the read operation is the same as that used in the write operation, and the polarization state of the ferroelectric film remains unchanged. Therefore, this operation is non-destructive and no restorative write operation is necessary.

Ferroelectric memories using ferroelectric thin film materials as storage media have better radiation resistance. However, the ferroelectric memory contains an array of Si field effect transistors, and its overall radiation resistance is limited by the radiation resistance of the Si field effect transistors. In order to prolong the service life of ferroelectric memory in space radiation environment, it is necessary to strengthen the radiation resistance of Si field effect transistor in ferroelectric memory. Compared with the first-generation semiconductor material Si, the second-generation and third-generation semiconductor materials generally have larger atomic displacement threshold energy and forbidden band width, so they have better radiation resistance and temperature stability. Therefore, in recent years, the integration of ferroelectric thin film materials with second-generation and third-generation semiconductor materials such as GaAs, SiC, GaN and diamond has attracted great attention from researchers in the ferroelectric field.

Contents of the invention

Based on this, the object of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a single-transistor single-capacitance storage unit device with good radiation resistance.

In order to achieve the above object, the technical solution adopted by the present invention is: a single-tube single-capacitance storage unit device, including a transistor and a capacitor structure, and the transistor includes:

Substrate;

isolation layers independently formed in at least two partial regions on the substrate;

a channel layer located between two adjacent isolation layers on the substrate;

The source and the drain are formed on the channel layer, the source and the drain are symmetrically located in the channel

Both sides on the road layer;

a transistor dielectric layer on the channel layer and between the source and the drain;

a gate electrode formed on the dielectric layer of the transistor;

a first transistor protection layer covering the transistor dielectric layer and the gate electrode;

The capacitor structure includes:

a second transistor protection layer formed on the isolation layer;

A lower electrode formed on the second transistor protection layer; a capacitive dielectric layer formed in a local area on the lower electrode; an upper electrode formed on the capacitive dielectric layer; formed on the upper electrode and covering the entire A capacitive protective layer of the capacitive structure; the upper electrode of the capacitive structure is connected with the drain of the transistor through a wire.

Preferably, the channel layer is composed of β-Ga ₂ O ₃ material, and the channel layer is also doped with tin, and the doping concentration of the tin is 10 ¹⁵ -10 ¹⁶ cm ^-3 . The use of β _{- Ga2O3} as the channel material provides a guarantee for the improvement of the radiation resistance and temperature stability of FeFET. β-Ga2O3, as a wide bandgap semiconductor material with good thermal and chemical stability, is expected to have very good radiation resistance, larger bandgap width and higher Baliga quality factor than SiC and GaN ( BFOM) value and cheaper price, using β-Ga2O3 as channel material can improve the overall radiation resistance and temperature stability of ferroelectric thin film FeFET.

Preferably, the ratio of the length to the width of the channel layer is (20-30):(80-100).

Preferably, the substrate is made of silicon material or germanium material.

Preferably, the isolation layer has a thickness of 150nm-300nm, and the channel layer has a thickness of 200nm-300nm.

Preferably, the transistor dielectric layer is composed of a hafnium-based dielectric material, and the thickness of the transistor dielectric layer is 2nm˜10nm.

Preferably, the gate electrode has a thickness of 20nm-50nm, and the transistor protection layer has a thickness of 200nm-300nm.

Preferably, the capacitive protection layer is made of silicon nitride material or silicon oxide material, and the thickness of the capacitive protective layer is 280nm-400nm.

Preferably, it also includes a wiring layer respectively formed on the upper electrode, the lower electrode, the source electrode and the drain electrode, the wiring layer is composed of Al, and the thickness of the wiring layer is 500nm-700nm .

Preferably, the gate electrode, the upper electrode and the lower electrode are all electrodes composed of TaN, TiN, HfN, Al or Au.

More preferably, the thickness of the gate electrode is 20nm˜50nm.

Preferably, the material of the capacitor dielectric layer is at least one of Bi ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ , PbTiO ₃ , BaTiO ₃ , BiFeO ₃ , or La, Nd, Ce, Sr, Zr, A substance formed by doping at least one of Mn, W, and Na with at least one of Bi ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ , PbTiO ₃ , BaTiO ₃ , and BiFeO ₃ , or Zr-doped HfO ₂ , Si-doped HfO ₂ , Al-doped HfO ₂ , and Y-doped HfO ₂ .

More preferably, the thickness of the capacitor dielectric layer is 5nm-600nm.

At the same time, the present invention also provides a memory comprising the above-mentioned single-transistor single-capacitance storage unit device.

In addition, the present invention also provides a method for preparing the above-mentioned single-tube single-capacitance storage unit, including the following steps:

(1) Separately form isolation layers in at least two partial regions on the substrate;

(2) forming a channel layer on the substrate processed in step (1) and between two adjacent isolation layers;

(3) forming a source electrode and a drain electrode on the channel layer formed in step (2);

(4) forming a transistor dielectric layer between the source and drain on the channel layer processed in step (3), depositing gate metal on the transistor dielectric layer to obtain a gate electrode;

(5) Depositing a first transistor protection layer covering the transistor dielectric layer and gate electrode, and depositing a second transistor protection layer on the isolation layer;

(6) Form a lower electrode on the second transistor protective layer in step (5); form a capacitor dielectric layer in a local area on the lower electrode; form an upper electrode on the capacitor dielectric layer; Form a capacitive protection layer covering the entire capacitive structure;

(7) Forming a wiring layer on the upper electrode, lower electrode, source electrode and drain electrode treated in step (6), to obtain the single-transistor single-capacitance storage unit device.

Preferably, in the step (1), a thermal oxidation process is used to form the isolation layer.

Preferably, in the step (2), a channel layer is epitaxially grown on the substrate by using a low-temperature solid-source molecular beam epitaxy process, the epitaxy temperature is 500° C. to 700° C., and the deposition rate is 0.6 μm/h.

Preferably, the forming process of the source and drain in the step (3) includes: forming a window by using a photolithography process, forming a source layer and a drain layer on the channel layer, and then forming a source region by doping, In the drain region, an ion implantation process is used to perform ion implantation on the source layer and the drain layer, remove glue, and activate to obtain the source electrode and the drain electrode.

More preferably, the conditions of the above-mentioned ion implantation process are: Si ⁺ ions are implanted in the N ⁺ -type source region and the N ⁺ -type drain region with an energy of 20-30KeV and a dose of 10 ¹⁸ -10 ¹⁹ cm ^-3 .

More preferably, the above-mentioned activation treatment process is: performing thermal annealing treatment on the source region and the drain region at 800° C. to 950° C. for 25 minutes to 35 minutes.

Preferably, the above photolithography process adopts a 365nm I-line photolithography process. Those skilled in the art can select a suitable etching formula according to needs.

Preferably, the formation of the transistor dielectric layer in the step (4) adopts an atomic layer deposition process or a pulsed laser deposition process, and the formation of the gate electrode adopts a magnetron sputtering process or a thermal evaporation process.

Preferably, in the step (4), a transistor dielectric layer is first deposited on the channel layer, and a gate electrode is deposited on the transistor dielectric layer; then a window is formed by photolithography, and the insulation on the source electrode and the drain electrode is removed by etching Layer and gate electrode, and then remove the glue.

Preferably, in the step (5) and step (6), the transistor protective layer and the capacitor protective layer are deposited by plasma enhanced chemical vapor deposition, and the process temperature is 100°C-300°C.

Preferably, in the step (6), the lower electrode is deposited using a magnetron sputtering process or a thermal evaporation process, and then an atomic layer deposition process or a pulsed laser deposition process is used to deposit a ferroelectric capacitor dielectric layer on the lower electrode, Finally, an upper electrode is deposited on the ferroelectric capacitor dielectric layer by using a magnetron sputtering process or a thermal evaporation process.

Preferably, the preparation process of the lead layer in the step (7) is: forming a window by photolithography, etching the isolation protective layer pattern on the ferroelectric upper electrode, lower electrode, source electrode and drain electrode, and forming a lead hole; The lead layer is formed through thermal evaporation process; the aluminum lead pattern is photoetched by photolithography process, the aluminum lead to be retained is protected with photoresist, and the pattern lead is etched by etching.

Compared with the prior art, the beneficial effects of the present invention are:

The single-tube single-capacitance storage unit device of the present invention uses β-Ga ₂ O ₃ as the channel material, a wide bandgap semiconductor material with good thermal stability and chemical stability, and is expected to have very good radiation resistance performance, which can Reinforce the radiation resistance of the channel part.

Description of drawings

Fig. 1 is a kind of cross-sectional structure diagram of single-tube single-capacitance storage unit device described in the present invention;

Fig. 2 is a kind of flowchart of the manufacturing method of single-tube single-capacitance storage unit device described in the present invention;

Among them, 1. Substrate; 2. Isolation layer; 3. Channel layer; 4. Source; 5. Transistor dielectric layer; 6. Gate electrode; 7. First transistor protection layer; 8. Drain; 9. Capacitance protective layer; 10, upper electrode; 11, capacitor dielectric layer; 12, lower electrode; 13, lead layer; 14, second transistor protective layer.

detailed description

In order to better illustrate the purpose, technical solutions and advantages of the present invention, the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

Example 1

An embodiment of the single-tube single-capacitance storage unit device of the present invention, a cross-sectional structure diagram of the single-tube single-capacitance storage unit device described in this embodiment is shown in Figure 1, including:

a substrate 1, the substrate 1 is composed of a silicon material;

Two isolation layers 2 are independently formed in at least two partial regions on the substrate 1, and the thickness of the isolation layers 2 is 200nm;

The channel layer 3 located between two adjacent isolation layers 2 on the substrate 1, the thickness of the channel layer 3 is 300nm, the channel layer ₃ is composed of β- _Ga2O3 material, and the channel layer 3 is also Doped with tin, the doping concentration of tin is 10 ¹⁵ cm ^-3 ;

The source electrode 4 and the drain electrode 8 formed on the channel layer 3, the source electrode 4 and the drain electrode 8 are symmetrically formed on both sides of the channel layer 3;

A transistor dielectric layer 5 formed on the channel layer 3 and between the source 4 and the drain 8, the transistor dielectric layer 5 is composed of a hafnium-based dielectric material, and the thickness of the transistor dielectric layer 5 is 5 nm;

A gate electrode 6 formed on the transistor dielectric layer 5, the thickness of the gate electrode 6 is 20nm;

A first transistor protective layer 7 covering the transistor dielectric layer 5 and the gate electrode 6, the thickness of the transistor protective layer 7 is 300nm;

The capacitor structure includes:

The second transistor protective layer 14 formed on the isolation layer 2; the lower electrode 12 formed on the second transistor protective layer 14; the capacitor dielectric layer 11 formed in a local area on the lower electrode 12, the material of the capacitor dielectric layer 11 is Zr doped Doped HfO ₂ , the thickness of the capacitor dielectric layer 11 is 10nm;

The upper electrode 10 formed on the capacitor dielectric layer 11;

A capacitance protection layer 9 formed on the upper electrode 10 and covering the entire capacitance structure, the capacitance protection layer 9 is made of silicon nitride material, and the thickness of the capacitance protection layer 9 is 300nm;

The lead layer 13 formed on the upper electrode 10, the lower electrode 12, the source electrode 4 and the drain electrode 8, the lead layer 13 is composed of Al, the thickness of the lead layer 13 is 600nm, the upper electrode 10 of the capacitor structure and the drain electrode 8 of the transistor connected by leads.

The present embodiment is a memory including the above-mentioned single-transistor single-capacitance storage unit device.

In this embodiment, a method for preparing the above-mentioned single-tube single-capacitance storage unit device includes the following steps:

Step 1, initial oxidation:

After a thermal oxidation process, a field oxygen isolation layer is formed in the local window formed by photolithography, and the thickness of the field oxygen is 200nm. Figure 2(a) is a schematic diagram of the result after initial oxidation.

Step 2. Epitaxial growth of β-Ga ₂ O ₃ layer:

Using the low-temperature solid-source molecular beam epitaxy process, a layer of β-Ga2O3 layer channel is epitaxially grown on the substrate with a thickness of 300nm, the epitaxial temperature is 500°C, and the deposition rate is 0.6μm/h. Figure 2(b) shows the epitaxial growth Schematic diagram of the result after the β-Ga2O3 layer.

Step 3, photolithography to form the active layer and source and drain electrode regions:

The window is formed by photolithography, and the source, drain and channel are formed on the β-Ga2O3 layer. The channel is located in the center of the β-Ga2O3 layer, and the source and drain are located on both sides of the channel. The length of the channel is The width ratio is 20nm/100nm, and then the source region and the drain region are formed by doping, and then the source layer and the drain layer are implanted with Si ions by ion implantation process, the implantation energy is 25KeV, and the dose is 10 ¹⁹ cm ^{- 3.} Form the source and drain, remove glue, and finally activate: thermally anneal the source and drain at 950°C for 30 minutes for activation to obtain the source and drain. Figure 2(c) shows the formation of the source and drain electrodes The schematic diagram of the result.

Step 4, depositing transistor insulating layer and gate electrode:

Using the atomic layer deposition process, under the environment of temperature 260 ℃ and pressure 12hPa, the transistor dielectric layer HfO ₂ 5nm is deposited on the β-Ga2O3 layer prepared in the active region in step (3), and then the magnetron Sputtering process, at a temperature of 300°C, a pressure of 0.28Pa, and a sputtering power of 112W, the gate electrode TiN20nm is deposited on the dielectric layer of the deposition transistor. Figure 2(d) shows the deposition of the transistor insulating layer and gate electrode The schematic diagram of the result.

Step 5, photolithography and etching:

Form a window by photolithography, etch to remove the insulating layer/TiN on the part other than the gate electrode area, and then remove the glue. Figure 2(e) is a schematic diagram of the result after etching the gate electrode and patterning it.

Step 6, depositing transistor protection layer:

Utilize the plasma chemical vapor phase process, on the transistor structure formed in step (5), deposit and form the transistor protection layer of depositing phospho-silicate glass 300nm, process temperature 300 ℃, Fig. 2 (f) is the deposition transistor protection layer Schematic diagram of the result.

Step 7. Lead hole photolithography:

A lead hole is formed by using a photolithography process, and FIG. 2( g ) is a schematic diagram of the result after depositing a transistor protection layer and forming a lead hole by photolithography.

Step 8, depositing the lower electrode of the ferroelectric capacitor, the dielectric layer of the ferroelectric capacitor and the upper electrode of the ferroelectric capacitor:

Using the magnetron sputtering process, deposit the lower electrode on the protective layer of the phosphosilicate glass transistor deposited in step (6), and then use the atomic layer deposition process, under the environment where the temperature is 280 ° C and the pressure is 15 hPa, the lower electrode is deposited on the lower electrode. Deposit ferroelectric Zr-doped _HfO2 ferroelectric capacitive dielectric layer 10nm on the electrode, and finally use magnetron sputtering process, under the conditions of temperature 300 ℃, pressure 0.28Pa, sputtering power 112W, ferroelectric Zr doped The upper electrode TiN 20nm is deposited on the doped HfO ₂ ferroelectric capacitor dielectric layer, and Fig. 2(h) is a schematic diagram of the result after depositing the ferroelectric capacitor lower electrode, the ferroelectric capacitor dielectric layer and the ferroelectric capacitor upper electrode.

Step 9, photolithography and etching:

Use photolithography to form windows, etch to form the pattern of the upper electrode and capacitor dielectric layer, and then remove the glue. Figure 2 (i) is a schematic diagram of the result of etching and patterning the ferroelectric capacitor dielectric layer and the ferroelectric capacitor upper electrode.

Step 10, photolithography and etching:

The window is formed by photolithography, the pattern of the lower electrode is formed by etching, and then the glue is removed. Fig. 2(j) is a schematic diagram of the result after etching and patterning of the lower electrode of the ferroelectric capacitor.

Step 11, depositing a ferroelectric capacitance isolation protective layer:

Using the plasma enhanced chemical vapor deposition method, the ferroelectric capacitor structure formed in the step is deposited with a silicon nitride ferroelectric capacitor isolation protection layer of 300nm, and the process temperature is 300°C. Figure 2(k) is the deposition of the ferroelectric capacitor isolation protection layer. Schematic diagram of the result.

Step 12. Lithographic lead hole:

Use photolithography to form a window, etch the silicon nitride ferroelectric capacitor isolation protection layer pattern on the ferroelectric upper electrode, lower electrode, source and drain to form a lead hole. Figure 2 (l) is after the photoetched lead hole The schematic diagram of the result.

Step 13, steam aluminum:

Through the thermal evaporation process, a 600nm wiring layer is formed, and Fig. 2(m) is a schematic diagram of the result after aluminum evaporation.

Step 14. Anti-engraving aluminum:

Using the photolithography process, the pattern of the aluminum lead is photoetched, and the aluminum lead to be retained is protected with photoresist, and then the pattern lead is etched to complete the preparation of the single-tube single-capacitance storage unit. Figure 2 (n) is Zr-doped Schematic diagram of the fabricated HfO ₂ ferroelectric single-tube single-capacitance storage unit.

Example 2

An embodiment of the single-tube single-capacitance storage unit device of the present invention, a cross-sectional structure diagram of the single-tube single-capacitance storage unit device described in this embodiment is shown in Figure 1, including:

A substrate 1, the substrate 1 is composed of a germanium material;

two isolation layers 2 independently formed on at least two partial regions on the substrate 1, the thickness of the isolation layer 2 is 300nm;

The channel layer 3 located between two adjacent isolation layers 2 on the substrate 1, the thickness of the channel layer 3 is 250nm, the channel layer ₃ is composed of β- _Ga2O3 material, and the channel layer 3 is also Doped with tin, the doping concentration of tin is 10 ¹⁶ cm ^-3 ;

The source electrode 4 and the drain electrode 8 formed on the channel layer 3, the source electrode 4 and the drain electrode 8 are symmetrically formed on both sides of the channel layer 3;

A transistor dielectric layer 5 formed on the channel layer 3 and between the source 4 and the drain 8, the transistor dielectric layer 5 is composed of a hafnium-based dielectric material, and the thickness of the transistor dielectric layer 5 is 2nm;

A gate electrode 6 formed on the transistor dielectric layer 5, the thickness of the gate electrode 6 is 20nm;

A first transistor protective layer 7 covering the transistor dielectric layer 5 and the gate electrode 6, the thickness of the transistor protective layer 7 is 280nm;

The capacitor structure includes:

The second transistor protective layer 14 formed on the isolation layer 2; the lower electrode 12 formed on the second transistor protective layer 14; the capacitor dielectric layer 11 formed in a local area on the lower electrode 12, the material of the capacitor dielectric layer 11 is Al-doped Doped HfO ₂ , the thickness of the capacitor dielectric layer 11 is 5nm;

The upper electrode 10 formed on the capacitor dielectric layer 11;

A capacitance protection layer 9 formed on the upper electrode 10 and covering the entire capacitance structure, the capacitance protection layer 9 is made of silicon oxide material, and the thickness of the capacitance protection layer 9 is 400nm;

The wiring layer 13 formed on the upper electrode 10, the lower electrode 12, the source electrode 4 and the drain electrode 8, the wiring layer 13 is composed of Al, the thickness of the wiring layer 13 is 500nm, the upper electrode 10 of the capacitor structure and the drain electrode 8 of the transistor pass through lead wire connection.

The present embodiment is a memory including the above-mentioned single-transistor single-capacitance storage unit device.

In this embodiment, a method for preparing the above-mentioned single-tube single-capacitance storage unit device includes the following steps:

Step 1, initial oxidation:

After a thermal oxidation process, a field oxygen isolation layer is formed in the local area window formed by photolithography, and the thickness of the field oxygen is 300nm. Figure 2(a) is a schematic diagram of the result after the initial oxidation.

Step 2. Epitaxial growth of β-Ga2O3 layer:

Using the low-temperature solid-source molecular beam epitaxy process, a layer of β-Ga2O3 layer channel is epitaxially grown on the substrate, with a thickness of 250nm, an epitaxial temperature of 700°C, and a deposition rate of 0.6μm/h. Figure 2(b) shows the epitaxial growth Schematic diagram of the result after the β-Ga2O3 layer.

Step 3, photolithography to form the active layer and source and drain electrode regions:

The window is formed by photolithography, and the source, drain and channel are formed on the β-Ga2O3 layer. The channel is located in the center of the β-Ga2O3 layer, and the source and drain are located on both sides of the channel. The length of the channel is The width ratio is 30nm/80nm, and then the source region and the drain region are formed by doping, and then the source layer and the drain layer are implanted with Si ions by ion implantation process, the implantation energy is 30KeV, and the dose is 10 ¹⁹ cm ^{- 3.} Form the source and drain, remove glue, and finally activate: thermally anneal the source and drain (8) for 35 minutes at 800°C for activation to obtain the source and drain. Figure 2(c) is the source Schematic diagram of the result after drain electrode formation.

Step 4, depositing transistor insulating layer and gate electrode:

Using the atomic layer deposition process, the transistor dielectric layer Al ₂ O ₃ 2nm is deposited on the β-Ga2O3 layer prepared in the active region in step (3) under an environment with a temperature of 260°C and a pressure of 12hPa, and then uses a magnetic Controlled sputtering process, under the conditions of temperature 300°C, pressure 0.28Pa, and sputtering power 112W, the gate electrode TaN20nm is deposited on the dielectric layer of the deposition transistor. Figure 2(d) shows the deposition of the transistor insulating layer and Schematic diagram of the result after the gate electrode.

Step 5, photolithography and etching:

Form a window by photolithography, etch to remove the insulating layer/TaN on the part other than the gate electrode area, and then remove the glue. Figure 2(e) is a schematic diagram of the result after etching the gate electrode and patterning it.

Step 6, depositing transistor protection layer:

Utilize the plasma chemical vapor phase process, on the transistor structure formed in step (5), deposit and form the transistor protection layer of depositing phospho-silicate glass 280nm, process temperature 100 ℃, Fig. 2 (f) is the deposition transistor protection layer Schematic diagram of the result.

Step 7. Lead hole photolithography:

A lead hole is formed by using a photolithography process, and FIG. 2( g ) is a schematic diagram of the result after depositing a transistor protection layer and forming a lead hole by photolithography.

Step 8, depositing the lower electrode of the ferroelectric capacitor, the dielectric layer of the ferroelectric capacitor and the upper electrode of the ferroelectric capacitor:

Using the magnetron sputtering process, deposit the lower electrode on the protective layer of the phosphosilicate glass transistor deposited in step (6), and then use the atomic layer deposition process, at a temperature of 280 ° C and a pressure of 15 hPa, in the lower electrode Deposit ferroelectric Al-doped _HfO2 ferroelectric capacitor dielectric layer 5nm on the electrode, utilize magnetron sputtering process to deposit upper electrode TaN 20nm on the ferroelectric Al-doped _HfO2 ferroelectric capacitor dielectric layer at last, Fig. 2 ( h) is a schematic diagram of the result after depositing the lower electrode of the ferroelectric capacitor, the dielectric layer of the ferroelectric capacitor and the upper electrode of the ferroelectric capacitor.

Step 9, photolithography and etching:

Use photolithography to form windows, etch to form the pattern of the upper electrode and capacitor dielectric layer, and then remove the glue. Figure 2 (i) is a schematic diagram of the result of etching and patterning the ferroelectric capacitor dielectric layer and the ferroelectric capacitor upper electrode.

Step 10, photolithography and etching:

The window is formed by photolithography, the pattern of the lower electrode is formed by etching, and then the glue is removed. Fig. 2(j) is a schematic diagram of the result after etching and patterning of the lower electrode of the ferroelectric capacitor.

Step 11, depositing a ferroelectric capacitance isolation protective layer:

Using the plasma enhanced chemical vapor deposition method, the ferroelectric capacitive structure formed in the step is deposited with a silicon oxide ferroelectric capacitive isolation protection layer of 400nm, and the process temperature is 200°C. The schematic diagram of the result.

Step 12. Lithographic lead hole:

Use photolithography to form a window, etch the silicon nitride ferroelectric capacitor isolation protection layer pattern on the ferroelectric upper electrode, lower electrode, source and drain to form a lead hole. Figure 2 (l) is after the photoetched lead hole The schematic diagram of the result.

Step 13, steam aluminum:

Through the thermal evaporation process, a 500nm wiring layer is formed, and FIG. 2(m) is a schematic diagram of the result after aluminum evaporation.

Step 14. Anti-engraving aluminum:

Using the photolithography process, the pattern of the aluminum lead wire is photoetched, the aluminum lead wire to be retained is protected with photoresist, and then the pattern lead wire is etched out to complete the preparation of the single-tube single-capacitance storage unit. Schematic diagram of the fabricated HfO ₂ ferroelectric single-tube single-capacitance storage unit.

Example 3

An embodiment of the single-tube single-capacitance storage unit device of the present invention, a cross-sectional structure diagram of the single-tube single-capacitance storage unit device described in this embodiment is shown in Figure 1, including:

a substrate 1, the substrate 1 is composed of a silicon material;

Two isolation layers 2 are independently formed in at least two partial regions on the substrate 1, and the thickness of the isolation layers 2 is 250 nm;

The channel layer 3 located between two adjacent isolation layers 2 on the substrate 1, the thickness of the channel layer 3 is 280nm, the channel layer 3 is composed of β-Ga ₂ O ₃ material, and the channel layer 3 is also Doped with tin, the doping concentration of tin is 10 ¹⁵ cm ^-3 ;

The source electrode 4 and the drain electrode 8 formed on the channel layer 3, the source electrode 4 and the drain electrode 8 are symmetrically formed on both sides of the channel layer 3;

A transistor dielectric layer 5 formed on the channel layer 3 and between the source 4 and the drain 8, the transistor dielectric layer 5 is composed of a hafnium-based dielectric material, and the thickness of the transistor dielectric layer 5 is 5 nm;

A gate electrode 6 formed on the transistor dielectric layer 5, the thickness of the gate electrode 6 is 35nm;

A first transistor protection layer 7 covering the transistor dielectric layer 5 and the gate electrode 6, the thickness of the transistor protection layer 7 is 200nm;

The capacitor structure includes:

The second transistor protective layer 14 formed on the isolation layer 2; the lower electrode 12 formed on the second transistor protective layer 14; the capacitor dielectric layer 11 formed in a local area on the lower electrode 12, the material of the capacitor dielectric layer 11 is Zr and _The substance formed by doping PbTiO3, the thickness of the capacitor dielectric layer 11 is 600nm;

The upper electrode 10 formed on the capacitor dielectric layer 11;

A capacitance protection layer 9 formed on the upper electrode 10 and covering the entire capacitance structure, the capacitance protection layer 9 is made of silicon nitride material, and the thickness of the capacitance protection layer 9 is 280nm;

The lead layer 13 formed on the upper electrode 10, the lower electrode 12, the source electrode 4 and the drain electrode 8, the lead layer 13 is composed of Al, the thickness of the lead layer 13 is 700nm, the upper electrode 10 of the capacitor structure and the drain electrode 8 of the transistor pass through lead wire connection.

The present embodiment is a memory including the above-mentioned single-transistor single-capacitance storage unit device.

In this embodiment, a method for preparing the above-mentioned single-tube single-capacitance storage unit device includes the following steps:

Step 1, initial oxidation:

After a thermal oxidation process, a field oxygen isolation layer is formed in the local window formed by photolithography, and the thickness of the field oxygen is 250nm. Figure 2(a) is a schematic diagram of the result after initial oxidation.

Step 2. Epitaxial growth of β-Ga2O3 layer:

Using the low-temperature solid-source molecular beam epitaxy process, a layer of β-Ga2O3 layer channel is epitaxially grown on the substrate with a thickness of 280nm, the epitaxial temperature is 600°C, and the deposition rate is 0.6μm/h. Figure 2(b) shows the epitaxial growth Schematic diagram of the result after the β-Ga2O3 layer.

Step 3, photolithography to form the active layer and source and drain electrode regions:

The window is formed by photolithography, and the source, drain and channel are formed on the β-Ga2O3 layer. The channel is located in the center of the β-Ga2O3 layer, and the source and drain are located on both sides of the channel. The length of the channel is The width ratio is 30nm/100nm, and then the source region and the drain region are formed by doping, and then the source layer and the drain layer are implanted with Si ions by ion implantation process, the implantation energy is 20KeV, and the dose is 10 ¹⁹ cm ^{- 3.} Form the source and drain, remove glue, and finally activate: thermally anneal the source and drain (8) at 900°C for 30 minutes for activation to obtain the source and drain. Figure 2(c) shows the source Schematic diagram of the result after drain electrode formation.

Step 4, depositing transistor insulating layer and gate electrode:

Using the atomic layer deposition process, under the environment of the temperature of 250 °C and the pressure of 10hPa, the transistor dielectric layer HfAlO 5nm is deposited on the β-Ga2O3 layer prepared in the active region in step (3), and then magnetron sputtering Sputtering process, at a temperature of 280°C, a pressure of 0.32Pa, and a sputtering power of 130W, the gate electrode TaN35nm was deposited on the dielectric layer of the deposition transistor. Figure 2(d) shows the deposition of the transistor insulating layer and gate electrode The schematic diagram of the result.

Step 5, photolithography and etching:

Form a window by photolithography, etch to remove the insulating layer/TaN on the part other than the gate electrode area, and then remove the glue. Figure 2(e) is a schematic diagram of the result after etching the gate electrode and patterning it.

Step 6, depositing transistor protection layer:

Utilize the plasma chemical vapor phase process, on the transistor structure formed in step (5), deposit and form the transistor protection layer of depositing phospho-silicate glass 200nm, process temperature 300 ℃, Fig. 2 (f) is the deposition transistor protection layer Schematic diagram of the result.

Step 7. Lead hole photolithography:

A lead hole is formed by using a photolithography process, and FIG. 2( g ) is a schematic diagram of the result after depositing a transistor protection layer and forming a lead hole by photolithography.

Step 8, depositing the lower electrode of the ferroelectric capacitor, the dielectric layer of the ferroelectric capacitor and the upper electrode of the ferroelectric capacitor:

Utilize the ultra-high vacuum electron beam evaporation method, deposit the lower electrode Pt on the top of the phospho-silicate glass transistor protective layer in step (6), with a thickness of 40nm, utilize pulsed laser deposition technology, single pulse energy 300mJ, make the energy of the laser pulse The density is 2J/cm ² , the laser repetition frequency is 10Hz, the oxygen pressure is 100mTorr, the deposition temperature is 700°C, and the thickness is 600nm. Pb(Zr _0.53 Ti _0.47 )O ₃ ferroelectric thin film is deposited. Method and preparation process Deposit the upper electrode Pt on the ferroelectric Pb(Zr _0.53 Ti _0.47 )O ₃ ferroelectric capacitor dielectric layer with a thickness of 40nm. Figure 2(h) shows the deposited ferroelectric capacitor lower electrode and ferroelectric capacitor dielectric Schematic diagram of the result after electrodes are placed on the layer and ferroelectric capacitor.

Step 9, photolithography and etching:

Use photolithography to form a window, etch to form the pattern of the upper electrode and the capacitor dielectric layer, and then remove the glue. Figure 2 (i) is a schematic diagram of the result of etching and patterning the ferroelectric capacitor dielectric layer and the ferroelectric capacitor upper electrode.

Step 10, photolithography and etching:

The window is formed by photolithography, the pattern of the lower electrode is formed by etching, and then the glue is removed. Fig. 2(j) is a schematic diagram of the result after etching and patterning of the lower electrode of the ferroelectric capacitor.

Step 11, depositing a ferroelectric capacitance isolation protection layer:

Using the plasma enhanced chemical vapor deposition method, the ferroelectric capacitor structure formed in the step is deposited with a silicon nitride ferroelectric capacitor isolation protective layer of 280nm, and the process temperature is 100°C. Figure 2(k) is the deposition of the ferroelectric capacitor isolation protective layer. Schematic diagram of the result.

Step 12. Lithographic lead hole:

Use photolithography to form a window, etch the silicon nitride ferroelectric capacitor isolation protection layer pattern on the ferroelectric upper electrode, lower electrode, source and drain to form a lead hole. Figure 2 (l) is after the photoetched lead hole The schematic diagram of the result.

Step 13, steam aluminum:

Through the thermal evaporation process, a 700nm wiring layer is formed, and Fig. 2(m) is a schematic diagram of the result after aluminum evaporation.

Step 14. Anti-engraving aluminum:

Utilize the photolithography process, photolithographically pattern the aluminum leads, protect the aluminum leads to be retained with photoresist, and then etch the pattern leads to complete the preparation of the single-tube single-capacitance storage unit. Figure 2(n) shows the Pb(Zr _0.53 Ti _0.47 )O ₃ ferroelectric single-tube single-capacitance memory cell fabricated results schematic diagram.

Example 4

An embodiment of the single-tube single-capacitance storage unit device of the present invention, a cross-sectional structure diagram of the single-tube single-capacitance storage unit device described in this embodiment is shown in Figure 1, including:

A substrate 1, the substrate 1 is composed of a germanium material;

Two isolation layers 2 are independently formed in at least two partial regions on the substrate 1, and the thickness of the isolation layers 2 is 150 nm;

The channel layer 3 located between two adjacent isolation layers 2 on the substrate 1, the thickness of the channel layer 3 is 200nm, the channel layer 3 is composed of β-Ga ₂ O ₃ material, and the channel layer 3 is also Doped with tin, the doping concentration of tin is 10 ¹⁶ cm ^-3 ;

The source electrode 4 and the drain electrode 8 formed on the channel layer 3, the source electrode 4 and the drain electrode 8 are symmetrically formed on both sides of the channel layer 3;

A transistor dielectric layer 5 formed on the channel layer 3 and between the source 4 and the drain 8, the transistor dielectric layer 5 is composed of a hafnium-based dielectric material, and the thickness of the transistor dielectric layer 5 is 10 nm;

A gate electrode 6 formed on the transistor dielectric layer 5, the thickness of the gate electrode 6 is 50nm;

A first transistor protective layer 7 covering the transistor dielectric layer 5 and the gate electrode 6, the thickness of the transistor protective layer 7 is 300nm;

The capacitor structure includes:

The second transistor protective layer 14 formed on the isolation layer 2; the lower electrode 12 formed on the second transistor protective layer 14; the capacitor dielectric layer 11 formed in a local area on the lower electrode 12, the material of the capacitor dielectric layer 11 is Nd and A substance formed by doping Bi ₄ Ti ₃ O ₁₂ , the thickness of the capacitor dielectric layer 11 is 320nm;

The upper electrode 10 formed on the capacitor dielectric layer 11;

A capacitance protection layer 9 formed on the upper electrode 10 and covering the entire capacitance structure, the capacitance protection layer 9 is made of silicon nitride material, and the thickness of the capacitance protection layer 9 is 280nm;

The wiring layer 13 formed on the upper electrode 10, the lower electrode 12, the source electrode 4 and the drain electrode 8, the wiring layer 13 is composed of Al, the thickness of the wiring layer 13 is 500nm, the upper electrode 10 of the capacitor structure and the drain electrode 8 of the transistor connected by leads.

The present embodiment is a memory including the above-mentioned single-transistor single-capacitance storage unit device.

In this embodiment, a method for preparing the above-mentioned single-tube single-capacitance storage unit device includes the following steps:

Step 1, initial oxidation:

After a thermal oxidation process, a field oxygen isolation layer is formed in the local area window formed by photolithography, and the thickness of the field oxygen is 150nm. Figure 2(a) is a schematic diagram of the result after initial oxidation.

Step 2. Epitaxial growth of β-Ga2O3 layer:

Using the low-temperature solid-source molecular beam epitaxy process, a layer of β-Ga2O3 layer channel is epitaxially grown on the substrate, with a thickness of 200nm, an epitaxial temperature of 500°C, and a deposition rate of 0.6μm/h. Figure 2(b) shows the epitaxial growth Schematic diagram of the result after the β-Ga2O3 layer.

Step 3, photolithography to form the active layer and source and drain electrode regions:

The window is formed by photolithography, and the source, drain and channel are formed on the β-Ga2O3 layer. The channel is located in the center of the β-Ga2O3 layer, and the source and drain are located on both sides of the channel. The length of the channel is The width ratio is 30nm/100nm, and then the source region and the drain region are formed by doping, and then the source layer and the drain layer are implanted with Si ions by ion implantation process, the implantation energy is 20KeV, and the dose is 10 ¹⁸ cm ^{- 3.} Form the source and drain, remove glue, and finally activate: thermally anneal the source and drain (8) at 800°C for 25 minutes for activation to obtain the source and drain. Figure 2(c) shows the source Schematic diagram of the result after drain electrode formation.

Step 4, depositing transistor insulating layer and gate electrode:

Utilize the atomic layer deposition process, under the environment that the temperature is 250 ℃, the pressure is 10hPa, on the β-Ga ₂ O ₃ layer that the active region is prepared in step (3), deposit the transistor dielectric layer HfAlO 10nm, reuse Magnetron sputtering process, at a temperature of 280°C, a pressure of 0.32Pa, and a sputtering power of 130W, the gate electrode TaN50nm is deposited on the dielectric layer of the deposition transistor. Figure 2(d) shows the deposition of the insulating layer of the transistor and the schematic diagram of the result after the gate electrode.

Step 5, photolithography and etching:

Form a window by photolithography, etch to remove the insulating layer/TaN on the part other than the gate electrode area, and then remove the glue. Figure 2(e) is a schematic diagram of the result after etching the gate electrode and patterning it.

Step 6, depositing transistor protection layer:

Utilize the plasma chemical vapor process, on the transistor structure formed in step (5), deposit and form the protective layer of phospho-silicate glass transistor of 300nm, process temperature 200 ℃, Fig. 2 (f) is deposited transistor protective layer Schematic diagram of the result.

Step 7. Lead hole photolithography:

A lead hole is formed by using a photolithography process, and FIG. 2( g ) is a schematic diagram of the result after depositing a transistor protection layer and forming a lead hole by photolithography.

Step 8, depositing the lower electrode of the ferroelectric capacitor, the dielectric layer of the ferroelectric capacitor and the upper electrode of the ferroelectric capacitor:

Utilize the ultra-high vacuum electron beam evaporation method, deposit the lower electrode Pt on the top of the phospho-silicate glass transistor protective layer in step (6), with a thickness of 40nm, utilize pulsed laser deposition technology, single pulse energy 320mJ, make the energy of the laser pulse The density is 2.5J/cm ² , the laser repetition frequency is 12Hz, the deposition oxygen pressure is 200mTorr, the deposition temperature is 750°C, and the deposition thickness is 320nm Bi _3.15 Nd _0.85 Ti ₃ O ₁₂ ferroelectric thin film, finally using ultra-high vacuum electron beam Evaporation method and preparation process Deposit the upper electrode Pt on the ferroelectric Bi _3.15 Nd _0.85 Ti ₃ O ₁₂ ferroelectric capacitor dielectric layer with a thickness of 40nm. Figure 2(h) shows the deposited ferroelectric capacitor lower electrode and ferroelectric capacitor dielectric Schematic diagram of the result after electrodes are placed on the layer and ferroelectric capacitor.

Step 9, photolithography and etching:

Use photolithography to form a window, etch to form the pattern of the upper electrode and the capacitor dielectric layer, and then remove the glue. Figure 2 (i) is a schematic diagram of the result of etching and patterning the ferroelectric capacitor dielectric layer and the ferroelectric capacitor upper electrode.

Step 10, photolithography and etching:

The window is formed by photolithography, the pattern of the lower electrode is formed by etching, and then the glue is removed. Fig. 2(j) is a schematic diagram of the result after etching and patterning of the lower electrode of the ferroelectric capacitor.

Step 11, depositing a ferroelectric capacitance isolation protective layer:

Using the plasma enhanced chemical vapor deposition method, the ferroelectric capacitor structure formed in the step is deposited with a silicon nitride ferroelectric capacitor isolation protective layer of 280nm, and the process temperature is 300°C. Figure 2(k) is the deposition of the ferroelectric capacitor isolation protective layer. Schematic diagram of the result.

Step 12. Lithographic lead hole:

Use photolithography to form a window, etch the silicon nitride ferroelectric capacitor isolation protection layer pattern on the ferroelectric upper electrode, lower electrode, source and drain to form a lead hole. Figure 2 (l) is after the photoetched lead hole The schematic diagram of the result.

Step 13, steam aluminum:

Through the thermal evaporation process, a 500nm wiring layer is formed, and Figure 2(m) is a schematic diagram of the result after aluminum evaporation.

Step 14. Anti-engraving aluminum:

Using the photolithography process, the pattern of the aluminum lead is photoetched, the aluminum lead to be retained is protected with photoresist, and then the pattern lead is etched to complete the preparation of the single-tube single-capacitance storage unit. Figure 2 (n) is Bi _3.15 Nd Schematic diagram of the fabricated _0.85 Ti ₃ O ₁₂ ferroelectric single-tube single-capacitance storage unit.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than limit the protection scope of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that, The technical solution of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solution of the present invention.

Claims (10)

1. a kind of single tube single capacitor memory unit, it is characterised in that including transistor and capacitance structure, the transistor bag Include：

Substrate；

The separation layer that at least two regional areas are formed alone respectively over the substrate；

It is located at the channel layer between two adjacent separation layers over the substrate；

The source electrode formed on the channel layer and drain electrode, the source electrode and the drain electrode are symmetrically positioned in two on the channel layer Side；

On the channel layer and positioned at the transistor dielectric layer between the source electrode and the drain electrode；

The gate electrode formed on the transistor dielectric layer；

Coat the first transistor protective layer of the transistor dielectric layer and gate electrode；

The capacitance structure includes：

The second transistor protective layer formed on the separation layer；

The bottom electrode formed on the second transistor protective layer；The capacitor dielectric of regional area formation on the bottom electrode Layer；The Top electrode formed on capacitor dielectric layer；The electric capacity of whole capacitance structure is formed and covered in the Top electrode Protective layer；The Top electrode of the capacitance structure is connected with the drain electrode of the transistor by lead.

2. single tube single capacitor memory unit as claimed in claim 1, it is characterised in that the channel layer is by β-Ga₂O₃Material Material composition, the channel layer is also doped with tin, and the doping concentration of the tin is 10¹⁵~10¹⁶cm^-3。

3. single tube single capacitor memory unit as claimed in claim 1, it is characterised in that the substrate is by silicon materials or germanium Material is constituted.

4. single tube single capacitor memory unit as claimed in claim 1, it is characterised in that the thickness of the separation layer is 150nm~300nm, the thickness of the channel layer is 200nm~300nm.

5. single tube single capacitor memory unit as claimed in claim 1, it is characterised in that the transistor dielectric layer is by hafnium Base dielectric material is constituted, and the thickness of the transistor dielectric layer is 2nm~10nm.

6. single tube single capacitor memory unit as claimed in claim 1, it is characterised in that the thickness of the gate electrode is 20nm~50nm, the thickness of the transistor protection layer is 200nm~300nm.

7. single tube single capacitor memory unit as claimed in claim 1, it is characterised in that the electric capacity protective layer is by nitrogenizing Silicon materials or silica material composition, the thickness of the electric capacity protective layer is 280nm~400nm.

8. single tube single capacitor memory unit as claimed in claim 1, it is characterised in that also described comprising being respectively formed in Trace layer in Top electrode, the bottom electrode, the source electrode and the drain electrode, the trace layer is made up of Al, the trace layer Thickness be 500nm~700nm.

9. a kind of memory for including the single tube single capacitor memory unit as described in any one of claim 1~8.

10. a kind of preparation method of single tube single capacitor memory unit as described in any one of claim 1~8, its feature It is, comprises the following steps：

(1) at least two regional areas on substrate form alone separation layer respectively；

(2) by step (1) processing substrate on and form channel layer between two neighboring separation layer；

(3) source electrode and drain electrode are formed on the channel layer of step (2) formation；

(4) on the channel layer by step (3) processing, and transistor dielectric layer is formed between the source electrode and drain electrode, Grid metal is deposited on the transistor dielectric layer, gate electrode is obtained；

(5) the first transistor protective layer of the deposit cladding transistor dielectric layer and gate electrode, is deposited on the separation layer Second transistor protective layer；

(6) bottom electrode is formed on the second transistor protective layer in step (5)；Regional area forms electricity on the bottom electrode Hold dielectric layer；Top electrode is formed on capacitor dielectric layer；The electricity of the whole capacitance structure of covering is formed in the Top electrode Hold protective layer；

(7) trace layer is formed on by step (6) treated Top electrode, bottom electrode, source electrode and drain electrode, produces the single tube Single capacitor memory unit.