CN107301952B - Self-alignment method for grid field plate, source electrode and drain electrode in planar power device - Google Patents

Abstract

The invention relates to a method for self-alignment of grid field plates, source electrodes and drain electrodes in a planar power device, comprising forming an insulating layer on a substrate, coating a negative photoresist for photolithographic development, and forming a first grid /source/drain region; etch the insulating layer at the bottom of the first gate/source/drain region to form a gate/source/drain trench; apply positive photoresist for photolithographic development, and in the gate trench Positive photoresist filling is formed in the groove and the first gate area; source/drain metal layer is formed in the source/drain trench; negative/positive photoresist filling is removed; gate is formed on the upper surface of the device Electrode insulating layer; Coating negative photoresist on the gate insulating layer for photolithographic development, forming a second gate region on the negative photoresist and above the gate trench; Forming a gate metal layer in the gate area; removing and coating negative photoresist. The invention eliminates the misalignment between the gate and the source/drain; improves the processing margin of the device; and improves the output of the large-diameter wafer device.

Description

Self-alignment method of gate field plate and source and drain in a planar power device

technical field

The invention relates to a self-alignment method of grid field plates, source electrodes and drain electrodes in planar power devices.

Background technique

In planar power conversion devices, the gate is used for Schottky contact or metal insulator semiconductor MIS contact, and the source and drain are used for ohmic contact. In the device, the gate, source and drain are all formed at fixed positions , that is, alignment needs to be formed between the gate, the source, and the drain. The existing method uses a separate gate mask that needs to be aligned with the source/drain mask when forming the gate, source, and drain. , however, this conventional approach will always result in misalignment between the gate and source/drain, or fail to achieve alignment, depending on the capabilities of the photographic tool.

Contents of the invention

The purpose of the present invention is to provide a method for self-alignment of gate field plates, source electrodes and drain electrodes in planar power devices.

In order to achieve the above object, the technical scheme adopted in the present invention is:

A self-alignment method for gate field plate and source and drain in a planar power device, comprising steps:

(1) An insulating layer is formed on the substrate, a negative photoresist is coated on the insulating layer, and the negative photoresist is photolithographically developed through the gate, source and drain masks , forming a first gate region, a source region and a drain region on the negative photoresist;

(2) Etching the insulating layer at the bottom of the first gate region, source region and drain region to form gate trenches, source trenches and drain trenches;

(3) Coating positive photoresist on the upper surface of the device, and photolithographically developing the positive photoresist through the gate field plate mask, in the gate trench and the first gate region Positive photoresist filling is formed inside;

(4) Forming a source metal layer and a drain metal layer in the source trench and the drain trench;

(5), removing the negative photoresist and positive photoresist filled in steps (1) and (3);

(6) Form a gate insulating layer on the upper surface of the device;

(7) Coating a negative photoresist on the gate insulating layer, and performing photolithography and development on the negative photoresist through a grid field plate mask, on the negative photoresist , forming a second gate region above the gate trench, and the width of the second gate region is greater than the width of the gate trench;

(8), forming a gate metal layer in the gate trench and the second gate region;

(9), removing the negative photoresist coated in step (6).

Preferably, in (1), the insulating layer includes a first insulating layer formed on the substrate, a second insulating layer formed on the first insulating layer, and on the second insulating layer Apply negative tone photoresist.

Further preferably, the thickness of the first insulating layer is 0-25 nm; the thickness of the second insulating layer is 25-200 nm.

Further preferably, the first insulating layer and the second insulating layer are oxide insulating layers or nitride insulating layers.

Preferably, in (2), the insulating layer at the bottom of the first gate region, source region, and drain region is etched to the substrate.

Preferably, in (2), the etching is wet etching or dry etching.

Preferably, in (6), the gate insulating layer is a silicon nitride insulating layer or an oxide insulating layer.

Preferably, in (6), the thickness of the gate insulating layer is 0-20 nm.

Preferably, in (7), the height of the gate metal layer formed in the second gate region is 50-250 nm.

Preferably, in (4) and (8), the liftoff process is used to remove, and the source metal layer, the drain metal layer and the gate metal layer are annealed.

Due to the use of the above-mentioned technical solutions, the present invention has the following advantages and effects compared with the prior art:

1. Effectively eliminate misalignment between gate and source/drain;

2. Improved the machining allowance of small geometric devices;

3. Effectively increase the output of large-diameter wafer devices.

Description of drawings

Accompanying drawing 1-10 is the step chart of this embodiment.

Wherein: 1. substrate; 20. first insulating layer; 21. second insulating layer; 2a. gate trench; 2b. source trench; 2c. drain trench; 30. negative photoresist; 30a, first gate region; 30b, source region; 30c, drain region; 31, negative photoresist; 31a, second gate region; 4, positive photoresist filling; 5, metal layer; 5b, source metal layer; 5c, drain metal layer; 6, gate insulating layer; 7, metal layer; 7a, gate metal layer.

Detailed ways

Below in conjunction with accompanying drawing and embodiment example, the present invention will be further described:

A self-alignment method for a gate field plate and a source and a drain in a planar power device, specifically comprising the following steps:

(1) An insulating layer is formed on the substrate 1, specifically, the insulating layer is: a first insulating layer 20 formed on the substrate 1, a second insulating layer 21 formed on the first insulating layer 20, the first insulating layer The thickness of 20 is 0-25nm, the thickness of the second insulating layer 21 is 25-200nm, the first insulating layer 20 and the second insulating layer 21 can be oxide insulating layer or nitride insulating layer, as shown in Figure 1;

(2) Coat the negative photoresist 30 on the second insulating layer 21, and perform photolithography on the negative photoresist 30 through the gate, source and drain mask (Gate/Source/Drain mask) developing, forming a first gate region 30a, a source region 30b and a drain region 30c on the negative photoresist 30, as shown in FIG. 2;

(3) Etching the bottom insulating layer of the first gate region 30a, the source region 30b and the drain region 30c to form the gate trench 2a, the source trench 2b and the drain trench 2c, and etching the oxide layer To the substrate 1, the etching method can be through wet etching (wet etch), dry etching (dry etch), as shown in Figure 3;

(4) Coating positive photoresist on the device, and photolithographically developing the positive photoresist through a gate field plate mask, in the gate trench 2a, the first gate Positive photoresist filling 4 is formed in the electrode region 30a. Since the gate field plate mask is used, the positive photoresist filling is not only filled in the gate trench 2a and the first gate region 30a, but also in the first gate region 30a. The negative photoresist 30 on both sides of the pole region 30a is also formed, as shown in FIG. 4 ;

(5) Forming the source metal layer 5b and the drain metal layer 5c in the source trench 2b and the drain trench 2c, in addition to forming an ohmic metal layer in the source trench 2b and the drain trench 2c, The metal layer 5 is also formed on the entire negative photoresist 30 and the positive photoresist filling 4, as shown in FIG. 5 ;

(6), remove the negative photoresist 30 and the metal layer 5 on the positive photoresist filling 4, the removal method can be removed by the liftoff process to remove the negative photoresist coated in steps (2) and (4) Glue 30 and positive photoresist filling 4, as shown in Figure 6, and annealing treatment is carried out to source metal layer 5b, drain metal layer 5c;

(7) A gate insulating layer 6 is formed on the upper surface of the device. The thickness of the gate insulating layer 6 is 0-20nm. The gate insulating layer 6 can be a silicon nitride insulating layer or an oxide insulating layer, as shown in FIG. 7 ;

(8), apply negative photoresist 31 on the gate insulating layer 6, carry out photolithographic development on the negative photoresist 31 through the gate field plate mask, and then A second gate region 31a is formed on the glue 31 and above the gate trench 2a, and the width of the second gate region 31a is greater than the width of the gate trench 2a, as shown in FIG. 8 ;

(9) A gate metal layer 7a is formed in the gate trench 2a and the second gate region 31a, and the height of the gate metal layer 7 formed on the second gate region 31a is 50-250nm, as shown in FIG. 9 ; In addition to forming the gate metal layer 7a in the gate trench 2a and the second gate region 31a, the metal layer 7 is also formed on the negative photoresist 31 at the same time;

(10) The metal layer 7 on the negative photoresist 31 is removed. The method of removal can be through the liftoff process, and the negative photoresist 31 coated in step (8) is removed to form a product as shown in FIG. 10 .

The above-mentioned embodiments are only to illustrate the technical concept and characteristics of the present invention, and the purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention shall fall within the protection scope of the present invention.

Claims (10)

1. A self-alignment method of gate field plate and source electrode and drain electrode in a planar power device, is characterized in that: comprise steps: (1) An insulating layer is formed on the substrate, a negative photoresist is coated on the insulating layer, and the negative photoresist is photolithographically developed through the gate, source and drain masks , forming a first gate region, a source region and a drain region on the negative photoresist; (2) Etching the insulating layer at the bottom of the first gate region, source region and drain region to form gate trenches, source trenches and drain trenches; (3) Coating positive photoresist on the upper surface of the device, and photolithographically developing the positive photoresist through the gate field plate mask, in the gate trench and the first gate region Positive photoresist filling is formed inside; (4) Forming a source metal layer and a drain metal layer in the source trench and the drain trench; (5), removing the negative photoresist and positive photoresist filled in steps (1) and (3); (6) Form a gate insulating layer on the upper surface of the device; (7) Coating a negative photoresist on the gate insulating layer, and performing photolithography and development on the negative photoresist through a grid field plate mask, and on the negative photoresist , forming a second gate region above the gate trench, and the width of the second gate region is greater than the width of the gate trench; (8), forming a gate metal layer in the gate trench and the second gate region; (9), removing the negative photoresist formed by coating in step (7). 2. The self-alignment method of gate field plate and source and drain in a planar power device according to claim 1, characterized in that: in (1), the insulating layer includes A first insulating layer on the substrate, a second insulating layer formed on the first insulating layer, and a negative photoresist is coated on the second insulating layer. 3. The self-alignment method of gate field plate and source and drain in a kind of planar power device according to claim 2, it is characterized in that: the thickness of the first insulating layer is 0-25nm; The thickness of the second insulating layer is 25-200nm. 4. The self-alignment method of gate field plate and source and drain in a kind of planar power device according to claim 2, it is characterized in that: described first insulation layer, second insulation layer are oxide insulation layer or nitride insulating layer. 5. The self-alignment method of gate field plate and source and drain in a planar power device according to claim 1, characterized in that: in (2), for the first gate region, The insulating layer at the bottom of the source region and the drain region is etched to the substrate. 6. The self-alignment method of gate field plate and source and drain in a planar power device according to claim 1, characterized in that: in (2), the etching is wet etching or dry etching etched. 7. The self-alignment method of gate field plate and source and drain in a planar power device according to claim 1, characterized in that: in (6), the gate insulating layer is nitrided Silicon insulating layer or oxide insulating layer. 8. The self-alignment method of gate field plate and source and drain in a planar power device according to claim 1, characterized in that: in (6), the thickness of the gate insulating layer is 0-20nm. 9. The self-alignment method of gate field plate and source and drain in a planar power device according to claim 1, characterized in that: in (8), in the second gate region The height of the formed gate metal layer is 50-250nm. 10. The self-alignment method of gate field plate and source and drain in a planar power device according to claim 1, characterized in that: in (5) and (9), the liftoff process is used to remove, and Annealing is performed on the source metal layer, the drain metal layer and the gate metal layer.