CN107294531B - Phase Locked Loops and Dividers - Google Patents

Abstract

The invention provides a phase-locked loop and a frequency divider. The above-mentioned phase-locked loop includes a differential integral modulator, a decoder and a frequency divider. The decoder is coupled to the differential integral modulator, and generates integer bits of the intermediate frequency division ratio and fractional bits of the intermediate frequency division ratio. The frequency divider is coupled to the decoder to receive the integer bits of the intermediate frequency division ratio and the fractional bits of the intermediate frequency division ratio. The above-mentioned frequency divider switches to the integer frequency dividing mode or the fractional frequency dividing mode according to the control signal.

Description

Phase Locked Loops and Dividers

technical field

The present invention generally relates to a phase-locked loop technique, and more particularly, to a phase-locked loop technique of reducing quantization noise introduced by a Delta-Sigma Modulator (DSM) by switching to a fractional frequency divider.

Background technique

A phase locked loop (PLL) circuit is a feedback control system and is commonly used in integrated circuits and electronic devices. The main function of the phase-locked loop is to change the oscillation frequency of the voltage-controlled oscillator, so that the feedback signal can track the phase of the reference signal, so that the feedback signal can achieve frequency and phase synchronization with the reference signal.

FIG. 1 is a block diagram showing a conventional phase locked loop 100 . As shown in FIG. 1 , the conventional phase-locked loop 100 may include a phase frequency detector (Phase Frequency Detector, PFD) 110, a charge pump (Charge Pump, CP) 120, and a loop filter (Loop Filter, LF) 130 , a Voltage Control Oscillator (VCO) 140 , a Delta-Sigma Modulator (DSM) 150 , and a Frequency Divider (Frequency Divider) 160 .

As shown in Figure 1, a traditional phase-locked loop incorporates a differential integral modulator. The function of the differential integral modulator is to sample at a higher rate, output a digital output value that changes in a certain interval according to the type of the differential integral modulator, and use the changed digital output value as the frequency division of the integer divider. Compared with the input signal, the integer frequency division is performed again and again, and the clock signal FBCLK is made to approach the input clock signal FIN of the phase-locked loop through accumulation. The differential integral modulator also pushes the quantization noise to high frequencies, making it easy to be filtered by a low-pass filter, but since the integer divider itself has a certain low-pass characteristic, it is generally Therefore, there is still a large amount of quantization noise in the phase-locked loop using the differential integral modulator, which affects the performance of the phase-locked loop.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems of the prior art, the present invention provides a phase-locked loop and a method for reducing quantization noise by switching to a fractional frequency divider to reduce the quantization noise introduced by the differential integral modulator.

According to an embodiment of the present invention, a phase locked loop is provided. The above-mentioned phase-locked loop includes a differential integral modulator, a decoder and a frequency divider. The decoder is coupled to the differential integral modulator, and generates integer bits of the intermediate frequency division ratio and fractional bits of the intermediate frequency division ratio. The frequency divider is coupled to the decoder to receive the integer bits of the intermediate frequency division ratio and the fractional bits of the intermediate frequency division ratio. The above-mentioned frequency divider switches to the integer frequency dividing mode or the fractional frequency dividing mode according to the control signal.

According to some embodiments of the present invention, the above-mentioned decoder includes a first decoder and a second decoder. The first decoder is coupled to the differential integral modulator, and generates an input signal of the differential integral modulator. The second decoder is coupled to the differential integral modulator, receives the output signal of the differential integral modulator, and generates the integer bits of the intermediate frequency division ratio and the fractional bits of the intermediate frequency division ratio. According to some embodiments of the present invention, the first decoder has a multiplying circuit, and the above-mentioned second decoder has a dividing circuit.

According to some embodiments of the present invention, the above-mentioned frequency divider includes an integer frequency divider and a frequency divider clock generating circuit. The integer divider receives the integer bits of the above-mentioned intermediate divider ratio. The frequency divider clock generating circuit receives the fractional bits of the above-mentioned intermediate frequency division ratio and the above-mentioned control signal.

An embodiment of the present invention provides a frequency divider. The above frequency divider includes an integer frequency divider and a frequency divider clock generating circuit. The integer divider receives integer bits of the intermediate divider ratio. The frequency divider clock generation circuit is coupled to the above-mentioned integer frequency divider, and receives the fractional bits of the intermediate frequency division ratio and the control signal.

An embodiment of the present invention provides a method for reducing quantization noise. The above-mentioned method for reducing quantization noise is applicable to a phase-locked loop. The steps of the above-mentioned method for reducing quantization noise include: generating an input signal of a differential integral modulator by a first decoder; receiving an output signal of the differential integral modulator by a second decoder to generate an intermediate frequency division ratio Integer bits and fractional bits of the intermediate frequency division ratio; transmitting the integer bits of the above-mentioned intermediate frequency division ratio and the decimal places of the above-mentioned intermediate frequency division ratio to the frequency divider; or fractional mode.

An embodiment of the present invention provides a method for reducing quantization noise. The methods described above for reducing quantization noise apply to frequency dividers. The steps of the above-mentioned method for reducing quantization noise include, from the decoder, receiving integer bits of the intermediate frequency division ratio and decimal places of the intermediate frequency division ratio; frequency mode.

Other additional features and advantages of the present invention can be obtained by those skilled in the art by making some changes and modifications according to the devices and methods disclosed in the implementation methods of the present application without departing from the spirit and scope of the present invention.

Description of drawings

FIG. 1 is a block diagram showing a phase locked loop 100 of the prior art.

FIG. 2 is a block diagram illustrating a phase locked loop 200 according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a phase-locked loop (PLL) circuit 300 according to another embodiment of the present invention

FIG. 4 is a block diagram illustrating a frequency divider 280 according to an embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a frequency divider clock generating circuit 282 according to an embodiment of the present invention.

FIG. 6 is a diagram showing a signal waveform according to an embodiment of the present invention.

FIG. 7 is a flowchart 600 illustrating a method for reducing quantization noise according to an embodiment of the present invention.

FIG. 8 is a flowchart 700 illustrating a method for reducing quantization noise according to an embodiment of the present invention.

Detailed ways

This chapter describes the best mode for implementing the present invention, and is intended to illustrate the spirit of the present invention but not to limit the protection scope of the present invention, which should be determined by the appended claims.

FIG. 2 is a block diagram illustrating a phase-locked loop (PLL) circuit 200 according to an embodiment of the present invention. As shown in FIG. 2, the phase-locked loop 200 may include a phase frequency detector (Phase Frequency Detector, PFD) 210, a charge pump (Charge Pump, CP) 220, a loop filter (Loop Filter, LF) 230, a voltage A Voltage Control Oscillator (VCO) 240 , a first decoder 250 , a Delta-Sigma Modulator (DSM) 260 , a second decoder 270 and a Frequency Divider 280 are included. It should be noted that the block diagram in FIG. 2 is only for the convenience of illustrating the embodiments of the present invention, and the present invention is not limited thereto.

The operations of the frequency discriminator 210 , the charge pump 220 and the loop filter 230 of the phase-locked loop 200 are similar to the structure of the traditional phase-locked loop, and will not be repeated in the present invention.

According to an embodiment of the present invention, the first decoder 250 receives a theoretical frequency division ratio DIV, which is divided into integer bits DIV_M and decimal bits DIV_N for the convenience of description below. For example, if the theoretical frequency division ratio is 5.4, the integer bit DIV_M is 5, the fractional bit DIV_N is 4, the integer bit DIV_M and the fractional bit DIV_N are processed by the first decoder 250 to generate the input signal of the differential integral modulator 260 DSMIN, the signal DSMIN is processed by the differential integral modulator 260 to generate the signal DSMOUT. The function of the differential integral modulator 260 is to sample the signal DSMIN at a higher rate and output a changed digital output value. For example, when the differential integral modulator 260 is a 3-stage 4-stage differential integral modulator, the output signal DSMOUT takes an integer in the interval [DSMIN-4, DSMIN+3], and the integer output signal DSMOUT is sent to the second decoder 270, in other aspects of the present invention In an embodiment, the differential integral modulator 260 may be of any order.

The first decoder 250 includes a multiplication circuit that is multiplied by 2. At this time, when DIV_N is less than or equal to 4, the last digit of the DSMIN integer digit is always binary 0; when DIV_N is greater than or equal to 5, the last digit of the DSMIN integer digit is always binary. 1. For example, if the theoretical frequency division ratio DIV is equal to 5.4, the decimal place DIV_N is equal to 4, and the theoretical frequency division ratio DIV is 0101.011 in binary. After being processed by the multiplication circuit of the first decoder 250 multiplied by 2, the output signal DSMIN is equal to the binary value of 1010.11..., if the theoretical frequency division ratio DIV is equal to 5.5, DIV_N is equal to 5, the theoretical frequency division ratio DIV is binary 0101.1, and is processed by the multiplication circuit of the first decoder 250 multiplied by 2, and the output signal DSMIN is equal to binary The value is 1011. If the differential integral modulator 260 is a 3-order 4-stage differential integral modulator, the output signal DSMOUT takes an integer in the interval [DSMIN-4, DSMIN+3], and the integer output signal DSMOUT is sent to the second decoder 270 .

The second decoder 270 includes a division circuit that divides by 2, and the division circuit has a corresponding relationship with the above-mentioned multiplication circuit. For example, when the multiplication circuit is a multiplication circuit of a multiplication by 2, the division circuit is a division circuit of a division by 2, In other embodiments of the present invention, the first decoder 250 and the second decoder 270 may also include other multiplication circuits and division circuits that have a corresponding relationship.

The integer output signal DSMOUT is processed by the second decoder 270 to generate an integer bit N of the intermediate frequency division ratio and a decimal bit S of the intermediate frequency division ratio. The second decoder 270 converts the integer bit N of the intermediate frequency division ratio and the middle The fractional bits S of the frequency division ratio are passed to the frequency divider 280 . The integer bit N of the intermediate frequency division ratio is the integer part of the result of the signal DSMOUT processed by the division circuit of the second decoder 270 ; The fractional part of the result is processed. For example, if the signal DSMIN is equal to the binary value of 1010.11..., it is processed by the 3-order 4-stage differential integral modulator 260, and the output signal DSMOUT takes the value in the interval [DSMIN-4, DSMIN+3]. Integer, for example, when the signal DSMOUT is equal to the binary value 1010, it is processed by the division circuit of the second decoder 270, and the binary value 1010 is shifted to the right by 1 bit. Bit S is a 1-bit binary value of 0. When DSMOUT is equal to a binary value of 1011, the binary value of 1011 is shifted to the right by 1 bit after being processed by the division circuit of the second decoder 270, and the integer bit N of the intermediate frequency division ratio is a binary value of 0101. The fractional bit S of the intermediate frequency division ratio is a 1-bit binary value of 1.

In other embodiments of the present invention, the first decoder 250 and the second decoder 270 may also include other multiplication circuits and division circuits that have a corresponding relationship, for example, when the first decoder 250 includes a multiplication by 4 The circuit and the second decoder 270 include a division circuit that divides by 4, then the multiplication and division of the corresponding binary data needs to be shifted 2 bits to the left and 2 bits to the right, and the decimal place S of the corresponding intermediate frequency division ratio is a 2-bit binary. value. The number of decimal places S of the intermediate frequency division ratio depends on the multiplication circuit included in the first decoder 250 and the division circuit included in the second decoder 270 .

In another embodiment of the present invention, for the convenience of operation, the fractional bit S of the intermediate frequency division ratio can also be a fractional part of the result obtained by subtracting the signal DSMOUT from a certain value and processed by the division circuit of the second decoder 270, for example When the decimal place S of the intermediate frequency division ratio is a 1-bit binary number, and the certain value is 2, then the decimal place S of the intermediate frequency division ratio is assigned as 01, or 10. If other values such as 00 or 11 appear, It is judged as an operation error.

FIG. 3 is a block diagram showing a phase-locked loop (Phase-locked loops, PLL) circuit 300 according to another embodiment of the present invention. As shown in FIG. 3 , the phase-locked loop 300 may include frequency discrimination and phase discrimination. Phase Frequency Detector (PFD) 310, Charge Pump (CP) 320, Loop Filter (LF) 330, Voltage Control Oscillator (VCO) 340, Differential Integral Modulator (Delta -SigmaModulator, DSM) 350, decoder 360 and frequency divider (Frequency Divider) 370.

Different from the embodiment shown in FIG. 2 , this embodiment integrates the first decoder 250 and the second decoder 270 in FIG. 2 into the decoder 350 , so that the decoder 350 has the first decoder at the same time. The function of the encoder 250 and the second decoder 270 is to receive the signal DIV_M and the signal DIV_N, process and generate the signal DSMIN and output it to the differential integral modulator 360; receive the signal DSMOUT, process the integer bit N and the intermediate divider of the intermediate frequency division ratio. The decimal place S of the frequency ratio is output to the frequency divider 370 .

FIG. 4 is a block diagram of a frequency divider 280 according to an embodiment of the present invention. As shown in FIG. 4 , the frequency divider 280 includes an integer frequency divider 281 and a frequency divider clock generating circuit 282 .

The integer divider 281 is an integer divider. According to an embodiment of the present invention, the integer frequency divider 281 receives the integer bit N of the frequency division ratio output by the second decoder 270 and the clock signal CLK1 output by the frequency divider clock generation circuit 282, and outputs the enable signal EN to the divider clock generation circuit 282 , and the clock signal FBCLK to the phase frequency detector 210 .

According to an embodiment of the present invention, the frequency divider clock generating circuit 282 receives the signal SMODE, and controls the frequency divider 280 to switch between the integer frequency dividing mode or the fractional frequency dividing mode according to the signal SMODE. When the control signal SMODE is equal to 0, part of the function of the frequency divider clock generating circuit 282 is turned off, and the frequency divider 280 is switched to the integer frequency division mode. When the control signal SMODE is equal to 1, all functions of the frequency divider clock generating circuit 282 are activated, and the frequency divider 280 is switched to the fractional frequency division mode. According to an embodiment of the present invention, the control signal SMODE is provided by an external circuit, and the control signal SMODE is set by the user according to requirements.

When the frequency divider 280 is switched to the integer frequency division mode, the frequency divider clock generation circuit 282 is in a partially enabled state, and the clock signal CLK1 output by the frequency divider clock generation circuit 282 is the voltage controlled oscillator collected by the multiplexer The output signal of 240 , that is, the clock signal CLK1 is equal to a certain channel of clock signal output by the voltage-controlled oscillator 240 , and is transmitted to the integer frequency divider 281 . That is, when the frequency divider 280 is switched to the integer frequency division mode, the frequency divider 280 can be regarded as only the integer frequency divider 281 .

According to an embodiment of the present invention, when the frequency divider 280 is switched to the integer frequency division mode, the integer frequency divider 281 receives the integer bit N of the frequency division ratio, and the integer frequency divider 281 starts to increase the clock signal CLK1 from 0 Counting along the edge, when the count value is equal to the integer bit N of the frequency division ratio, the output enable signal EN generates a pulse, and gives a reset signal to the integer frequency divider 281 to start counting from 0 again.

When the frequency divider 280 is switched to the fractional frequency division mode, the frequency divider clock generation circuit 282 is fully enabled. That is to say, when the frequency divider 280 is switched to the fractional frequency dividing mode, the integer frequency divider 281 combined with the frequency divider clock generating circuit 282 can be regarded as a fractional frequency divider. When the frequency divider 280 is switched to the fractional frequency division mode, the integer frequency divider output enable signal EN acts on the frequency divider clock generation circuit 282 and receives the clock signal CLK1 from the frequency divider clock generation circuit 282 for fractional division. frequency operation.

The frequency divider clock generation circuit 282 utilizes at least one clock signal VCOCLK generated by the voltage controlled oscillator 240, so that the intermediate frequency division ratio of the frequency divider 280 is included in the integer bit N of the frequency division ratio as a starting point, 1/2 ⁿ . ^-1 (n is a natural number) is a set with a step size and N+1 as an end point. The frequency divider clock generation circuit 282 needs to use 2 ^n-1 clock signals, and the 2 ^n-1 clock signals are equally phased. , the phase interval is 2π/2 ^n-1 . In one embodiment, to implement a fractional divider compatible with integer and half-integer frequency division, that is, to make the frequency division ratio of the frequency divider 280 included in the set {N, N+1/2, N+1}, the clock The generating circuit 282 needs to use the first clock signal VCOCLK1 and the second clock signal VCOCLK2 generated by the voltage controlled oscillator 240 , and the first clock signal VCOCLK1 and the second clock signal VCOCLK2 are inverted. In another embodiment, the frequency dividing ratio of the frequency divider 280 is to be included in the set of {N, N+1/4, N+1/2, N+3/4, N+1}, that is, the frequency divider When the frequency division ratio of 280 is any value in the set of {N, N+1/4, N+1/2, N+3/4, N+1}, n is equal to 3, the frequency divider clock generation circuit 282 It is necessary to utilize 4 clocks generated by the voltage controlled oscillator 240 with a phase interval of π/2.

According to an embodiment of the present invention, the frequency divider clock generation circuit 282 obtains the decimal place S of the intermediate frequency division ratio from the second decoder 270 including a divide-by-2 circuit. For the convenience of operation, another value of S is 2 minus 2 The decimal place S of the original intermediate frequency division ratio is removed, so when the frequency divider 280 is switched to the fractional frequency division mode, when the decimal place of the frequency division ratio is a first signal, for example, S is equal to 01, the frequency divider clock generation circuit 282 The phase of the clock signal CLK1 is switched for a first predetermined number of times, for example, once; when the decimal place of the frequency division ratio is the second signal, for example, S is equal to 10, the frequency divider clock generation circuit 282 performs the first predetermined number of times on the phase of the clock signal CLK1. Two predetermined times of switching, for example, two times; when the signal S is the third signal, for example, S is equal to 00 or 11, it means that the phase-locked loop is operating in an error, and the frequency divider clock generating circuit 282 maintains the previous state until the S returns to normal 01 or 10, otherwise no switching is performed.

5 is a circuit diagram of the frequency divider clock generation circuit 282 according to an embodiment of the present invention. Through the first decoder 250, the second decoder 270 and the frequency divider clock generation circuit 282 of FIG. The value of the control signal SMODE is switched to the fractional frequency division mode to realize a fractional frequency divider compatible with integer and half-integer frequency division, that is, the frequency division ratio of the frequency divider 280 can be set {N, N+1/2, N+1 }, and can switch to integer frequency division mode according to the value of the control signal SMODE.

As shown in FIG. 5 , when the control signal SMODE is equal to 0, the frequency divider 280 switches to the integer frequency division mode. A second D-type flip-flop 530 , an exclusive OR gate (XOR) 540 , a third D-type flip-flop 550 and a second multiplexer 560 are included. The output SW of the second D-type flip-flop 530 is always at a high level, the signal sel output by the third D-type flip-flop 550 is set, that is, the signal sel is always at a high level or a low level, the frequency divider clock generation circuit The clock signal CLK1 output by 282 is a certain output signal of the voltage-controlled oscillator 240 collected by the multiplexer 560. In this embodiment, the clock signal CLK1 is always the first clock signal VCOCLK1 output by the voltage-controlled oscillator 240. Or it is always the second clock signal VCOCLK2 output by the voltage controlled oscillator 240, and is transmitted to the integer frequency divider 281. Therefore, when the frequency divider 280 is switched to the integer frequency division mode, the frequency divider 280 can be regarded as only integer frequency divider 281.

As shown in FIG. 5 , when the control signal SMODE is equal to 1, the frequency divider 280 switches to the fractional frequency division mode. The frequency divider clock generation circuit 282 is fully enabled, including a first D-type flip-flop 510, a first multiplexer 520, a second D-type flip-flop 530, an exclusive OR gate (XOR) 540, and a third D-type flip-flop 540. flip-flop 550 and second multiplexer 560 . The first multiplexer 520 is coupled to the first D-type flip-flop 510 and the second D-type flip-flop 530, respectively. When S is equal to 01, the first multiplexer 520 outputs the EN signal to the second D-type flip-flop 530 . When S is equal to 10, the first multiplexer 520 outputs the output signal of the first D-type flip-flop 510 to the second D-type flip-flop 530 . When S is equal to 00 or 11, the first multiplexer 520 outputs a low level to the second D-type flip-flop 530 . The second D-type flip-flop 530 receives the control signal SMODE, and outputs the signal SW to the XOR gate 540 . The XOR gate 540 receives the signal SW from the second D-type flip-flop 530 and the signal sel from the third D-type flip-flop 550 . The third D-type flip-flop 550 receives the signal add output by the exclusive OR gate 540 and outputs the signal sel. The second multiplexer 560 receives the first clock signal VCOCLK1 and the second clock signal VCOCLK2, and selects the first clock signal VCOCLK1 or the second clock signal VCOCLK2 as the clock signal according to the signal sel output by the third D-type flip-flop 550 CLK1. After the clock signal CLK1 is generated, the second multiplexer 560 transmits the clock signal CLK1 to the integer frequency divider 281 .

FIG. 6 is a timing diagram according to an embodiment of the present invention. The timing diagram shown in FIG. 6 is based on the fully enabled state of the frequency divider clock generation circuit 282 shown in FIG. 5 , that is, the case where the frequency divider 280 is switched to the fractional frequency division mode. Examples, the present invention is not limited thereto.

As shown in FIG. 6 , the waveforms from a to b, from c to d, from e to f, from g to h, from i to j, from k to l, and from m to n indicate that the clock signal CLK1 triggers D When the type flip-flop samples the input level, from the clock signal CLK1 reaching the D-type flip-flop to the output signal of the D-type flip-flop, the delay time t is generated inside the D-type flip-flop, so the delay time of each D-type flip-flop is t. The output has a delay of time t for the rising edge of the clock signal CLK1 that triggers it, and the delay t is not completely consistent because of the differences between the individual D-type flip-flops, but the delay t must be greater than 0. And less than 1/2 period of the inverted clock signal VCOCLK1 or VCOCLK2.

The part of the waveform from e to g corresponds to the waveform with S equal to 01. After each count, the enable signal EN generates a high level. The duration of this high level is 1 cycle of the clock signal CLK1. In the second D-type Flip-flop 430, the clock signal CLK1 samples the signal EN, the output signal SW is a high level for one clock signal CLK1 cycle, the signal sel is flipped once, and the control clock signal CLK1 is switched from the signal VCOCLK1 to the signal VCOCLK2, from the rise of the clock signal CLK1 The time taken from edge e to its next rising edge is 1/2 cycle of the inverted clock signal VCOCLK1 or VCOCLK2, so when S is equal to 01, the frequency divider clock generation circuit 282 uses the fractional bit S of the frequency division ratio to be equal to 01 to achieve Counting 1/2 bits of the input clock signal VCOCLK1 or VCOCLK2 enables the frequency divider clock generation circuit 282 and the integer frequency divider 281 to realize the actual frequency division ratio DIV_actual to be N+1/2.

The part of the waveform diagram from k to o corresponds to the waveform diagram with S equal to 10. After each count, when the enable signal EN is at a high level, the first multiplexer 420 outputs a high level, and the rising edge of the clock signal CLK1 is k After the arrival, the output of the first multiplexer 420 is flipped to a low level, and after the rising edge m of the clock signal CLK1 comes, the low level will be transmitted to the signal SW in the second D-type flip-flop 430 . Before that, the signal SW was at a high level for two cycles of the clock signal CLK1, and the signal sel was flipped twice, so the signal sel controlled the clock signal CLK1 to switch between the signal VCOCLK2 and the signal VCOCLK1 twice, since the rising edge k of the clock signal CLK1 The time taken to its next rising edge is 1/2 cycle of the clock signal VCOCLK1 or VCOCLK2, and the time taken from the rising edge m of the clock signal CLK1 to its next rising edge is 1/2 cycle of the inverted clock signal VCOCLK1 or VCOCLK2, Therefore, when S is equal to 10, the frequency divider clock generation circuit 282 receives the fractional bit S of the frequency division ratio equal to 10, and realizes the count of the input clock signal VCOCLK1 or VCOCLK2 (1/2+1/2) bit, that is, 1 bit, so that The frequency divider clock generation circuit 282 and the integer frequency divider 281 together can realize the actual frequency division ratio DIV_actual to be N+1 bit frequency division, and because under the action of the differential integral modulator, the integer bit N of the frequency division ratio is The constantly fluctuating integer, N and N+1 are no different, and it is also equivalent to the frequency divider that realizes the frequency division of N bits.

To sum up, when the frequency divider 280 is switched to the integer frequency division mode, combined with the differential integral modulator, the clock signal FBCLK output by the frequency divider 280 is a long-term comprehensive effect of several N integer frequency divisions to achieve a fractional frequency division effect. When the frequency divider 280 is switched to the fractional frequency division mode, combined with the differential integral modulator, the clock signal FBCLK output by the frequency divider 280 is the long-term comprehensive effect of several N integer frequency divisions and several half-integer frequency divisions, and the realized fractional frequency division Effect.

According to the phase-locked loop 200 proposed in the embodiment of the present invention, when the fractional frequency divider of the present invention is used, in addition to reducing the quantization noise introduced by the differential integral modulator to 1/2 or lower, it also effectively utilizes Due to the decimal places of the frequency division ratio, the frequency division progress is improved, so that the clock signal FBCLK is closer to the input clock signal FIN of the phase-locked loop. In addition, the phase-locked loop 200 proposed in the embodiment of the present invention can be compatible with both an integer frequency divider and a fractional frequency divider, so that the operation of the phase-locked loop is more flexible.

FIG. 7 is a flowchart 700 illustrating a method for reducing quantization noise according to an embodiment of the present invention. The quantization noise reduction method shown in the flowchart 700 is applicable to the phase locked loop 200 . In step S710, the phase-locked loop 200 generates the input signal of the differential integral modulator by the first decoder. In step S720, the phase-locked loop 200 receives the output signal of the differential integral modulator through a second decoder to generate the integer bits of the frequency division ratio and the fractional bits of the frequency division ratio. In step S730, the PLL 200 transmits the integer bits of the frequency division ratio and the fractional bits of the frequency division ratio to the frequency divider. In step S740, the phase-locked loop 200 determines, according to the control signal, to switch the frequency divider to the integer frequency dividing mode or the fractional frequency dividing mode.

According to an embodiment of the present invention, in the method shown in the flowchart 700, the first decoder performs a multiplication operation, and the second decoder performs a division operation.

According to an embodiment of the present invention, the steps of the flowchart 700 further include, when switching to the above-mentioned integer frequency division mode, partially enabling the frequency divider clock generation circuit in the frequency divider, and when switching to the above-mentioned fractional frequency division mode , fully enabling the above-mentioned frequency divider clock generating circuit in the above-mentioned frequency divider.

According to an embodiment of the present invention, the steps of the flowchart 700 further include that when the decimal place of the frequency division ratio is the first signal, switching the output clock signal from the first clock signal to the second clock signal, and executing the first predetermined number of times switching, and when the fractional bit of the frequency division ratio is the second signal, switching the output clock signal from the first clock signal to the second clock signal, and then switching from the second clock signal to the first clock signal, performed The second predetermined number of switching.

FIG. 8 is a flowchart 800 illustrating a method for reducing quantization noise according to an embodiment of the present invention. The method of reducing quantization noise shown in flowchart 800 applies to frequency divider 280 . In step S810, the frequency divider 280 receives the integer bits of the frequency division ratio and the fractional bits of the frequency division ratio from the decoder. In step S820, the frequency divider 280 decides to switch to the integer frequency division mode or the fractional frequency division mode according to the control signal.

"An embodiment" or "embodiment" mentioned in this specification means that the specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment according to the present invention, but does not mean They are present in every example. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places in this specification are not necessarily referring to the same embodiment of the invention.

The above paragraphs use multiple levels of description. Obviously, the teachings herein may be implemented in a variety of ways, and any particular architecture or functionality disclosed in the examples is merely a representative case. Based on the teachings herein, those skilled in the art will understand that each aspect disclosed herein can be implemented independently or that two or more aspects can be implemented in combination.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope defined by the appended claims.

Claims (9)

1. A phase-locked loop, comprising: Differential integral modulator, receiving input signal; a decoder, coupled to the differential integral modulator, to generate integer bits of the frequency division ratio and fractional bits of the frequency division ratio; and a frequency divider, coupled to the decoder, receiving the integer bits of the frequency dividing ratio and the fractional bits of the frequency dividing ratio, and switching to the integer frequency dividing mode or the fractional frequency dividing mode according to the control signal, The above frequency dividers include: an integer divider that receives integer bits of the above-mentioned division ratio; and The frequency divider clock generation circuit receives the decimal place of the frequency division ratio and the above control signal, When the frequency divider is switched to the integer frequency dividing mode, the frequency divider clock generating circuit is partially enabled; and When the frequency divider is switched to the above-mentioned fractional frequency division mode, the above-mentioned frequency divider clock generating circuit is fully enabled. 2. The phase-locked loop of claim 1, wherein the decoder comprises: a first decoder, comprising a multiplying circuit, coupled to the differential integral modulator, to generate the input signal of the differential integral modulator; and The second decoder includes a division circuit corresponding to the multiplication circuit, is coupled to the differential integral modulator, receives the output signal of the differential integral modulator, and generates the integer bits of the frequency division ratio and the decimal fraction of the frequency division ratio bit. 3. The phase-locked loop as claimed in claim 1, wherein there are 2 ^n-1 clock signals with a phase interval of 2π/2 ^n-1 input into the above-mentioned frequency divider clock generating circuit, and n is a natural number; When the decimal place of the frequency division ratio is the first signal, the output clock signal of the frequency divider clock generation circuit is switched from the first clock signal among the 2n ^- 1 clock signals with a phase interval of 2π/ ^2n-1 to a second clock signal; and When the decimal place of the frequency division ratio is the second signal, the output clock signal of the frequency divider clock generation circuit is switched from the first clock signal among the 2n ^- 1 clock signals with a phase interval of 2π/ ^2n-1 to The second clock signal is switched from the second clock signal to the first clock signal. 4. A frequency divider comprising: an integer divider that receives integer bits of the divider ratio; and a frequency divider clock generating circuit, coupled to the above-mentioned integer frequency divider, and receiving the fractional bits of the frequency dividing ratio and a control signal, The above-mentioned frequency divider clock generation circuit switches the frequency divider to the integer frequency dividing mode or the fractional frequency dividing mode according to the above-mentioned control signal, When the frequency divider is switched to the integer frequency dividing mode, the frequency divider clock generating circuit is partially enabled; and When the frequency divider is switched to the above-mentioned fractional frequency division mode, the above-mentioned frequency divider clock generating circuit is fully enabled. 5. The frequency divider as claimed in claim 4, wherein there are 2 ^n-1 clock signals with a phase interval of 2π/2 ^n-1 input into the above-mentioned frequency divider clock generating circuit, and n is a natural number; When the decimal place of the frequency division ratio is the first signal, the output clock signal of the frequency divider clock generation circuit is switched from the first clock signal among the 2n ^- 1 clock signals with a phase interval of 2π/ ^2n-1 to a second clock signal; and When the decimal place of the frequency division ratio is the second signal, the output clock signal of the frequency divider clock generation circuit is switched from the first clock signal among the 2n ^- 1 clock signals with a phase interval of 2π/ ^2n-1 to The second clock signal is switched from the second clock signal to the first clock signal. 6. A phase-locking method, applicable to a phase-locked loop, comprising: performing a multiplication operation by the first decoder to generate an input signal of the differential integral modulator; Receive the output signal of the differential integral modulator by the second decoder, perform a division operation corresponding to the multiplication operation, and generate the integer bits of the frequency division ratio and the fractional bits of the frequency division ratio; sending the integer bits of the frequency division ratio and the fractional bits of the frequency division ratio to the frequency divider; and According to the control signal, it is determined that the above-mentioned frequency divider is switched to the integer frequency division mode or the fractional frequency division mode, The phase locking method further includes: When the frequency divider is switched to the integer frequency dividing mode, partially enabling the frequency divider clock generating circuit of the frequency divider; and When the frequency divider is switched to the fractional frequency dividing mode, the frequency divider clock generating circuit of the frequency divider is fully enabled. 7. The phase locking method of claim 6, further comprising: There are 2 ^n-1 clock signals with a phase interval of 2π/2 ^n-1 input to the above-mentioned frequency divider clock generation circuit, n is a natural number; When the decimal place of the frequency division ratio is the first signal, the output clock signal of the frequency divider clock generation circuit is switched from the first clock signal among the 2n ^- 1 clock signals with a phase interval of 2π/ ^2n-1 to a second clock signal; and When the decimal place of the frequency division ratio is the second signal, the output clock signal of the frequency divider clock generation circuit is switched from the first clock signal among the 2n ^- 1 clock signals with a phase interval of 2π/ ^2n-1 to The second clock signal is switched from the second clock signal to the first clock signal. 8. A phase locking method, applicable to a frequency divider, comprising: receiving from the decoder integer bits of the divider ratio and fractional bits of the divider ratio; and According to the control signal, it is determined that the above-mentioned frequency divider is switched to the integer frequency division mode or the fractional frequency division mode, The phase locking method further includes: When the frequency divider is switched to the integer frequency dividing mode, partially enabling the frequency divider clock generating circuit of the frequency divider; and When the frequency divider is switched to the fractional frequency dividing mode, the frequency divider clock generating circuit of the frequency divider is fully enabled. 9. The phase locking method of claim 8, further comprising: There are 2 ^n-1 clock signals with a phase interval of 2π/2 ^n-1 input to the above-mentioned frequency divider clock generation circuit, n is a natural number; When the decimal place of the frequency division ratio is the first signal, the output clock signal of the frequency divider clock generation circuit is switched from the first clock signal among the 2n ^- 1 clock signals with a phase interval of 2π/ ^2n-1 to a second clock signal; and When the decimal place of the frequency division ratio is the second signal, the output clock signal of the frequency divider clock generation circuit is switched from the first clock signal among the 2n ^- 1 clock signals with a phase interval of 2π/ ^2n-1 to The second clock signal is switched from the second clock signal to the first clock signal.

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