CN107293505A - Dead ring, pre-cleaning cavity and semiconductor processing equipment - Google Patents
Dead ring, pre-cleaning cavity and semiconductor processing equipment Download PDFInfo
- Publication number
- CN107293505A CN107293505A CN201610227636.9A CN201610227636A CN107293505A CN 107293505 A CN107293505 A CN 107293505A CN 201610227636 A CN201610227636 A CN 201610227636A CN 107293505 A CN107293505 A CN 107293505A
- Authority
- CN
- China
- Prior art keywords
- dead ring
- loading end
- cleaning cavity
- pedestal
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Dead ring, pre-cleaning cavity and semiconductor processing equipment that the present invention is provided, it is applied in pre-cleaning cavity, and pedestal is provided with the pre-cleaning cavity, and the pedestal includes the first loading end of the central area for bearing wafer lower surface.Dead ring is arranged on pedestal, and is looped around the edge of the first loading end.Dead ring includes ring body, and the ring body has the second loading end and annular boss, wherein, the fringe region of the second loading end and chip lower surface is oppositely arranged.Annular boss is looped around the second loading end edge, and upper surface of the upper surface higher than chip of annular boss.The dead ring that the present invention is provided, it can reduce the etch rate of wafer edge region, so as to reduce the difference between the etch rate of wafer edge region and the etch rate of wafer central region, and then can improve etching homogeneity.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular it relates to a kind of dead ring,
Pre-cleaning cavity and semiconductor processing equipment.
Background technology
Pre-cleaning techniques have been widely used in semiconductor preparing process, especially for
The manufacturing process such as integrated circuit, silicon perforation.Prewashed purpose is to remove being stained with crystal column surface
Dirty and impurity, to be conducive to effective progress of subsequent deposition process, it is ensured that IC-components
Overall performance.
Inductively coupled plasma (ICP) process equipment is usually taken in conventional pre-cleaning cavity,
Its general principle is the high-voltage alternating electric field produced using radio-frequency power supply, by process gas (for example
Argon gas, helium, hydrogen and oxygen etc.) excite to form plasma, have in the plasma
The ion of high reaction activity or high-energy, these ions are made by chemical reaction or physical bombardment
With the removal to workpiece surface progress impurity.
Fig. 1 is the sectional view of existing pre-cleaning cavity.Referring to Fig. 1, pre-cleaning cavity by
The insulating top cover 4 of reaction cavity 1, annular support member 2 and dome shape is limited and formed, in insulation
Wrapping around for top cover 4 is provided with coil 3, coil 3 successively with the first adaptation 5 and first
Radio-frequency power supply 6 is electrically connected, to excite the process gas formation plasma in pre-cleaning cavity
Body.Moreover, being additionally provided with the pedestal 7 for bearing wafer 9, pedestal in pre-cleaning cavity
7 electrically connect with the second adaptation 10 and the second radio-frequency power supply 11 successively, on chip 9
Bias is produced, so as to attract plasma to be moved towards chip 9, to remove on the surface of chip 9
Impurity.In addition, dead ring 8 is provided with the edge of pedestal 7, to block pedestal 21
Edge and side not by plasma etching.The concrete structure of dead ring 8 as shown in Fig. 2
The upper surface of dead ring 8 and the upper surface of chip 9 are substantially flush, and this in actual applications can not
There is problems with avoiding：
As shown in figure 3, radially being carved for the chip that technique acquisition is carried out using existing dead ring
Lose the distribution map of speed.Ordinate is etch rate, and abscissa is the position of chip radially.
As seen from the figure, the etch rate of wafer edge region (a-quadrant) is apparently higher than central area,
Because the electric-field intensity being distributed at the position tactile with the side edge of pedestal 7 of chip 9 is inclined
Greatly, the bombarding energy increase for moving to the ion of the adjacent edges of pedestal 7 is caused, so as to cause crystalline substance
The etch rate increase of piece fringe region, so as to have impact on etching homogeneity, this phenomenon is referred to as
Fringe field effects.
The content of the invention
It is contemplated that at least solving one of technical problem present in prior art, it is proposed that
A kind of dead ring, pre-cleaning cavity and semiconductor processing equipment, it can reduce wafer edge region
The etch rate in domain, so as to reduce etch rate and the center wafer area of wafer edge region
Difference between the etch rate in domain, and then etching homogeneity can be improved.
To realize that the purpose of the present invention provides a kind of dead ring, apply in pre-cleaning cavity,
Pedestal is provided with the pre-cleaning cavity, the pedestal includes being used for bearing wafer lower surface
Central area the first loading end；The dead ring is arranged on the pedestal, and is looped around
The edge of first loading end, the dead ring includes ring body, the ring body
With the second loading end and annular boss, wherein, second loading end and the chip following table
The fringe region in face is oppositely arranged；The annular boss is looped around the second loading end edge
Place, and upper surface of the upper surface higher than the chip of the annular boss.
It is preferred that, second loading end be plane, and with the edge of the chip lower surface
Region is in contact.
It is preferred that, the inner peripheral surface of the annular boss is mutually perpendicular to second loading end.
It is preferred that, it is vertical between the upper surface of the annular boss and second loading end
The span of spacing is in 3~5mm.
It is preferred that, the pedestal includes annular groove, and the annular groove is arranged on described the
The edge of one loading end；The ring body is arranged on the annular groove.
As another technical scheme, the present invention also provides a kind of pre-cleaning cavity, including sets
Pedestal and dead ring in it are put, the pedestal includes the loading end for bearing wafer, institute
State dead ring to be arranged on the pedestal, and be looped around the edge of the loading end；It is described exhausted
Edge ring employs the above-mentioned dead ring that the present invention is provided.
As another technical scheme, the present invention also provides a kind of semiconductor processing equipment, wraps
Pre-cleaning cavity is included, coil is provided with the top of the pre-cleaning cavity, by the line
Circle loading radio-frequency power, to excite the reacting gas formation plasma in the pre-cleaning cavity
Body, the above-mentioned pre-cleaning cavity that the pre-cleaning cavity is provided using the present invention, also, pass through
Rf bias is loaded to the pedestal, and the plasma is moved towards the chip.
It is preferred that, the semiconductor processing equipment includes Pvd equipment.
It is preferred that, the semiconductor processing equipment includes plasma etch apparatus.
The invention has the advantages that：
The dead ring that the present invention is provided, it includes ring body, and the ring body has second
Loading end and annular boss, wherein, the second loading end is relative with the fringe region of chip lower surface
Set, annular boss is looped around the second loading end edge, and the upper surface of annular boss is higher than
The upper surface of chip.After mutually being collided due to the ion in pre-cleaning cavity and particle, ion
It can be moved with certain scattering angle, therefore, by making the upper surface of annular boss be higher than chip
Upper surface, annular boss can be made effectively to stop the ion motion of a part of scattering angle extremely
The edge of chip, so as to reduce the ion concentration for the edge for moving to chip.So,
Even if the electric-field intensity for being distributed in wafer edge is bigger than normal, but is due to the edge for moving to chip
The ion concentration at place reduces, and the degree that the etch rate of wafer edge region is improved can also be reduced,
So as to reduce the etch rate of wafer edge region and the etch rate of wafer central region
Between difference, and then etching homogeneity can be improved.
The pre-cleaning cavity that the present invention is provided, its dead ring provided by using the present invention,
The etch rate of wafer edge region can be reduced, so as to reduce the quarter of wafer edge region
The difference between speed and the etch rate of wafer central region is lost, and then it is equal to improve etching
Even property.
The semiconductor processing equipment that the present invention is provided, its by using the present invention provide it is pre- clear
Chamber is washed, the etch rate of wafer edge region can be reduced, so as to reduce Waffer edge
Difference between the etch rate in region and the etch rate of wafer central region, and then can carry
High etching homogeneity.
Brief description of the drawings
Fig. 1 is the sectional view of existing pre-cleaning cavity；
Fig. 2 is the sectional view of existing dead ring；
Fig. 3 is the chip radial etch rate that technique acquisition is carried out using existing dead ring
Distribution map；
Fig. 4 is the sectional view of dead ring provided in an embodiment of the present invention；
Fig. 5 carries out technique acquisition for the dead ring that existing and the present embodiment is provided is respectively adopted
Chip radial etch rate distribution map；And
Fig. 6 is a kind of point for the chip radial etch rate that technique acquisition is carried out using dead ring
Butut.
Embodiment
To make those skilled in the art more fully understand technical scheme, tie below
The dead ring, pre-cleaning cavity and semiconductor processing equipment for closing accompanying drawing to provide the present invention are carried out
It is described in detail.
Fig. 4 is the sectional view of dead ring provided in an embodiment of the present invention.Referring to Fig. 4, insulation
Ring 12 is applied in pre-cleaning cavity (not shown), and the pre-cleaning cavity is used to use
Etching technics removes the impurity of wafer surface, and it includes pedestal 10, and the pedestal 10 includes being used for
First loading end 101 of the central area of the lower surface of bearing wafer 11, and annular groove,
The annular groove is arranged on the edge of the first loading end 101.
Dead ring 12 includes ring body, and the ring body is arranged on above-mentioned annular groove,
And the edge of the first loading end 101 is looped around, and ring body has the second loading end
121 and annular boss 122, wherein, annular boss 122 is looped around the side of the second loading end 121
At edge, and upper surface of the upper surface higher than chip 11 of annular boss 122.Due to prerinse
After ion in chamber is mutually collided with particle, ion can be moved with certain scattering angle,
Therefore, by making the upper surface of annular boss 122 be higher than the upper surface of chip 11, it can make
Annular boss 122 effectively stops the ion motion of a part of scattering angle to the edge of chip 11
Place, as shown in figure 4, scattering angle be less than a ° ion can by annular boss 122 stop,
And the edge of chip 11 can not be moved to.So as to reduce the edge for moving to chip 11
The ion concentration at place.So, even if the electric-field intensity for being distributed in wafer edge is bigger than normal, still
Because the ion concentration for the edge for moving to chip 11 reduces, the etching speed of wafer edge region
The degree that rate is improved can also be reduced, so as to reduce the etch rate and crystalline substance of wafer edge region
Difference between the etch rate of piece central area, and then etching homogeneity can be improved.
It is preferred that, it is vertical between the upper surface of annular boss 122 and the second loading end 121
Spacing H span is in 3~5mm.It is found through experiments that, it is exhausted using within the range
The etching homogeneity that edge ring carries out technique is preferable.As shown in figure 5, for be respectively adopted it is existing and
The dead ring that the present embodiment is provided carries out the distribution map of the chip radial etch rate of technique acquisition.
Ordinate is etch rate, and abscissa is the position of chip radially.Curve one is using existing
Carry out technique acquisition chip radial etch rate curve；Curve two is carried using the present embodiment
The dead ring of confession carries out the chip radial etch rate curve of technique acquisition.Found by contrasting,
For curve one, the etch rate of wafer edge region apparently higher than central area so that using
The etching homogeneity that existing dead ring carries out technique is poor.For curve two, wafer edge region
Difference between the etch rate in domain and the etch rate of wafer central region is smaller, so that using
The dead ring that the present embodiment is provided carries out the etching homogeneity of technique.
But, if vertical spacing H is higher than 6mm, as shown in fig. 6, to use vertical spacing
Dead rings of the H higher than 6mm carries out the chip radial etch rate curve of technique acquisition.Chip
The etch rate of fringe region can be less than wafer central region etch rate, etching homogeneity compared with
Difference.
In addition, the second loading end 121 be preferably plane, and with the edge of the lower surface of chip 11
Region is relative to be contacted, so as to so that the whole lower surface of chip 11 is placed in plane,
So as to avoid the lower surface of chip 11 by plasma etching.It is further preferred that annular
The inner peripheral surface 123 of boss 122 is mutually perpendicular to the second loading end 121, and this can strengthen annular
Boss 122 stop ion motion to the edge of the lower surface of chip 11 effect, so as to
The lower surface of chip 11 is further avoided by plasma etching.
As another technical scheme, the embodiment of the present invention also provides a kind of pre-cleaning cavity,
Its mode for being preferred to use inductively excites to form plasma.The pre-cleaning cavity includes setting
Pedestal and dead ring in it are put, wherein, pedestal includes the loading end for bearing wafer,
Dead ring is arranged on pedestal, and is looped around the edge of the loading end.Also, dead ring is adopted
Above-mentioned dead ring is provided with the embodiment of the present invention.
Pre-cleaning cavity provided in an embodiment of the present invention, it is carried by using the embodiment of the present invention
The above-mentioned dead ring supplied, can reduce the etch rate of wafer edge region, so as to reduce
Difference between the etch rate of wafer edge region and the etch rate of wafer central region, enters
And etching homogeneity can be improved.
As another technical scheme, a kind of semiconductor machining that the embodiment of the present invention is also provided
Equipment, it includes pre-cleaning cavity, is provided with coil at the top of the pre-cleaning cavity, passes through
Radio-frequency power is loaded to the coil, to excite the reacting gas formation plasma in pre-cleaning cavity
Body.Moreover, pre-cleaning cavity uses above-mentioned pre-cleaning cavity provided in an embodiment of the present invention, and
And rf bias is loaded by the pedestal into the pre-cleaning cavity, and make plasma towards crystalline substance
Piece is moved, to remove the impurity in wafer surface.Above-mentioned semiconductor processing equipment can be applied
Pvd equipment or plasma etch apparatus etc. possess setting for pre-cleaning cavity
It is standby.
Semiconductor processing equipment provided in an embodiment of the present invention, it is implemented by using the present invention
The pre-cleaning cavity that example is provided, can reduce the etch rate of wafer edge region, so as to
Reduce the difference between the etch rate of wafer edge region and the etch rate of wafer central region
It is different, and then etching homogeneity can be improved.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and
The illustrative embodiments of use, but the invention is not limited in this.For in the art
For those of ordinary skill, without departing from the spirit and substance in the present invention, it can do
Go out all variations and modifications, these variations and modifications are also considered as protection scope of the present invention.
Claims (9)
1. a kind of dead ring, is applied in pre-cleaning cavity, set in the pre-cleaning cavity
Pedestal is equipped with, the pedestal includes the first carrying of the central area for bearing wafer lower surface
Face；The dead ring is arranged on the pedestal, and is looped around the edge of first loading end
Place, it is characterised in that the dead ring includes ring body, the ring body has second
Loading end and annular boss, wherein,
The fringe region of second loading end and the chip lower surface is oppositely arranged；
The annular boss is looped around the second loading end edge, and the annular boss
Upper surface be higher than the chip upper surface.
2. dead ring according to claim 1, it is characterised in that second carrying
Face is plane, and is in contact with the fringe region of the chip lower surface.
3. dead ring according to claim 2, it is characterised in that the annular boss
Inner peripheral surface be mutually perpendicular to second loading end.
4. dead ring according to claim 1, it is characterised in that the annular boss
Upper surface and second loading end between vertical spacing span in 3~5mm.
5. dead ring according to claim 1, it is characterised in that the pedestal includes
Annular groove, the annular groove is arranged on the edge of first loading end；The annular
Body is arranged on the annular groove.
6. a kind of pre-cleaning cavity, including the pedestal and dead ring set within it, the base
Seat includes the loading end for bearing wafer, and the dead ring is arranged on the pedestal, and ring
It is wound on the edge of the loading end；Characterized in that, the dead ring uses claim
Dead ring described in 1-5 any one.
7. a kind of semiconductor processing equipment, including pre-cleaning cavity, in the pre-cleaning cavity
Top be provided with coil, it is described pre- clear to excite by loading radio-frequency power to the coil
The reacting gas formation plasma washed in chamber, it is characterised in that the pre-cleaning cavity is adopted
With the pre-cleaning cavity described in claim 6, also, it is inclined by loading radio frequency to the pedestal
Pressure, and the plasma is moved towards the chip.
8. semiconductor processing equipment according to claim 7, it is characterised in that described
Semiconductor processing equipment includes Pvd equipment.
9. semiconductor processing equipment according to claim 7, it is characterised in that described
Semiconductor processing equipment includes plasma etch apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610227636.9A CN107293505A (en) | 2016-04-13 | 2016-04-13 | Dead ring, pre-cleaning cavity and semiconductor processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610227636.9A CN107293505A (en) | 2016-04-13 | 2016-04-13 | Dead ring, pre-cleaning cavity and semiconductor processing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107293505A true CN107293505A (en) | 2017-10-24 |
Family
ID=60093685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610227636.9A Pending CN107293505A (en) | 2016-04-13 | 2016-04-13 | Dead ring, pre-cleaning cavity and semiconductor processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107293505A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109473333A (en) * | 2018-10-08 | 2019-03-15 | 深圳市华星光电半导体显示技术有限公司 | Etching machine |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040050078A (en) * | 2002-12-09 | 2004-06-16 | 주식회사 하이닉스반도체 | Apparatus for driving focus ring of plasma etch chamber |
| US20050155718A1 (en) * | 2004-01-20 | 2005-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Step edge insert ring for etch chamber |
| CN1649105A (en) * | 2004-01-30 | 2005-08-03 | 松下电器产业株式会社 | Dry etching device and dry etching method |
| CN1845307A (en) * | 2005-12-16 | 2006-10-11 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Electrostatic chuck for accelerating wafer etching uniformity |
| CN101150044A (en) * | 2006-09-19 | 2008-03-26 | 东京毅力科创株式会社 | Focus ring and plasma processing apparatus |
| JP2012174997A (en) * | 2011-02-23 | 2012-09-10 | Mitsubishi Materials Corp | Part for plasma processing device, method for identification display imprinting |
| CN106876315A (en) * | 2015-12-14 | 2017-06-20 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Pressure ring, pre-cleaning cavity and semiconductor processing equipment |
-
2016
- 2016-04-13 CN CN201610227636.9A patent/CN107293505A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040050078A (en) * | 2002-12-09 | 2004-06-16 | 주식회사 하이닉스반도체 | Apparatus for driving focus ring of plasma etch chamber |
| US20050155718A1 (en) * | 2004-01-20 | 2005-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Step edge insert ring for etch chamber |
| CN1649105A (en) * | 2004-01-30 | 2005-08-03 | 松下电器产业株式会社 | Dry etching device and dry etching method |
| CN1845307A (en) * | 2005-12-16 | 2006-10-11 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Electrostatic chuck for accelerating wafer etching uniformity |
| CN101150044A (en) * | 2006-09-19 | 2008-03-26 | 东京毅力科创株式会社 | Focus ring and plasma processing apparatus |
| JP2012174997A (en) * | 2011-02-23 | 2012-09-10 | Mitsubishi Materials Corp | Part for plasma processing device, method for identification display imprinting |
| CN106876315A (en) * | 2015-12-14 | 2017-06-20 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Pressure ring, pre-cleaning cavity and semiconductor processing equipment |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109473333A (en) * | 2018-10-08 | 2019-03-15 | 深圳市华星光电半导体显示技术有限公司 | Etching machine |
| CN109473333B (en) * | 2018-10-08 | 2021-03-16 | 深圳市华星光电半导体显示技术有限公司 | Etching machine |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102035890B1 (en) | Etching processing method | |
| KR102418245B1 (en) | Plasma processing method and plasma processing apparatus | |
| KR102033979B1 (en) | Etching method and etching apparatus | |
| KR100381117B1 (en) | Plasma processing method and apparatus | |
| US20160148789A1 (en) | Pre-cleaning chamber and a semiconductor processing apparatus containing the same | |
| US20120267051A1 (en) | Inductively coupled plasma processing apparatus | |
| KR102132045B1 (en) | Gas supply method and plasma processing apparatus | |
| KR20120100750A (en) | Plasma processing apparatus | |
| CN106898534A (en) | Plasma confinement ring, plasma processing apparatus and processing method for substrate | |
| CN106876315B (en) | Compression ring, pre-cleaning chamber and semiconductor processing equipment | |
| KR102459959B1 (en) | Plasma system and filter device | |
| WO2004012235A3 (en) | Atmospheric pressure plasma processing reactor | |
| CN213660344U (en) | Plasma processing device | |
| CN105895488B (en) | The manufacturing method of plasma processing apparatus and electronic component | |
| US20220319816A1 (en) | Plasma etching system | |
| CN107293505A (en) | Dead ring, pre-cleaning cavity and semiconductor processing equipment | |
| JP2019087666A5 (en) | ||
| TW201834058A (en) | Reduced-pressure processing apparatus | |
| CN106653549B (en) | Semiconductor processing equipment | |
| CN206907751U (en) | A kind of bearing base and precleaning unit | |
| CN103165374B (en) | Plasma processing device and edge ring applied to plasma processing device | |
| KR20110096464A (en) | Multiple gas supply device and plasma processing device having the same | |
| TW201901731A (en) | Bearing base and pre-cleaning device | |
| CN109427551A (en) | A kind of substrate lithographic method and corresponding processing unit | |
| CN107403750B (en) | Base assembly and reaction chamber |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171024 |
|
| RJ01 | Rejection of invention patent application after publication |