CN107275347B - An array substrate, its preparation method and display panel - Google Patents

Abstract

The invention discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises: a gate electrode, an active layer, a source electrode and a drain electrode sequentially located on a base substrate; further comprising: a light blocking layer; the The orthographic projection of the active layer on the base substrate overlaps with the orthographic projection of the light blocking layer on the base substrate and the orthographic projection of the gate electrode on the base substrate; The orthographic projection of the source layer on the base substrate is located in the orthographic projection area of the light blocking layer and the gate on the base substrate; the orthographic projection area of the gate on the base substrate is smaller than that of the active layer on the base substrate. shadow area. In this way, the parasitic capacitance between the gate electrode and the source-drain electrodes can be reduced, and the active layer is shielded by the gate electrode and the light blocking layer, so as to avoid the problem of light leakage caused by the active layer due to light exposure.

Description

An array substrate, its preparation method and display panel

technical field

The present invention relates to the field of display technology, and in particular, to an array substrate, a preparation method thereof and a display panel.

Background technique

Compared with a traditional cathode ray display (CRT, Cathode ray tube), a liquid crystal display (LCD, Liquid Crystal Display) can be made smaller and lighter, and is currently widely used in televisions, mobile phones and display of public information. At present, in a liquid crystal display panel, an electric field can be generated on the liquid crystal layer by applying a voltage to two electrodes, and the transmittance of light passing through the liquid crystal layer can be adjusted by adjusting the intensity of the generated electric field, so that a display can be obtained. image.

The structure of the array substrate of the liquid crystal display panel is shown in FIG. 1, which mainly includes: a gate 2, a gate insulating layer 3, an active layer 4, a source electrode 5, a drain electrode 6, a pixel electrode 7, The passivation layer 8 and the common electrode 9; wherein, the gate electrode 2, the active layer 4, the source electrode 5 and the drain electrode 6 are mainly composed of a thin film transistor (TFT, ThinFilm Transistor) used to control the switch of each pixel. Due to the large overlapping area between the gate and the source-drain electrodes in the existing TFT, a large parasitic capacitance will be generated between the gate and the source-drain electrodes, and the large parasitic capacitance will make the liquid crystal display panel drive During the display process, the load is large, which will cause the problem of large power consumption of the display panel as a whole. In addition, as shown in FIG. 1 , when the TFT is turned off, a large amount of charges are induced in the channel region corresponding to the gate; and as shown in FIG. Therefore, as shown in Figure 3, the induced charges can contact the metal of the source electrode 5 and the drain electrode 6 on both sides, thereby forming a current path, which eventually leads to the problem of sidewall leakage of the display panel.

Therefore, how to reduce the power consumption of the display panel and improve the display effect of the display panel is an urgent problem to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide an array substrate, a method for manufacturing the same, and a display panel, so as to solve the problem of high power consumption of the display panel in the prior art.

An embodiment of the present invention provides an array substrate, comprising: a gate electrode, an active layer, a source electrode and a drain electrode sequentially located on a base substrate; further comprising: a light blocking layer;

The orthographic projection of the active layer on the base substrate overlaps with the orthographic projection of the light blocking layer on the base substrate and the orthographic projection of the gate on the base substrate ;

The orthographic projection of the active layer on the base substrate is located in the orthographic projection area of the light blocking layer and the gate on the base substrate;

The orthographic projection area of the gate electrode on the base substrate is smaller than the orthographic projection area of the active layer on the base substrate.

In a possible implementation manner, in the above array substrate provided by the embodiment of the present invention, the orthographic projection of the gate on the base substrate and the orthographic projection of the light blocking layer on the base substrate Do not overlap or partially overlap.

In a possible implementation manner, in the above-mentioned array substrate provided by the embodiment of the present invention, the light blocking layer is located between the base substrate and the gate electrode.

In a possible implementation manner, in the above-mentioned array substrate provided by the embodiment of the present invention, the shape of the source electrode is U-shaped.

In a possible implementation manner, in the above-mentioned array substrate provided by the embodiment of the present invention, the material of the light blocking layer is a metal material.

In a possible implementation manner, the above-mentioned array substrate provided in the embodiment of the present invention further includes: a pixel electrode, a passivation layer and a common electrode; wherein,

The pixel electrode is disposed in the same layer as the active layer and is electrically connected to the drain;

the passivation layer is located over the source electrode and the drain electrode;

The common electrode is located on the passivation layer.

An embodiment of the present invention provides a display panel including the above-mentioned array substrate provided by an embodiment of the present invention.

An embodiment of the present invention provides a method for preparing the above-mentioned array substrate provided by an embodiment of the present invention, including:

forming a pattern of the light blocking layer on the base substrate;

forming a pattern including the gate electrode, the active layer, the source electrode and the drain electrode on the base substrate on which the pattern of the light blocking layer is formed;

in,

The orthographic projection of the active layer on the base substrate overlaps with the orthographic projection of the light blocking layer on the base substrate and the orthographic projection of the gate on the base substrate ;

The orthographic projection of the active layer on the base substrate is located in the orthographic projection area of the light blocking layer and the gate on the base substrate;

The orthographic projection area of the gate electrode on the base substrate is smaller than the orthographic projection area of the active layer on the base substrate.

In a possible implementation, in the above-mentioned preparation method provided by the embodiment of the present invention, the orthographic projection of the gate on the base substrate and the orthographic projection of the light blocking layer on the base substrate Do not overlap or partially overlap.

In a possible implementation, the above-mentioned preparation method provided in the embodiment of the present invention further includes:

On the base substrate on which the pattern of the light blocking layer is formed, a pattern including the pixel electrode, the passivation layer and the common electrode is formed.

The beneficial effects of the embodiments of the present invention include:

Embodiments of the present invention provide an array substrate, a preparation method thereof, and a display panel. The array substrate includes: a gate electrode, an active layer, a source electrode and a drain electrode sequentially located on a base substrate; and further includes: a light blocking layer; The orthographic projection of the active layer on the base substrate overlaps with the orthographic projection of the light blocking layer on the base substrate and the orthographic projection of the gate on the base substrate , the orthographic projection of the active layer on the base substrate is located in the orthographic projection area of the light blocking layer and the gate on the base substrate; the orthographic projection area of the gate on the base substrate is smaller than that of the active layer on the base substrate the orthographic projection area of . In this way, in the present invention, by arranging a light-blocking layer on the base substrate, both the light-blocking layer and the gate electrode have overlapping areas with the active layer, so that the overlapping area between the gate electrode and the active layer can be reduced, thereby reducing the size of the gate electrode and the active layer. The overlapping area between the electrode and the source-drain electrode, that is, the width of the gate is reduced by adding a light-blocking layer, so that the overlapping area of the gate and the source-drain electrode is reduced, and the parasitic capacitance between the gate and the source-drain electrode is reduced. Thereby, the power consumption of the display panel is reduced; at the same time, the orthographic projection of the active layer on the base substrate is arranged in the orthographic projection area of the gate and the light-blocking layer on the base substrate, so that the gate and the light-blocking layer can block the The source layer can avoid the problem of photo-generated carriers, that is, optical leakage, caused by the active layer due to light exposure.

Description of drawings

1 is a schematic structural diagram of an array substrate in the prior art;

2 is a schematic plan view of an array substrate in the prior art;

3 is a schematic diagram of an induced charge distribution in a channel region in the prior art;

FIG. 4 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention;

FIG. 5 is a schematic plan view of an array substrate provided by an embodiment of the present invention;

6 is a schematic diagram of an induced charge distribution in a track region provided by an embodiment of the present invention;

FIG. 7 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention;

8a-8g are schematic diagrams of a preparation process of an array substrate according to an embodiment of the present invention, respectively.

Detailed ways

The specific implementations of the array substrate, the manufacturing method thereof, and the display panel provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

An embodiment of the present invention provides an array substrate, as shown in FIG. 4 , which may include: a gate electrode 02 , an active layer 03 , a source electrode 04 and a drain electrode 05 sequentially located on a base substrate 01 ; and may further include: a blocking Optical layer 06; the orthographic projection of the active layer 03 on the base substrate 01 and the orthographic projection of the light blocking layer 06 on the base substrate 01 and the gate 02 on the base substrate 01 The orthographic projections on the base plate 03 are overlapped; the orthographic projection of the active layer 03 on the base substrate 01 is located in the orthographic projection area of the light blocking layer 06 and the gate 02 on the base substrate; the gate 02 is on the base substrate 01 The orthographic projection area on the substrate 01 is smaller than the orthographic projection area of the active layer 03 on the base substrate 01 .

In the above-mentioned array substrate provided by the embodiment of the present invention, by disposing the light blocking layer 06 on the base substrate, the light blocking layer 06 and the gate 02 both have overlapping regions with the active layer 03, as shown in FIG. The A-A cutting line in the top view 5 can be cut, and the cross-sectional view 4) can be obtained, so that the overlapping area between the gate and the active layer can be reduced, and the overlapping area between the gate and the source and drain electrodes can be reduced, that is, by adding a light blocking layer. To reduce the width of the gate, reduce the overlapping area between the gate and the source-drain electrodes, reduce the parasitic capacitance between the gate and the source-drain electrodes, thereby reducing the power consumption of the display panel; at the same time, the active layer is arranged on the substrate The orthographic projection on the substrate is located in the orthographic projection area of the gate and the light-blocking layer on the substrate, so that the active layer can be completely blocked by the gate and the light-blocking layer in the direction perpendicular to the substrate to avoid active The problem of photo-generated carriers, that is, light leakage, occurs when the layer is exposed to light. Moreover, as shown in Figure 6, after the width of the gate is reduced, the charges induced in the active layer only exist in the area facing the gate, which can reduce the direct contact between the induced charges and the source and drain, reducing the Hole leakage, thereby improving the leakage problem of the sidewall of the display panel.

During specific implementation, in the above-mentioned array substrate provided by the embodiments of the present invention, the orthographic projection of the gate on the base substrate may be set to partially overlap or not overlap with the orthographic projection of the light blocking layer on the base substrate. Specifically, in the above-mentioned array substrate provided by the embodiment of the present invention, the gate electrode and the light-blocking layer are set to be non-overlapping, so that the overlapping region of the gate electrode and the source and drain electrodes can overlap with the light-blocking layer and the source and drain electrodes. There is no overlap in the area of the source and drain, so that the area overlapping the source and drain can be shared by the light blocking layer and the gate, thereby reducing the width of the gate, thereby reducing the overlap between the gate and the source and drain, thereby reducing the gate and the gate. The parasitic capacitance between the source and drain electrodes reduces the power consumption of the display panel; at the same time, the light blocking layer and the gate do not overlap, and parasitic capacitance can also be avoided from being formed between the light blocking layer and the gate.

During specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, the light blocking layer may be located between the base substrate and the gate, and the shape of the source may be set to be U-shaped. Specifically, in the above-mentioned array substrate provided by the embodiment of the present invention, as shown in FIG. 2 , most areas of the two U-shaped source electrodes 5 connected in series overlap with the gate electrode 2 , so that there is a gap between the gate electrode and the source electrode. Because the overlapping area is too large, the parasitic capacitance is too large. Therefore, in the present invention, a light-blocking layer is provided. As shown in FIG. The shielding of the layer 03, so that the gate 02 does not need to be made too large, resulting in the overlap with the U-shaped source 04, thereby effectively reducing the parasitic capacitance between the gate and the source electrode, and reducing the power consumption of the display panel.

During specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, the material of the light blocking layer may be an opaque metal material. Specifically, in the above-mentioned array substrate provided by the embodiment of the present invention, the light-blocking layer is made of a non-light-transmitting metal material, which can not only block the influence of external light on the active layer, prevent the active layer from generating photo-generated carriers, but also can The overlapping area between the gate and the source-drain electrodes is reduced, thereby reducing the parasitic capacitance between the gate and the source-drain electrodes, thereby reducing the power consumption of the display panel.

In the specific implementation, the light-blocking layer can be floated; it can also be connected to corresponding signals, for example, the common electrode signal can be input as a common electrode line, or the touch signal can also be connected. According to actual needs, the light-blocking layer can be connected with other functional layers at the same time. For example, it can be made through the same patterning process as the common electrode line or the touch lead, which is not limited in this application.

During specific implementation, the above-mentioned array substrate provided in the embodiment of the present invention, as shown in FIG. 4 , may further include: pixel electrode 07 , passivation layer 08 and common electrode 09 ; wherein, the pixel electrode 07 and the active layer are in the same layer The passivation layer 08 is located on the source electrode 04 and the drain electrode 05 ; the common electrode 09 is located on the passivation layer 08 . Specifically, the above-mentioned array substrate provided by the embodiment of the present invention further includes a plurality of necessary film layer structures such as pixel electrodes, passivation layers, and common electrodes, so as to realize the driving and display function of the array substrate. The function and structure design of each film layer are the same as in the prior art, and will not be described in detail here.

Based on the same inventive concept, an embodiment of the present invention provides a display panel including the above-mentioned array substrate provided by an embodiment of the present invention. The display panel can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator. Since the principle of solving the problem of the display panel is similar to that of the array substrate, the implementation of the display panel can refer to the implementation of the above-mentioned array substrate, and the repetition will not be repeated.

Based on the same inventive concept, an embodiment of the present invention provides a method for preparing the above-mentioned array substrate provided by an embodiment of the present invention, as shown in FIG. 7 , which may specifically include:

S101, forming a pattern of a light blocking layer on a base substrate;

S102, forming a pattern including a gate electrode, an active layer, a source electrode and a drain electrode on the base substrate on which the pattern of the light blocking layer is formed;

Wherein, the orthographic projection of the active layer on the base substrate, the orthographic projection of the light blocking layer on the base substrate, and the orthographic projection of the gate on the base substrate are both overlapping; the orthographic projection of the active layer on the base substrate is located in the orthographic projection area of the light blocking layer and the gate on the base substrate;

The orthographic projection area of the gate on the base substrate is smaller than the orthographic projection area of the active layer on the base substrate.

The above-mentioned preparation method provided by the embodiment of the present invention may further include a process of fabricating a plurality of necessary film layers such as a pixel electrode, a passivation layer, and a common electrode. Specifically, the fabrication process of each film layer is as follows:

The first step: forming a pattern of the light-blocking layer 06 on the base substrate 01 through a patterning process, and the base substrate for forming the light-blocking layer is shown in FIG. 8a;

The second step: forming the pattern of the gate 02 on the base substrate 01 formed with the light blocking layer 06 through a patterning process, which also includes forming the pattern of the insulating layer 10; the base substrate for forming the gate is shown in Figure 8b;

The third step: forming a pattern of the active layer 03 on the base substrate 01 formed with the gate 02 through a patterning process, which also includes forming the pattern of the gate insulating layer 11; the base substrate for forming the active layer is shown in Figure 8c Show;

The fourth step: forming the pattern of the pixel electrode 07 on the base substrate 01 on which the active layer 03 is formed by a patterning process; the base substrate for forming the pixel electrode is shown in FIG. 8d;

The fifth step: forming the pattern of the source electrode 04 and the drain electrode 05 on the base substrate 01 formed with the pixel electrode 07 through a patterning process; the base substrate for forming the source electrode and the drain electrode is shown in FIG. 8e;

The sixth step: forming a pattern of the passivation layer 08 on the base substrate 01 on which the source electrode 04 and the drain electrode 05 are formed by a patterning process; the base substrate for forming the passivation layer is shown in FIG. 8f;

The seventh step: forming the pattern of the common electrode 09 on the base substrate 01 formed with the passivation layer 08 through a patterning process; the base substrate for forming the common electrode is shown in FIG. 8g.

In the above-mentioned preparation method provided by the embodiment of the present invention, by fabricating a light-blocking layer on the base substrate, both the light-blocking layer and the gate electrode have overlapping regions with the active layer, so that the difference between the gate electrode and the active layer can be reduced. The overlap area, thereby reducing the overlap area between the gate and the source-drain electrodes, that is, by increasing the light-blocking layer to reduce the width of the gate, so that the overlap area between the gate and the source-drain electrodes is reduced, and the gate and the source are reduced. The parasitic capacitance between the drain electrodes reduces the power consumption of the display panel; at the same time, the orthographic projection of the active layer on the substrate is located in the orthographic projection area of the gate and the light-blocking layer on the substrate, so that the vertical In the direction of the base substrate, the gate electrode and the light blocking layer completely shield the active layer, so as to avoid the problem that the active layer generates photo-generated carriers due to light exposure, that is, light leakage.

In specific implementation, in the above-mentioned preparation method provided by the embodiment of the present invention, the orthographic projection of the gate formed on the base substrate does not overlap or partially overlaps with the orthographic projection of the light blocking layer on the base substrate. Specifically, the gate and the light-blocking layer are set to be non-overlapping, so that the overlapped region of the gate and the source-drain and the overlapped region of the light-blocking layer and the source-drain are not overlapped. The overlapping area is shared by the light blocking layer and the gate, thereby reducing the width of the gate, thereby reducing the overlap between the gate and the source and drain electrodes, thereby reducing the parasitic capacitance between the gate and the source and drain electrodes, reducing the display The power consumption of the panel; at the same time, the light blocking layer and the gate do not overlap, and the formation of parasitic capacitance between the light blocking layer and the gate can also be avoided.

Embodiments of the present invention provide an array substrate, a preparation method thereof, and a display panel. The array substrate includes: a gate electrode, an active layer, a source electrode and a drain electrode sequentially located on a base substrate; and further includes: a light blocking layer; The orthographic projection of the active layer on the base substrate overlaps with the orthographic projection of the light blocking layer on the base substrate and the orthographic projection of the gate on the base substrate ; the orthographic projection of the active layer on the base substrate is located in the orthographic projection area of the light blocking layer and the gate on the base substrate; the orthographic projection area of the gate on the base substrate is smaller than that of the active layer on the base substrate the orthographic projection area of . In this way, in the present invention, by arranging a light-blocking layer on the base substrate, the light-blocking layer and the gate electrode both have overlapping areas with the active layer, so that the overlapping area between the gate electrode and the active layer can be reduced, thereby reducing the size of the gate electrode and the active layer. The overlapping area between the electrode and the source-drain electrode, that is, the width of the gate is reduced by adding a light-blocking layer, so that the overlapping area of the gate and the source-drain electrode is reduced, and the parasitic capacitance between the gate and the source-drain electrode is reduced. Therefore, the power consumption of the display panel is reduced; at the same time, the orthographic projection of the active layer on the base substrate is located in the orthographic projection area of the gate and the light-blocking layer on the base substrate, so that the gate and the light-blocking layer can block the The source layer can avoid the problem of photo-generated carriers, that is, optical leakage, caused by the active layer due to light exposure.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (9)

1. An array substrate, comprising: the grid electrode, the active layer, the source electrode and the drain electrode are sequentially positioned on the substrate; it is characterized by also comprising: a light-blocking layer;

the orthographic projection of the active layer on the substrate base plate is overlapped with the orthographic projection of the light blocking layer on the substrate base plate and the orthographic projection of the grid electrode on the substrate base plate;

the orthographic projection of the active layer on the substrate is positioned in an orthographic projection area of the light blocking layer and the grid electrode on the substrate;

the orthographic projection area of the grid electrode on the substrate is smaller than that of the active layer on the substrate;

the orthographic projection of the grid electrode on the substrate base plate is not overlapped with the orthographic projection of the light blocking layer on the substrate base plate;

wherein the light blocking layer is arranged in a region corresponding to the surrounding of the grid electrode.

2. The array substrate of claim 1, wherein the light blocking layer is between the substrate and the gate electrode.

3. The array substrate of claim 1, wherein the source electrode is U-shaped.

4. The array substrate of any of claims 1-3, wherein the light blocking layer is made of a metal material.

5. The array substrate of claim 4, further comprising: a pixel electrode, a passivation layer and a common electrode; wherein,

the pixel electrode and the active layer are arranged on the same layer and are electrically connected with the drain electrode;

the passivation layer is positioned above the source electrode and the drain electrode;

the common electrode is located on the passivation layer.

6. A method for preparing the array substrate according to any one of claims 1 to 5, comprising:

forming a pattern of the light blocking layer on the substrate base plate;

forming a pattern including the gate electrode, the active layer, the source electrode and the drain electrode on the substrate on which the pattern of the light blocking layer is formed;

wherein, the orthographic projection of the active layer on the substrate base plate is overlapped with the orthographic projection of the light blocking layer on the substrate base plate and the orthographic projection of the grid electrode on the substrate base plate;

the orthographic projection of the active layer on the substrate is positioned in an orthographic projection area of the light blocking layer and the grid electrode on the substrate;

the orthographic projection area of the grid electrode on the substrate is smaller than that of the active layer on the substrate.

7. The method according to claim 6, wherein an orthographic projection of the gate electrode on the substrate base plate does not overlap or partially overlaps with an orthographic projection of the light-blocking layer on the substrate base plate.

8. The method of claim 6 or 7, further comprising:

and forming a pattern comprising a pixel electrode, a passivation layer and a common electrode on the substrate with the pattern of the light blocking layer.

9. A display panel comprising the array substrate according to any one of claims 1 to 5.

Images