CN107272822A - A kind of system clock monitoring method and device - Google Patents

Abstract

The present invention provides a system clock monitoring method and device. The method includes: performing frequency modulation processing on the clock cycle of the clock to be monitored according to the preset target clock cycle to obtain the first clock cycle; The frequency modulation process is performed on the clock cycle to obtain the second clock cycle; in each first clock cycle, at least one check data is stored in the storage space with a preset capacity; in each second clock cycle, read from the storage space Take at least one check data stored earlier, and delete at least one check data read from the storage space; according to at least two check data read in two consecutive second clock cycles, it is judged that the Check whether the clock is abnormal. The invention provides a system clock monitoring method and device, which can monitor the system clock.

Description

A system clock monitoring method and device

technical field

The invention relates to the technical field of computers, in particular to a system clock monitoring method and device.

Background technique

The system clock is a very important part of the server system, and it is mostly used in the server as the CPU, the integrated south bridge (Platform Controller Hub, PCH), the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCI-E) slot and the base board A management controller (Baseboard Management Controller, BMC) device provides a clock.

The system clock needs to meet certain frequency requirements. When the system clock frequency exceeds the allowable range, the server will be inaccurate or even down due to abnormal system clock. Therefore, it is necessary to monitor the system clock to ensure that the server can run normally.

At present, general servers cannot monitor the system clock, and can only verify whether the system clock is abnormal through manual timing.

Contents of the invention

Embodiments of the present invention provide a system clock monitoring method and device, which can monitor the system clock.

In a first aspect, an embodiment of the present invention provides a system clock monitoring method, including:

According to the preset target clock cycle, frequency modulation is performed on the clock cycle of the clock to be monitored to obtain the first clock cycle;

performing frequency modulation processing on the clock cycle of the reference clock according to the target clock cycle to obtain a second clock cycle;

In each of the first clock cycles, at least one verification data is stored in a storage space with a preset capacity, wherein when the capacity of the storage space is insufficient, the data with a longer storage time is overwritten;

In each of the second clock cycles, read at least one of the verification data stored earlier from the storage space, and transfer the read at least one of the verification data from the storage space Delete in, wherein, when the verification data does not exist in the storage space, read specific data as the verification data;

Whether the clock to be monitored is abnormal is determined according to at least two verification data read in two consecutive cycles of the second clock.

Preferably, the judging whether the clock to be monitored is abnormal according to at least two verification data read in two consecutive cycles of the second clock includes:

determining an association relationship between at least two check data stored in the storage space in two consecutive first clock cycles;

judging whether at least two of the verification data read in two consecutive second clock cycles conform to the association relationship;

If yes, it is determined that the clock to be monitored is normal; otherwise, it is determined that the clock to be monitored is abnormal.

Preferably, the judging whether the clock to be monitored is abnormal according to at least two verification data read in two consecutive cycles of the second clock includes:

determining an association relationship between at least two check data stored in the storage space in two consecutive first clock cycles;

judging whether at least two of the verification data read in two consecutive second clock cycles conform to the association relationship, and if not, recording an abnormality of the verification data once;

Judging whether the time interval between the abnormality of the verification data recorded this time and the abnormality of the verification data recorded last time is less than the preset duration threshold, if yes, determine that the clock to be monitored is abnormal, otherwise determine The clock to be monitored is normal.

Preferably, after recording the abnormality of the verification data once, further comprising:

suspending execution of the at least one verification data stored earlier from the storage space at each second clock cycle, and restarting execution of the verification data after the pause duration reaches a preset buffer duration Read at least one of the verification data stored earlier from the storage space in each second clock cycle;

Wherein, the buffer duration is greater than or equal to one cycle of the second clock.

Preferably, the frequency modulation process is performed on the clock cycle of the clock to be monitored according to the preset target clock cycle to obtain the first clock cycle, including:

Determine the first frequency modulation parameter according to the ratio of the preset target clock period to the standard clock period of the clock to be monitored, and use the first frequency modulation parameter to scale the actual clock period of the clock to be monitored to obtain the first clock period ;

According to the target clock cycle, performing frequency modulation processing on the clock cycle of the reference clock to obtain the second clock cycle includes:

A second frequency modulation parameter is determined according to a preset ratio of the target period to the clock period of the reference clock, and the second frequency modulation parameter is used to scale the clock period of the reference clock to obtain the second clock period.

Preferably, before storing at least one verification data in a storage space with a preset capacity at each first clock cycle, further comprising:

At least one piece of buffer data conforming to the association relationship is sequentially stored in the storage space.

In a second aspect, an embodiment of the present invention provides a system clock monitoring device, including: a frequency modulation processing unit, a storage unit, a reading unit, and a judging unit;

The frequency modulation processing unit is configured to perform frequency modulation processing on the clock cycle of the clock to be monitored according to the preset target clock cycle to obtain the first clock cycle, and is also used to perform frequency modulation on the clock cycle of the reference clock according to the target clock cycle Frequency modulation processing to obtain the second clock cycle;

The storage unit is configured to store at least one check data in a storage space with a preset capacity at each first clock cycle acquired by the frequency modulation processing unit, wherein the capacity of the storage space is insufficient Overwrite the data that has been stored for a long time;

The reading unit is configured to read at least one of the verification data stored earlier by the storage unit from the storage space at each second clock cycle acquired by the frequency modulation processing unit, and deleting the at least one read check data from the storage space, wherein, when the check data does not exist in the storage space, read specific data as the check data ;

The judging unit is configured to judge whether the clock to be monitored is abnormal according to at least two verification data read by the reading unit in two consecutive cycles of the second clock.

Preferably, the judging unit includes: a first determining subunit and a first judging subunit;

The first determination subunit is configured to determine an association relationship between at least two check data stored in the storage space in two consecutive first clock cycles;

The first judging subunit is configured to judge whether at least two check data read in two consecutive second clock cycles conform to the association relationship determined by the first determining subunit, if Yes, it is determined that the clock to be monitored is normal; otherwise, it is determined that the clock to be monitored is abnormal.

Preferably, the judging unit includes: a second determining subunit and a second judging subunit;

The second determination subunit is configured to determine an association relationship between at least two verification data stored in the storage space during two consecutive first clock cycles;

The second judging subunit is configured to judge whether at least two check data read in two consecutive second clock cycles conform to the association relationship determined by the second determining subunit, if No, record the abnormality of the verification data once, and it is also used to judge whether the time interval between the abnormality of the verification data recorded this time and the abnormality of the verification data recorded last time is less than the preset duration threshold, if Yes, it is determined that the clock to be monitored is abnormal; otherwise, it is determined that the clock to be monitored is normal.

Preferably, the second judging subunit is further configured to trigger the reading unit after an abnormality occurs in the verification data recorded once;

The reading unit is further configured to, when receiving the trigger of the second judging subunit, suspend the execution of the reading of at least one stored earlier from the storage space in each second clock cycle. The verification data, and after the pause time reaches the preset buffer time, restart the execution of reading at least one of the calibration data stored earlier from the storage space in each second clock cycle. test data, wherein the buffering duration is greater than or equal to one cycle of the second clock.

Preferably, the frequency modulation processing unit is configured to determine a first frequency modulation parameter according to the ratio of a preset target clock period to a standard clock period of the clock to be monitored, and use the first frequency modulation parameter to determine the frequency of the clock to be monitored. The actual clock cycle is scaled to obtain the first clock cycle, which is also used to determine the second frequency modulation parameter according to the ratio of the preset target cycle to the clock cycle of the reference clock, and use the second frequency modulation parameter to the reference clock The clock period is scaled to obtain a second clock period.

Preferably, the storage unit is further configured to sequentially store at least one buffer data conforming to the association relationship in the storage space.

In the embodiment of the present invention, in order to have comparable clock periods of the clock to be monitored and the reference clock, according to the preset target clock period, the frequency of the clock period to be monitored is adjusted to the first clock period, and the clock period of the reference clock The cycle frequency is adjusted to the second clock cycle, and at least one check data is stored in the storage space at each first clock cycle, in order to read at least one check data stored earlier from the storage space at each second clock cycle. verification data, due to the limited capacity of the storage space, when the first clock cycle is different from the second clock cycle, the verification data in the storage space will overflow or the verification data does not exist, so that the verification data read from the storage space The experimental data produced corresponding changes. Therefore, it can be determined whether the first clock period and the second clock period are the same through the verification data read from the storage space, so as to determine whether the clock to be monitored is abnormal, and monitor the system clock.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a flow chart of a system clock monitoring method provided by an embodiment of the present invention;

FIG. 2 is a flow chart of another system clock monitoring method provided by an embodiment of the present invention;

Fig. 3 is a flowchart of another system clock monitoring method provided by an embodiment of the present invention;

Fig. 4 is a flowchart of another system clock monitoring method provided by an embodiment of the present invention;

Fig. 5 is a schematic structural diagram of a system clock monitoring device provided by an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of another system clock monitoring device provided by an embodiment of the present invention;

Fig. 7 is a schematic structural diagram of another system clock monitoring device provided by an embodiment of the present invention.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection of the present invention. scope.

As shown in FIG. 1, an embodiment of the present invention provides a system clock monitoring method, which may include the following steps:

Step 101: Perform frequency modulation processing on the clock cycle of the clock to be monitored according to the preset target clock cycle to obtain the first clock cycle;

Step 102: Perform frequency modulation processing on the clock cycle of the reference clock according to the target clock cycle to obtain a second clock cycle;

Step 103: At each first clock cycle, store at least one verification data in a storage space with a preset capacity, wherein when the capacity of the storage space is insufficient, overwrite the data with a longer storage time;

Step 104: At each second clock cycle, read at least one of the verification data stored earlier from the storage space, and transfer the read at least one of the verification data from the Delete in the storage space, wherein, when the verification data does not exist in the storage space, read specific data as the verification data;

Step 105: Determine whether the clock to be monitored is abnormal according to at least two verification data read in two consecutive cycles of the second clock.

In the embodiment of the present invention, in order to have comparable clock periods of the clock to be monitored and the reference clock, according to the preset target clock period, the frequency of the clock period to be monitored is adjusted to the first clock period, and the clock period of the reference clock The cycle frequency is adjusted to the second clock cycle, and at least one check data is stored in the storage space at each first clock cycle, in order to read at least one check data stored earlier from the storage space at each second clock cycle. verification data, due to the limited capacity of the storage space, when the first cycle is different from the second cycle, the verification data in the storage space will overflow or the verification data does not exist, so that the verification data read from the storage space produce corresponding changes. Therefore, it can be determined whether the first clock period and the second clock period are the same through the verification data read from the storage space, so as to determine whether the clock to be monitored is abnormal, and monitor the system clock.

Step 105 can be implemented in the following two ways, specifically including:

Method 1: Judging whether the two verification data read from the storage space conform to the two verification data determined when storing in the storage space during two consecutive first clock cycles during two consecutive second clock cycles , so as to determine whether the clock to be monitored is abnormal.

Method 2: Record the abnormality time of each verification data that does not conform to the data association relationship, and judge whether the time interval between two verification data occurrences is less than the preset duration threshold, so as to judge whether the clock to be monitored is abnormal.

The following is a detailed description of the above two methods for judging whether the clock to be monitored is abnormal:

For the first method, as shown in Figure 2, the method for judging whether the clock to be monitored is abnormal may include the following steps:

Step 201: Determine an association relationship between at least two check data stored in the storage space in two consecutive first clock cycles;

Step 202: Judging whether at least two verification data read in two consecutive second clock cycles conform to the association relationship, if yes, perform step 203, otherwise perform step 204.

Step 203: Determine that the clock to be monitored is normal, and continue to execute step 202;

Step 204: Determine that the clock to be monitored is abnormal.

The method for determining whether the clock to be monitored is abnormal provided by the first method is to use two verification data read in two consecutive second clock cycles as the object, when the two verification data read continuously do not meet the two The association relationship corresponding to the verification data may be due to the fact that the rate of storing the verification data in the storage space is greater than the rate of reading the verification data from the storage space, resulting in the verification data that has not been read in the storage space has been overwritten, making continuous reading The two verification data obtained do not conform to the corresponding association relationship, and the verification data in the storage space may be read empty because the rate of storing verification data in the storage space is lower than the rate of reading verification data from the storage space However, specific data is read, so that the two verification data read continuously do not conform to the corresponding association relationship, and the rate of storing verification data in the storage space is determined by the actual clock cycle of the clock to be monitored. Therefore, when When the two verification data read continuously do not match the association relationship corresponding to the two verification data, it can be determined that the clock to be monitored is abnormal.

For the second method, as shown in Figure 3, the method for judging whether the clock to be monitored is abnormal may specifically include the following steps:

Step 301: Determine an association relationship between at least two verification data stored in the storage space in two consecutive first clock cycles;

Step 302: judging whether at least two verification data read in two consecutive second clock cycles conform to the association relationship, if yes, continue to execute step 302, otherwise execute step 303;

Step 303: Determine that the verification data is abnormal, and record the time when the verification data is abnormal;

Step 304: judging whether the number of abnormalities in the verification data is equal to 2, if yes, execute step 305, otherwise execute step 302;

Step 305: Determine whether the time interval between the abnormality of the verification data recorded this time and the abnormality of the verification data recorded last time is less than the preset duration threshold, if yes, execute step 306, otherwise execute step 307;

Step 306: Determine that the clock to be monitored is abnormal, and end the current process;

Step 307: Clear the recorded abnormal times, and execute step 302.

The method provided by method 2 to determine whether the clock to be monitored is abnormal is to take every two verification data that do not conform to the corresponding relationship as the object, and when the two verification data that are read consecutively for the first time do not conform to the corresponding correlation When there is a relationship, instead of immediately determining the abnormality of the clock to be monitored, the time when the abnormality occurs in the verification data is recorded, because the rate at which the clock to be monitored stores the verification data in the storage space is different from the rate at which the verification data is read from the storage space. Minor deviation, after a long period of accumulation of minor deviation, there will inevitably be a situation where the verification data read continuously from the storage space does not conform to the corresponding relationship, which may be the inherent deviation of the clock to be monitored; continue Determine and record the time when the next two consecutively read verification data do not conform to the corresponding association relationship. After determining that the two verification data are abnormal, determine whether the time interval between the two verification data occurrences is less than the preset If the time interval between two abnormal occurrences is less than the duration threshold, it means that the actual clock period of the clock to be monitored is quite different from the standard clock period, and it is determined that the clock to be monitored is abnormal; if the time difference between the two abnormalities is greater than the duration threshold , indicating that the clock to be monitored takes a long time to accumulate before an abnormality occurs. At this time, it can be determined that the clock to be monitored is normal.

The method of determining whether the clock to be monitored is abnormal in method 1 is applicable to the situation that the clock to be monitored is required to be very accurate, while the method of determining whether the clock to be monitored is abnormal provided in method 2 is applicable to the situation that the accuracy of the clock to be monitored is required to be general. Therefore, method 1 and method 2 are applicable to different application scenarios, and can be flexibly selected according to actual requirements in the actual service implementation process, thereby improving the applicability of the verification method.

In an embodiment of the present invention, according to the method for determining the abnormality of the clock to be monitored described in the second method, after recording the abnormality of the verification data once, it further includes:

suspending execution of the at least one verification data stored earlier from the storage space at each second clock cycle, and restarting execution of the verification data after the pause duration reaches a preset buffer duration Read at least one of the verification data stored earlier from the storage space in each second clock cycle;

Wherein, the buffer duration is greater than or equal to one cycle of the second clock.

In an embodiment of the present invention, after determining and recording an abnormality in the verification data once, instead of directly sending out an alarm message, or continuing to determine and record the time at which the next verification data is abnormal, the timeout is not less than the second clock. The buffering time of the cycle reads the verification data from the storage space. The purpose of this method is to avoid the slight deviation between the rate of storing the verification data in the storage space and the rate of reading the verification data from the storage space. It is determined that the clock to be monitored is abnormal because the two verification data read continuously from the storage space do not conform to the corresponding association relationship.

In an embodiment of the present invention, the frequency modulation processing is performed on the clock cycle of the clock to be monitored according to the preset target clock cycle to obtain the first clock cycle, including:

Determine the first frequency modulation parameter according to the ratio of the preset target clock period to the standard clock period of the clock to be monitored, and use the first frequency modulation parameter to scale the actual clock period of the clock to be monitored to obtain the first clock period ;

According to the target clock cycle, performing frequency modulation processing on the clock cycle of the reference clock to obtain the second clock cycle includes:

A second frequency modulation parameter is determined according to a preset ratio of the target period to the clock period of the reference clock, and the second frequency modulation parameter is used to scale the clock period of the reference clock to obtain the second clock period.

In the embodiment of the present invention, the determined first frequency modulation parameter is equal to the ratio of the preset target clock cycle to the standard clock cycle of the clock to be monitored, and the determined second frequency modulation parameter is equal to the ratio of the preset target clock cycle to the reference clock For the ratio of the clock period, use the first frequency modulation parameter to scale the actual clock period of the clock to be monitored to obtain the first clock period, and then use the second frequency modulation parameter to scale the clock period of the reference clock to obtain the second clock period The purpose of determining the first frequency modulation parameter and the second frequency modulation parameter is to compare the first clock period obtained by scaling the actual clock period of the clock to be monitored with the second clock period obtained by scaling the clock period of the reference clock.

In an embodiment of the present invention, before storing the at least one verification data in the storage space according to the order of creation, it further includes:

At least one piece of buffered data conforming to the data creation rule is sequentially stored in the storage space.

In the embodiment of the present invention, before the clock to be monitored stores at least one verification data in the storage space, at least one buffer data conforming to the data creation rule is stored in the storage space, and the operation of storing the buffer data can prevent the system from starting to work. At this time, the operation of reading the verification data from the storage space has been executed before the operation of storing the verification data to the storage space, and the result is that the verification data cannot be read from the storage space, and it is determined that the clock to be monitored is abnormal .

The method for monitoring a system clock provided by the embodiment of the present invention will be described in further detail below in combination with the aforementioned method 2. As shown in FIG. 4 , the method may include the following steps:

Step 401: Create a storage space with a preset capacity.

Specifically, a storage space with a preset capacity is created in advance, so as to store the generated check data after the clock to be monitored generates at least one check data.

For example, create a storage space with a capacity of 1MB in the server.

Step 402: sequentially store at least one piece of buffered data conforming to the data creation rule in the storage space.

Specifically, before the server starts to work and stores the verification data into the storage space, at least one buffer data conforming to the data creation rules is stored in the storage space, preventing the server from starting to work, and the verification data has not been stored in the storage space. The data operation has already performed the operation of reading the verification data from the storage space, resulting in an abnormal situation where the verification data cannot be read.

For example, buffer data A, B, and C each with a size of 0.2MB and meeting the data creation rules are stored in the storage space.

Step 403: Determine the first frequency modulation parameter and the second frequency modulation parameter.

Specifically, the first frequency modulation parameter and the second frequency modulation parameter are determined according to the standard clock period of the clock to be monitored and the clock period of the reference clock, wherein the standard clock period of the clock to be monitored is a theoretical clock period of the clock to be monitored.

For example, the clock source of the server (that is, the clock to be monitored) has a clock period of 0.02s, and the clock frequency of the reference clock is 0.05s. In order to adjust the clock periods of the clock to be monitored and the reference clock to the target clock period of 0.1s , it can be determined that the first frequency modulation parameter of the clock to be monitored is 5, and the second frequency modulation parameter of the reference clock is 2.

Step 404: Use the first frequency modulation parameter to perform frequency modulation on the actual clock period of the clock to be monitored, and obtain the first clock period of the clock to be monitored.

Specifically, in order to tune both the standard clock period of the clock to be monitored (that is, the theoretical clock period) and the clock period of the reference clock to the target clock period, it is necessary to use the first frequency tuning parameter to tune the standard clock period of the clock to be monitored to the first clock cycle.

For example, using the first frequency tuning parameter 5, the clock source of the server with a clock period of 0.02s is tuned to a clock period of 0.1s.

Step 405: Frequency modulation is performed on the clock period of the reference clock by using the second frequency modulation parameter to obtain the second clock period of the reference clock.

Specifically, in order to tune both the clock period of the reference clock and the standard clock period (that is, the theoretical clock period) of the clock to be monitored to the target clock period, it is necessary to use the second frequency modulation parameter to tune the clock period of the reference clock to the second clock period .

For example, by using the second frequency modulation parameter 2, the frequency of the reference clock with a clock period of 0.05s is modulated to 0.1s.

Step 406: According to the preset data creation rule, at least one check data is sequentially created in each first clock cycle, and the at least one check data is stored in the storage space according to the order of creation.

Specifically, at least one verification data conforming to the data creation rule is created in each first clock cycle, and the created verification data is stored in the storage space in sequence, so that it is convenient to read from the storage space when the verification data is needed, but Due to the limited capacity of the storage space, when the capacity of the storage space is insufficient, the verification data created later will overwrite the verification data stored for a longer period of time, thereby ensuring that the verification data created later can be stored in the storage space.

For example, the default data creation rule is to store the first verification data a+1 in the 0.1s clock cycle of the first clock to be monitored, and store it in the 0.1s clock cycle of the second clock to be monitored Enter the second verification data a+2, store the third verification data a+3 in the 0.1s clock cycle of the third clock to be monitored, and store the third verification data a+3 in the 0.1s clock cycle of the fourth clock to be monitored Enter the fourth verification data a+1, and cyclically store the three verification data a+1, a+2, a+3 in the storage space (verification data a+1, a+2, a+3 That is, the verification data conforming to the data creation rules), and the size of each verification data is 0.2MB. For example, at the 0.1s clock cycle of the first clock to be monitored, the verification data a+1 will be generated, and a+1 will be stored in the storage space, and at the 0.1s clock cycle of the second clock to be monitored , the verification data a+2 will be generated, and a+2 will be stored in the storage space. Since the capacity of the storage space is 1MB, and there is already 0.5MB of cached data in the storage space, the capacity of the remaining storage space is 0.5MB and only two verification data of a+1 and a+2 can be stored. Under the 0.1s clock cycle of the clock to be monitored, after the verification data a+3 is generated, if you want to store the verification data a+3 in the storage space, you need to overwrite the verification data a+1 that has been stored for a long time in the storage space .

Step 407: At each second clock cycle, read at least one verification data that has been stored for a long time from the storage space, and delete the read verification data in the storage space.

Specifically, since the capacity of the storage space is limited, at each second clock cycle, after the verification data stored for a long time is read from the storage space, the data is deleted, so as to release the capacity of the storage space in time. When there is no verification data in the storage space, specific data is read as verification data, for example, the specific data is b.

For example, at the 0.1s clock cycle of the first reference clock, read the verification data a+1 with a longer storage time in the storage space according to the order in which the verification data is stored in the storage space, and read the verification data a+1 in the storage space. After verifying the data a+1, delete the verification data a+1 from the storage space. At the 0.1s clock cycle of the second reference clock, read the verification data a+2 with a long storage time in the storage space, and after reading the verification data a+2, transfer the verification data a+2 from Deleted from storage.

Step 408: Judging whether at least two verification data read in two consecutive second clock cycles comply with the data creation rule, if yes, perform step 409, otherwise perform step 410.

Specifically, according to the verification data read from the storage space, it is sequentially judged whether the two verification data read continuously conform to the verification data rules, so as to determine whether the monitoring is always abnormal.

For example, if the check data a+1 and a+2 read from the storage space are to be monitored during the first 0.1s clock cycle and the second 0.1s clock cycle of the reference clock The verification data a+1 and a+2 stored in the clock during the first 0.1s and second 0.1s clock cycles can determine that the clock to be monitored is normal.

If the check data a+2 and a+3 read from the storage space during the first 0.1s and second 0.1s clock cycles of the reference clock are not in the first 0.1s of the clock to be monitored The verification data a+1 and a+2 stored in the clock cycle of the clock cycle can determine that the clock to be monitored is abnormal.

Step 409: Determine that the current verification data conforms to the data creation rule, and proceed to step 408.

Specifically, according to the comparison between the data creation rule and the currently read verification data, after confirming that the data creation rule is met, continue to confirm whether the next verification data read from the storage space conforms to the data creation rule.

For example, during the first 0.1s clock cycle of the reference clock, the verification data a+1 and a+2 read from the storage space are the first 0.1s clock cycle of the clock to be monitored The verification data a+1 and a+2 stored at the time are determined to meet the data creation rules, and the next verification data read from the storage space is continued to be verified.

Step 410: Determine that the verification data is abnormal, and record the time when the verification data is abnormal.

Specifically, after it is determined that the verification data read from the storage space does not comply with the data creation rules, it is determined that the verification data is abnormal, and the time when the verification data is abnormal is recorded once, and when the verification data is abnormal once recorded, After that, instead of directly sending out an alarm message, or continuing to determine and record the time when the next verification data is abnormal, it is to suspend the buffer time not less than the second clock cycle to read the verification data from the storage space. The purpose of this approach It is to avoid the slight deviation between the rate of storing the verification data in the storage space and the rate of reading the verification data from the storage space, resulting in that the two verification data continuously read from the storage space do not conform to the corresponding To determine the abnormality of the clock to be monitored, after the pause time is reached, continue to determine the next verification data that does not meet the data creation rules, and record the time when the verification data is abnormal.

For example, due to an abnormality in the actual clock period of the clock to be monitored, the original 0.02s becomes 0.04s, and after frequency modulation by the first frequency modulation parameter 5, the clock period of the clock to be monitored becomes 0.2s.

The clock to be monitored has stored two verification data a+1 and a+2 in the storage space in the first 0.2s clock cycle, and reads from the storage space in the first 0.1s clock cycle of the reference clock Take the verification data a+1, delete the verification data a+1 after reading a+1, and then the remaining verification data a+2 in the storage space;

The clock to be monitored stores a+3 and a+1 in the second 0.2s clock cycle, and a+2 should be read in the second 0.1s of the reference clock, but because the stored a +3 and a+1 have overwritten a+2, so a+3 is read. According to a+1 and a+3 read twice in a row, it is determined that a+1 and a+1 are not stored in order. a+2, so it can be determined that the verification data is abnormal. It is recorded that the verification data is abnormal in the second 0.1s clock cycle of the reference clock. At this time, the remaining verification data in the storage space is a+1, and it is suspended A 0.1s buffering time reads the verification data from the storage space;

Within 0.1s of the pause, the clock to be monitored stores two verification data a+2 and a+3, and overwrites the previously stored a+1. In the third 0.1s of the reference clock, it should start from the storage A+3 is read in the space, but the actual read is a+2. According to the last read a+3 and the current read a+2, it is determined that the verification data is abnormal, and the verification data is recorded. The second anomaly occurs in the data at the third 0.1s of the reference clock.

Step 411: Determine whether the number of abnormalities in the verification data is equal to 2, if yes, execute step 412, otherwise execute step 408.

Specifically, it cannot be determined that the clock to be monitored is abnormal when the first verification data is abnormal, because the clock to be monitored may be abnormal after long-term accumulation due to a small clock cycle deviation, but it needs to be determined twice It is judged by the time difference of the abnormality of the verification data, so it is necessary to determine whether the number of abnormalities in the verification data is equal to 2.

For example, if the number of abnormal occurrences of the recorded verification data is equal to 2, the time difference between the two abnormalities is further determined.

If the number of abnormal occurrences of the recorded verification data is less than 2, continue to judge whether the number of abnormal occurrences of the next verification data is equal to 2.

Step 412: Determine whether the time interval between the second occurrence of abnormality in the verification data and the first occurrence of abnormality is less than a preset duration threshold, if yes, execute step 414, otherwise execute step 413.

Specifically, it is determined whether the time difference between the two times when the verification data is abnormal meets the preset duration threshold, so as to determine whether the clock to be monitored is abnormal.

For example, the preset duration threshold is 0.5s. Since the time difference between the first occurrence of data anomaly and the second occurrence of data anomaly is 0.1s, which is less than the duration threshold of 0.5s, it can be determined that the clock to be monitored is abnormal.

If the time difference between the first occurrence of data anomaly and the second occurrence of data anomaly is 0.6s and not less than the duration threshold of 0.5s, it can be determined that the clock to be monitored is normal.

Step 413: Determine that the clock to be monitored is normal, and proceed to step 408.

Specifically, if the time difference between the abnormality of the two verification data is not less than the set duration threshold, it can be determined that the clock to be monitored is normal.

For example, if the time difference between the first occurrence of data anomaly and the second occurrence of data anomaly is 0.1s, which is not less than the duration threshold, it can be determined that the clock to be monitored is normal.

Step 414: Determine that the clock to be monitored is abnormal, and send an alarm message.

Specifically, according to the fact that the time difference between the two verification data occurrences is less than the set duration threshold, it can be determined that the clock to be monitored is abnormal, and an alarm message is sent to the server.

For example, if the time difference between the first data anomaly and the second data anomaly is 0.1s, which is less than the 0.5s set by the duration threshold, it can be determined that the clock to be monitored is abnormal, and a notification that the clock to be monitored is too fast is sent to the server. Alarm information.

As shown in Figure 5, an embodiment of the present invention provides a system clock monitoring device, including:

A frequency modulation processing unit 501, a storage unit 502, a reading unit 503 and a judging unit 504;

The frequency modulation processing unit 501 is configured to perform frequency modulation processing on the clock cycle of the clock to be monitored according to the preset target clock cycle to obtain the first clock cycle, and is also used to adjust the clock cycle of the reference clock according to the target clock cycle Perform frequency modulation processing to obtain a second clock cycle;

The storage unit 502 is configured to store at least one check data in a storage space with a preset capacity at each first clock cycle acquired by the frequency modulation processing unit 501, wherein, in the storage space Overwrite the data stored for a long time when the capacity is insufficient;

The reading unit 503 is configured to read from the storage space at least one of the calibration values stored earlier by the storage unit 502 at each second clock cycle acquired by the frequency modulation processing unit 501. verification data, and delete the read at least one verification data from the storage space, wherein, when the verification data does not exist in the storage space, read specific data as the check data;

The judging unit 504 is configured to judge whether the clock to be monitored is abnormal according to at least two verification data read by the reading unit 503 in two consecutive cycles of the second clock.

Based on a system clock monitoring device shown in FIG. 5, in an embodiment of the present invention, as shown in FIG. 6, the judging unit 504 includes: a first determining subunit 5041 and a first judging subunit 5042;

The first determination subunit 5041 is configured to determine an association relationship between at least two check data stored in the storage space in two consecutive first clock cycles;

The first judging subunit 5042 is configured to judge whether at least two verification data read in two consecutive second clock cycles conform to the association relationship determined by the first determining subunit 5041 , if yes, determine that the clock to be monitored is normal, otherwise determine that the clock to be monitored is abnormal.

Based on the system clock monitoring device shown in FIG. 5, in an embodiment of the present invention, as shown in FIG. 7, the judging unit 504 includes: a second determining subunit 5043 and a second judging subunit 5044;

The second determining subunit 5043 is configured to determine an association relationship between at least two verification data stored in the storage space in two consecutive first clock cycles;

The second judging subunit 5044 is configured to judge whether at least two verification data read in two consecutive second clock cycles conform to the association relationship determined by the second determining subunit 5043 , if not, record the abnormality of the verification data once, which is also used to judge whether the time interval between the abnormality of the verification data recorded this time and the abnormality of the verification data recorded last time is less than the preset duration threshold , if yes, determine that the clock to be monitored is abnormal, otherwise determine that the clock to be monitored is normal.

In one embodiment of the present invention,

The frequency modulation processing unit is configured to determine a first frequency modulation parameter according to the ratio of a preset target clock period to a standard clock period of the clock to be monitored, and use the first frequency modulation parameter to determine the actual clock period of the clock to be monitored Perform scaling to obtain the first clock period, and also determine a second frequency modulation parameter according to the ratio of the preset target period to the clock period of the reference clock, and use the second frequency modulation parameter to adjust the clock period of the reference clock Scale to get the second clock cycle;

In an embodiment of the present invention, the second judging subunit is configured to trigger the reading unit after recording the abnormality of the verification data for the first time;

The reading unit is further configured to, when receiving the trigger of the recording subunit, suspend the execution of the reading of at least one of the earlier stored from the storage space in each second clock cycle. verifying the data, and after the pause time reaches the preset buffering time, restarting the execution of reading at least one of the verification data stored earlier from the storage space in each second clock cycle , wherein the buffer duration is greater than or equal to one cycle of the second clock.

In an embodiment of the present invention, the storage unit is further configured to sequentially store at least one buffer data conforming to the association relationship in the storage space.

In the embodiment of the present invention, in order to have comparable clock periods of the clock to be monitored and the reference clock, the frequency modulation processing unit frequency-tunes the clock period to be monitored to the first clock period according to the preset target clock period, and the reference The clock cycle of the clock is frequency-modulated to the second clock cycle, and the storage unit stores at least one verification data in the storage space during the first clock cycle obtained by each frequency-modulation processing unit, so that the reading unit obtains at each frequency-modulation processing unit The second clock cycle reads at least one check data stored earlier from the storage space. Due to the limited capacity of the storage space, when the first clock cycle is different from the second clock cycle, the check data in the storage space will be Overflow or check data does not exist, so that the check data read from the storage space has a corresponding change. Therefore, the judging unit can determine whether the first clock cycle and the second clock cycle are the same by reading the verification data read by the unit from the storage space, so as to determine whether the clock to be monitored is abnormal, and realize monitoring the system clock .

Various embodiments of the present invention have at least the following beneficial effects:

1. In the embodiment of the present invention, in order to make the clock periods of the clock to be monitored and the reference clock comparable, according to the preset target clock period, the frequency of the clock period to be monitored is adjusted to the first clock period, and the reference clock The clock cycle frequency is adjusted to the second clock cycle, and at least one check data is stored in the storage space at each first clock cycle, in order to read at least one of the earlier stored data from the storage space at each second clock cycle A check data, due to the limited capacity of the storage space, when the first clock cycle is different from the second clock cycle, it will cause the check data in the storage space to overflow or the check data does not exist, so that the read from the storage space The verification data of the corresponding changes. Therefore, it can be determined whether the first clock period and the second clock period are the same through the verification data read from the storage space, so as to determine whether the clock to be monitored is abnormal, and monitor the system clock.

2. In the embodiment of the present invention, the method for determining whether the clock to be monitored is abnormal provided by the first method is to use two verification data read in two consecutive second clock cycles as the object, and when the two consecutively read A verification data does not conform to the corresponding relationship between the two verification data. It may be that the rate of storing verification data in the storage space is greater than the rate of reading verification data from the storage space, resulting in unread verification data in the storage space. The data has been overwritten, so that the two verification data read continuously do not conform to the corresponding association relationship. It may also be because the rate of storing verification data in the storage space is lower than the rate of reading verification data from the storage space, causing the storage space to fail. The verification data in is read empty and specific data is read, so that the two consecutively read verification data do not conform to the corresponding association relationship, and the rate of storing verification data in the storage space is determined by the clock to be monitored The actual clock cycle is determined. Therefore, when the two verification data read continuously do not match the correlation relationship corresponding to the two verification data, it can be determined that the clock to be monitored is abnormal.

3. In the embodiment of the present invention, the method for determining whether the clock to be monitored is abnormal provided by the second method is based on the fact that the verification data does not conform to the corresponding relationship every two times. When a verification data does not conform to the corresponding relationship, it is not immediately determined that the clock to be monitored is abnormal but the time when the verification data is abnormal is recorded. There is a slight deviation in the rate of reading verification data in the system. When the slight deviation is accumulated for a long time, there will inevitably be a situation where the verification data continuously read from the storage space does not conform to the corresponding relationship. This may It is the inherent deviation of the clock to be monitored; continue to determine and record the time when the next two consecutively read verification data do not conform to the corresponding relationship, and after determining that the two verification data are abnormal, determine the two verification data Whether the time interval between abnormal occurrences is less than the preset duration threshold. If the time interval between two abnormal occurrences is less than the duration threshold, it means that the actual clock period of the clock to be monitored is quite different from the standard clock period, and it is determined that the clock to be monitored is abnormal; if If the time difference between the two abnormalities is greater than the duration threshold, it means that the clock to be monitored needs a long time to accumulate before an abnormality occurs. At this time, it can be determined that the clock to be monitored is normal.

4. In the embodiment of the present invention, in one embodiment of the present invention, after determining and recording an abnormality in the verification data, it is not to send an alarm message directly, nor to continue to determine and record the time when the next verification data is abnormal , but to suspend the buffering duration of not less than the second clock cycle to read the verification data from the storage space. The purpose of this approach is to avoid the There is a slight deviation in the rate, which results in the fact that the two verification data read continuously from the storage space do not conform to the corresponding correlation, and it is determined that the clock to be monitored is abnormal.

5. In the embodiment of the present invention, the determined first frequency modulation parameter is equal to the ratio of the preset target clock period to the standard clock period of the clock to be monitored, and the determined second frequency modulation parameter is equal to the preset target clock period and the reference The ratio of the clock period of the clock, using the first frequency modulation parameter to scale the actual clock period of the clock to be monitored, can obtain the first clock period, and then use the second frequency modulation parameter to scale the clock period of the reference clock, and then obtain the second Clock period, determining the first frequency modulation parameter and the second frequency modulation parameter, is to scale the first clock period obtained by scaling the actual clock period of the clock to be monitored and the second clock period obtained by scaling the clock period of the reference clock for comparability .

6. In the embodiment of the present invention, in the embodiment of the present invention, before the clock to be monitored stores at least one verification data in the storage space, store at least one buffer data conforming to the data creation rules in the storage space, and store the buffer data The operation can prevent the system from executing the operation of reading the verification data from the storage space before performing the operation of storing the verification data in the storage space when the system starts to work, resulting in failure to read the verification data from the storage space The data identifies the abnormality of the clock to be monitored.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or sequence. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a "..." does not exclude the presence of additional same elements in the process, method, article or apparatus comprising said element.

Those of ordinary skill in the art can understand that all or part of the steps to realize the above method embodiments can be completed by program instructions related hardware, and the aforementioned programs can be stored in a computer-readable storage medium. When the program is executed, the It includes the steps of the above method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

Finally, it should be noted that the above descriptions are only preferred embodiments of the present invention, and are only used to illustrate the technical solution of the present invention, and are not used to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present invention are included in the protection scope of the present invention.

Claims (10)

1. a kind of system clock monitoring method, it is characterised in that including：

According to the target clock cycle set in advance, the clock cycle for treating monitoring clock carries out frequency modulation processing, when obtaining first The clock cycle；

According to the target clock cycle, frequency modulation processing is carried out to the clock cycle of reference clock, the second clock cycle is obtained；

In each described first clock cycle, at least one verification data is stored into the memory space with preset capacity, Wherein, the data longer to storage time in the off-capacity of the memory space are covered；

In each described second clock cycle, read from the memory space compared with least one the described check number first stored According to, and at least one described verification data described in reading deletes from the memory space, wherein, when the storage is empty Between when in the absence of the verification data, read specific data and be used as the verification data；

The verification data according at least two read the continuous two second clock cycles, judges described to be monitored Whether clock is abnormal.

2. according to the method described in claim 1, it is characterised in that

The basis read the continuous two second clock cycles at least two described in verification data judge described in treat Whether monitoring clock is abnormal, including：

It is determined that in continuous two the first clock cycle storages to verification data described at least two in the memory space Between incidence relation；

Whether verification data described in judging read the continuous two second clock cycles at least two meets the pass Connection relation；

If it is, determining that the clock to be monitored is normal, otherwise determine that the clock to be monitored is abnormal；

And/or

The basis read the continuous two second clock cycles at least two described in verification data judge described in treat Whether monitoring clock is abnormal, including：

It is determined that in continuous two the first clock cycle storages to verification data described at least two in the memory space Between incidence relation；

Whether verification data described in judging read the continuous two second clock cycles at least two meets the pass Connection relation, if not, verification data exception of record；

Judge between the abnormal verification data exception recorded the last time of described verification data that this is recorded when Between be spaced whether be less than default duration threshold value, if it is, determining that the clock to be monitored is abnormal, otherwise determine described to be monitored Clock is normal.

3. method according to claim 2, it is characterised in that

After the record once the verification data exception, further comprise：

Pause reads at least one more first stored in each described second clock cycle described in performing from the memory space The individual verification data, and after pause duration reaches buffering duration set in advance, restart execution described at each The second clock cycle is read from the memory space compared with least one the described verification data first stored；

Wherein, the buffering duration is more than or equal to a second clock cycle.

4. according to the method described in claim 1, it is characterised in that

Described the clock cycle for treating monitoring clock carries out frequency modulation processing according to the target clock cycle set in advance, obtains the One clock cycle, including：

According to target clock cycle set in advance and the ratio of the standard clock cycle of clock to be monitored, determine that the first frequency modulation is joined Number, is zoomed in and out using first chirp parameter to the actual clock cycle of the clock to be monitored, obtains the first clock week Phase；

It is described that frequency modulation processing is carried out to the clock cycle of reference clock according to the target clock cycle, obtain second clock week Phase, including：

According to target period set in advance and the ratio of the clock cycle of reference clock, the second chirp parameter is determined, institute is utilized State the second chirp parameter to zoom in and out the clock cycle of the reference clock, obtain the second clock cycle.

5. according to any described method in claim 2 to 3, it is characterised in that

Described in each described first clock cycle, at least one verification is stored into the memory space with preset capacity Before data, further comprise：

At least one buffered data for meeting the incidence relation is stored in the memory space successively.

6. a kind of system clock supervising device, it is characterised in that including：Frequency modulation processing unit, memory cell, reading unit and sentence Disconnected unit；

The frequency modulation processing unit, for according to the target clock cycle set in advance, the clock cycle for treating monitoring clock to enter The processing of row frequency modulation, obtained for the first clock cycle, is additionally operable to, according to the target clock cycle, enter the clock cycle of reference clock The processing of row frequency modulation, obtains the second clock cycle；

The memory cell, for each described first clock cycle obtained in the frequency modulation processing unit, to pre- If storing at least one verification data in the memory space of capacity, wherein, in the off-capacity of the memory space to storage Time longer data are covered；

The reading unit, for each the described second clock cycle obtained in the frequency modulation processing unit, is deposited from described Read in storage space the memory cell compared with least one the described verification data first stored, and described in reading at least One verification data is deleted from the memory space, wherein, when the memory space is in the absence of the verification data When, read specific data and be used as the verification data；

The judging unit, for read according to the reading unit the continuous two second clock cycles at least two The individual verification data, judges whether the clock to be monitored is abnormal.

7. device according to claim 6, it is characterised in that

The judging unit includes：First determination subelement and the first judgment sub-unit；

First determination subelement, for determining in continuous two the first clock cycle storages into the memory space At least two described in incidence relation between verification data；

First judgment sub-unit, for judge to read the continuous two second clock cycles at least two described in Whether verification data meets the incidence relation that first determination subelement is determined, if it is, when determining described to be monitored Clock is normal, otherwise determines that the clock to be monitored is abnormal；

And/or

The judging unit includes：Second determination subelement and the second judgment sub-unit；

Second determination subelement, it is determined that being stored in continuous two first clock cycle into the memory space extremely Incidence relation between few two verification datas；

Second judgment sub-unit, for judge to read the continuous two second clock cycles at least two described in Whether verification data meets the incidence relation that second determination subelement is determined, if not, verification data of record It is abnormal, it is additionally operable to judge the verification data exception and the last verification data exception recorded that this is recorded Between time interval whether be less than default duration threshold value, if it is, determining that the clock to be monitored is abnormal, otherwise determine described Clock to be monitored is normal.

8. device according to claim 7, it is characterised in that

Second judgment sub-unit, is further used for after record once the verification data generation exception, reads described Unit is taken to be triggered；

The reading unit, is further used for when receiving the triggering of second judgment sub-unit, pause perform it is described Each described second clock cycle is read from the memory space compared with least one the described verification data first stored, and Pause duration reached after buffering duration set in advance, restart to perform it is described in each described second clock cycle from institute At least one the described verification data read in memory space compared with first storing is stated, wherein, the buffering duration is more than or equal to one The individual second clock cycle.

9. device according to claim 6, it is characterised in that

The frequency modulation processing unit, for the standard clock cycle according to target clock cycle set in advance and clock to be monitored Ratio, determine the first chirp parameter, the actual clock cycle of the clock to be monitored entered using first chirp parameter Row scaling, obtained for the first clock cycle, is additionally operable to the ratio of the clock cycle according to target period set in advance and reference clock Value, is determined the second chirp parameter, the clock cycle of the reference clock is zoomed in and out using second chirp parameter, is obtained The second clock cycle.

10. according to any described device in claim 7 to 8, it is characterised in that

The memory cell, is further used for storing at least one in the memory space successively and meets the incidence relation Buffered data.