The patent is a divisional application, and the name of a parent patent is a drive circuit of a display panel, a drive module of the display panel, display equipment and a manufacturing method of the display panel, wherein the application number is 2013106627712, and the application date is 2013, 12 months and 06 days.
Drawings
FIG. 1 is a block diagram of a display device according to a preferred embodiment of the present invention;
FIG. 2 is a block diagram of a data driving circuit according to a preferred embodiment of the present invention;
FIG. 3 is an RC equivalent circuit of the source line pixel structure of the display panel according to the present invention;
FIG. 4 is a block diagram of a driving circuit of a display panel according to a first embodiment of the present invention;
FIG. 5 is a block diagram of a driving circuit of a display panel according to a second embodiment of the present invention;
FIG. 6 is a block diagram of a driving circuit of a display panel according to a third embodiment of the present invention;
FIG. 7 is a circuit diagram of a driving unit according to a first embodiment of the present invention;
FIG. 8 is a circuit diagram of a driving unit according to a second embodiment of the present invention;
FIG. 9 is a block diagram of a driving circuit of a display panel according to a fourth embodiment of the present invention;
FIG. 10 is a circuit diagram of a boosting unit according to a first embodiment of the present invention;
FIG. 11 is a block diagram of a driving circuit of a display panel according to a fifth embodiment of the present invention;
FIG. 12 is a circuit diagram of a boosting unit according to a second embodiment of the present invention;
FIG. 13 is a circuit diagram of a boosting unit according to a third embodiment of the present invention;
FIG. 14A is a schematic structural diagram of a display module;
FIG. 14B is a schematic structural diagram of a display module according to the present invention; and
fig. 15 is a flowchart of a method of manufacturing a display panel.
[ brief description of the drawings ]
1 display device
2 scan driving circuit
3 data driving circuit
32 gamma circuit
34 drive circuit
340 drive unit
3400, 3404 differential cell
34000, 34002, 34004, 34006 transistors
34020, 34040, 34041, 34043 transistors
34044, 34048, 34049, 34050 transistors
34051, 34052, 34052, 34053 transistors
34060, 34062, 3461, 3462, 3463 transistors
3464 transistor
34008, 34022, 34042, 34045 current sources
3402, 3406 output unit
342 digital-to-analog conversion circuit
344 boost circuit
346. 348 boost unit
3460 flying capacitor
Cs1、Cs2Storage capacitor
3470 control transistor
3472 diode
3474 storage inductor
3476 output capacitance
349 line buffer
4 sequential control circuit
5 display panel
50 pixel structure
500 resistance
502 capacitor
6 drive module
60 flexible circuit board
62 drive chip
V1~VrGamma voltage
VT1、VT2First timeA timing signal, a second timing signal
VS1~VSnScanning drive signal
Vs1~VsnData driving voltage
VP1,VP2A first supply voltage, a second supply voltage
VP3Third supply voltage
Vref1~VrefnReference driving voltage
Detailed Description
Certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "coupled" is intended to encompass any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
In order to provide a further understanding and appreciation for the structural features and advantages achieved by the present invention, the following detailed description of the presently preferred embodiments is provided:
fig. 1 is a block diagram of a display device according to a preferred embodiment of the invention. As shown in the figure, the display device 1 of the present invention includes a scan driving circuit 2, a data driving circuit 3, a timing control circuit 4 and a display panel 5. The scan driving circuit 2 is used for generating a plurality of scan driving voltages Vg1~VgmAnd sequentially transmitting the scan driving voltages Vg1~VgmTo the display panel 5, the data driving circuit 3 is used for generating a plurality of data driving voltages Vs1~VsnAnd corresponding to the scan driving voltages Vg1~VgmTransmitting the data driving voltages Vs1~VsnTo the display panel 5 to drive the display panel 5 to display images.
The timing control circuit 4 is used to generate a first timing signal VT1And a second timing signal VT2The timing control circuit 4 transmits the first timing signals V respectivelyT1And a second timing signal VT2To the scan driving circuit 2 and the data driving circuit 3 to control the scan driving voltage V transmitted from the scan driving circuit 2 to the display panel 5g1~VgmThe data driving voltage V transmitted to the display panel 5 synchronously with the data driving circuit 3s1~VsnThat is, when the scan driving circuit 2 transmits the scan driving voltage Vg1When the display panel 5 is reached, the data driving circuit 3 corresponds to the scanning driving voltage Vg1Transmitting the data driving voltages Vs1~VsnDriving the display panel 5 to display the image of the first row; when the scan driving circuit 2 transmits the scan driving voltage Vg2When the display panel 5 is reached, the data driving circuit 3 corresponds to the scanning driving signal Vg2Transmitting the data driving voltages Vs1~VsnAnd driving the display panel 5 to display the second row of images on the display panel 5, and so on, and driving the display panel 5 to display a whole display frame.
Fig. 2 is a block diagram of a data driving circuit according to a preferred embodiment of the invention. As shown, the data driving circuit 3 includes a Gamma (Gamma) circuit 32 and a driving circuit 34. The gamma circuit 32 generates a plurality of gamma voltages according to a gamma curve, the gamma circuit 32 transmits the gamma voltages to the driving circuit 34, the gamma voltages are voltage signals with different levels, the driving circuit 34 receives the gamma voltages and a plurality of pixel data, the driving circuit 34 selects one of the gamma voltages according to the pixel data, and generates the data driving voltages V corresponding to the pixel datas1~VsnAnd transmitting the data driving voltages Vs1~VsnTo the display panel 5 to drive the display panel 5 to display images.
Referring to fig. 3, an RC equivalent circuit of the source line pixel structure of the display panel of the invention is shown. As shown in the drawings, a preferred embodiment of the present invention is applied to a display panel 5 which is a thin film transistor liquid crystal display (TFT-LCD). The display panel 5 includes a plurality of pixel structures 50, the pixel structures 50 are coupled to the driving circuit 34, the pixel structure 50 of each source line in the display panel 5 is a Thin-film Transistor (TFT), and the pixel structure 50 can be equivalent to a resistor 500 connected in series to a capacitor 502.
Fig. 4 is a block diagram of a driving circuit of a display panel according to a first embodiment of the invention. As shown, the driving circuit 34 of the display panel of the present invention includes a plurality of driving units 340, a plurality of digital-to-analog conversion circuits 342, a boosting circuit 344 and at least one boosting unit 346. The driving units 340 are coupled to the gamma circuit 32, and the driving units 340 respectively depend on the gamma voltages V of the gamma circuit 321~VrA reference driving voltage is generated, that is, a plurality of output lines of the gamma circuit 32 are respectively coupled to the driving units 340, and the gamma circuit 32 respectively transmits the gamma voltages V through the output lines1~VrTo the driving units 340, the driving units 340 are driven to generate a plurality of reference driving voltages V respectivelyref1~VrefrAnd transmitting the reference driving voltages Vref1~VrefrTo the digital-to-analog conversion circuits 342.
The digital-to-analog conversion circuits 342 are coupled to the driving units 340 and receive the reference driving voltages V transmitted by the driving units 340ref1~VrefrSelecting the reference driving voltages V according to the pixel dataref1~VrefrOne of them is a data driving voltage VsThe digital-to-analog conversion circuits 342 transmit the data driving voltages Vs1~VsnTo the display panel 5 to display a picture, that is, each numeralThe analog conversion circuits 342 receive the reference driving voltages Vref1~VrefrAnd selecting the reference driving voltages V according to the pixel dataref1~VrefrOne of them is a data driving voltage VsTherefore, the digital-to-analog conversion circuits 342 generate the data driving voltages Vs1~VsnAnd transmitting the data driving voltages Vs1~VsnTo the display panel 5 to display a picture. The pixel data may be provided from a buffer 349 or, referring to fig. 2, from an input of a driver circuit 34.
The boost circuit 344 is coupled to the gamma circuit 32 and the digital-to-analog converters 342, and the boost circuit 344 is used for generating a first supply voltage VP1And providing a first supply voltage VP1To the gamma circuit 32 and the digital-to-analog conversion circuits 342. At least one boosting unit 346 coupled to the driving units 340 for generating a second supply voltage VP2And providing a second supply voltage VP2To the driving units 340. In the present embodiment, only one boosting unit 346 is used to generate the second supply voltage VP2And providing a second supply voltage VP2The boosting unit 346 coupled to the driving units 340 is coupled to the flying capacitor Cf1And Cf2And a storage capacitor Cs1The boost circuit 344 is coupled to the flying capacitor Cf3And Cf4And a storage capacitor Cs2. According to the above, the driving units 340 and the digital-to-analog conversion circuits 342 may have respective power supplies, and the gamma circuit 32 and the driving units 340 may have respective power supplies. Thus, the voltage boosting units 346 and the voltage boosting circuit 344 respectively provide voltages to the corresponding components to reduce the external storage capacitor Cs1And Cs2Area of, even without external storage capacitor Cs1And Cs2Thereby achieving the purpose of saving circuit area.
Furthermore, since the number of source lines of the display panel 5 is greater than the number of output lines of the gamma circuit 32, the driving units 340 are disposed between the gamma circuit 32 and the digital-to-analog conversion circuits 342, that is, the driving units 340 are disposed on the output lines of the gamma circuit 32, so that the number of driving units 340 can be reduced, and the circuit area can be reduced, thereby achieving the purpose of reducing the cost.
In addition, the driving circuit of the present invention further includes a line buffer 349. The line buffer 349 is used for temporarily storing the pixel data and transmitting the pixel data to the digital-to-analog conversion circuits 342.
Fig. 5 is a block diagram of a driving circuit of a display panel according to a second embodiment of the invention. As shown, the difference between the present embodiment and the embodiment of fig. 4 is that the present embodiment uses two voltage boosting units 346, 348, and the voltage boosting units 346, 348 respectively generate the second supply voltage VP2And a third supply voltage VP3The boost unit 346 delivers a second supply voltage VP2To the first half 340 of the driving units 340, and the boost unit 348 transmits the third supply voltage VP3 to the second half 340 of the driving units 340. In addition, the boosting units 346 and 348 do not necessarily need to allocate half of the driving units 340, but may allocate different ratios, for example, the boosting unit 346 is responsible for the first third of the driving units 340, the boosting unit 348 is responsible for the second two thirds of the driving units 340, or the boosting unit 346 is responsible for the first quarter of the driving units 340, and the boosting unit 348 is responsible for the second three quarters of the driving units 340.
In addition, the present invention is not limited to using one or two voltage boosting units, and the present invention can be applied to the driving units 340 from one voltage boosting unit to one driving unit 340.
Fig. 6 and fig. 7 are a block diagram of a driving circuit of a display panel according to a third embodiment of the invention and a circuit diagram of a driving unit according to a first embodiment of the invention. As shown, the present embodiment is different from the embodiment of fig. 4 in that the driving units 340 of the present embodiment simultaneously receive the first supply voltage V generated by the voltage boost circuit 344P1And a second supply voltage V generated by the boost unit 346P2As shown in fig. 7, the driving unit 340 of the present embodiment includes a differential unit 3400 and an output unit 3402. The differential unit 3400 receives a first supply voltage VP1For serving as a power source of the differential unit 3400 and generating a differential voltage V according to the gamma voltagedThe output unit 3402 receives a second supply voltage VP2For serving as a power supply of the output unit 3402 and according to the differential voltage VdGenerating a reference driving voltage Vref。
As mentioned above, the differential cell 3400 of the present embodiment includes the transistor 34000, the transistor 34002, the transistor 34004, the transistor 34006, and the current source 34008. A gate terminal of the transistor 34000 is coupled to the output line of the gamma circuit 32 to receive the gamma voltage output by the gamma circuit 32, a first terminal of the transistor 34000 is coupled to a first terminal of the transistor 34002, a gate terminal of the transistor 34002 is coupled to the output terminal of the driving unit 340, a second terminal of the transistor 34002 is coupled to a first terminal of the transistor 34004, a second terminal of the transistor 34004 is coupled to the power source to receive the first supply voltage V provided by the voltage boost circuit 344P1A gate terminal of the transistor 34004 is coupled to the gate terminal of the transistor 34006 and the first terminal of the transistor 34004, a first terminal of the transistor 34006 is coupled to a second terminal of the transistor 34000, a second terminal of the transistor 34006 is coupled to the power source terminal for receiving the first supply voltage V provided by the voltage boost circuit 344P1A first terminal of the current source 34008 is coupled to the first terminal of the transistor 34000 and the first terminal of the transistor 34002, and a second terminal of the current source 34008 is coupled to the reference potential.
Furthermore, the output unit 3402 of the present embodiment includes a transistor 34020 and a current source 34022. A gate terminal of the transistor 34020 is coupled to the second terminal of the transistor 34000 and the first terminal of the transistor 34006, a first terminal of the transistor 34020 is coupled to the output terminal of the driving unit 340, a second terminal of the transistor 34020 is coupled to the power source terminal to receive the second supply voltage V output by the voltage boosting unit 346P2A first terminal of the current source 34022 is coupled to the output terminal of the driving unit 340, and a second terminal of the current source 34022 is coupled to the reference potential. Thus, in the present embodiment, the differential unit 3400 and the output unit 3402 of the driving units 340 use boosting voltages respectivelyThe circuit 344 and the boosting unit 346 individually provide voltages to their corresponding components to improve the stability of the output voltage of the driving unit 340.
In addition, in addition to the differential unit 3400 and the output unit 3402 of the driving units 340 respectively using the respective supply voltages provided by the boosting circuit 344 and the boosting unit 346, the differential unit 3400 and the output unit 3402 of the driving units 340 of the invention can also simultaneously receive the second supply voltage V provided by the boosting unit 346P2。
Fig. 8 is a circuit diagram of a driving unit according to a second embodiment of the invention. As shown, the driving unit 340 of the present embodiment is different from the embodiment of fig. 7 in that a differential unit 3404 of rail-to-rail is used in the driving unit 340 of the present embodiment, and therefore, the driving unit 340 of the present embodiment includes the differential unit 3404 and an output unit 3406. The differential cell 3404 includes transistors 34040-34053.
A gate terminal of the transistor 34040 is coupled to the output terminal of the gamma circuit 32, a first terminal of the transistor 34040 is coupled to a first terminal of the transistor 34041, a second terminal of the transistor 34040 is coupled between the transistor 34046 and the transistor 34048, a gate terminal of the transistor 34041 is coupled to the output terminal of the driving unit 340, a second terminal of the transistor 34041 is coupled between the transistors 34047 and 34049, a first terminal of the current source 34042 is coupled to the first terminal of the transistor 34040 and the first terminal of the transistor 34041, and a second terminal of the current source 34042 is coupled to the power source terminal for receiving the first supply voltage V provided by the voltage boost circuit 344P1The gate of the transistor 34043 is coupled to the output terminal of the gamma circuit 32, a first terminal of the transistor 34043 is coupled to a first terminal of the transistor 34044, a second terminal of the transistor 34043 is coupled between the transistors 34050 and 34052, the gate of the transistor 34044 is coupled to the output terminal of the driving unit 340, a second terminal of the transistor 34044 is coupled between the transistors 34051 and 34053, a first terminal of the current source 34045 is coupled to the first terminal of the transistor 34043 and the first terminal of the transistor 34044, and a second terminal of the current source 34045 is coupled to the reference potential.
As mentioned above, the gate of the transistor 34046 of this embodiment is coupled to the gate of the transistor 34047, the transistor 34046 is coupled to the reference potential at a first terminal, and the transistor 34046 is coupled to a first terminal of the transistor 34048 at a second terminal. A first terminal of the transistor 34047 is coupled to the reference potential, and a second terminal of the transistor 34047 is coupled to the gate terminal of the transistor 34047 and a first terminal of the transistor 34049. The gate of transistor 34048 receives a first reference voltage Vb1A second terminal of the transistor 34048 is coupled to a first terminal of the transistor 34052. A gate terminal of the transistor 34049 receives a first reference voltage Vb1A second terminal of the transistor 34049 is coupled to a first terminal of the transistor 34053.
A gate terminal of the transistor 34050 is coupled to a gate terminal of the transistor 34051, a first terminal of the transistor 34050 is coupled to a second terminal of the transistor 34052, and a second terminal of the transistor 34050 is coupled to the power source terminal for receiving the first supply voltage V output by the voltage boost circuit 344P1. A first terminal of the transistor 34051 is coupled to a second terminal of the transistor 34053 and the gate terminal of the transistor 34051, and a second terminal of the transistor 34051 is coupled to the power source terminal for receiving the first supply voltage V output by the voltage boost circuit 344P1. The gates of the transistors 34052 and 34053 receive a second reference voltage Vb2。
The output cell 3406 of the present embodiment includes transistors 34060 and 34062. A gate terminal of the transistor 34060 is coupled to the first terminal of the transistor 34050, the second terminal of the transistor 34052 and the second terminal of the transistor 34043, a first terminal of the transistor 34060 is coupled to a first terminal of the transistor 34062 and the output terminal of the driving unit 340, a second terminal of the transistor 34060 is coupled to the power source terminal to receive the second supply voltage V output by the voltage boost unit 346P2. A gate of the transistor 34062 is coupled to the second terminal of the transistor 34046, the first terminal of the transistor 34048 is coupled to the second terminal of the transistor 34040, and a second terminal of the transistor 34062 is coupled to the reference potential. Therefore, it is able to avoid affecting the power supply of the differential unit 3404 of the driving units 340 and further affecting the differential voltage V output by the differential unit 3404 when the output current varies greatly due to the loaddThe level of (1). Thus, the differential unit 3404 and the output unit 3406 of the present embodiment use the respective supplies provided by the boost circuit 344 and the boost unit 346Voltage to improve the stability of the output voltage of the driving unit 340.
Fig. 9 is a block diagram of a driving circuit of a display panel according to a fourth embodiment of the invention. As shown, the present embodiment is different from the embodiment of fig. 6 in that the positions of the driving units 340 and the digital-to-analog conversion circuits 342 of the present embodiment are reversed, that is, the output terminal of the gamma circuit 32 is coupled to the digital-to-analog conversion circuits 342, the output terminals of the digital-to-analog conversion circuits 342 are coupled to the driving units 340, respectively, that is, the digital-to-analog conversion circuits 342 receive the gamma voltages V of the gamma circuit 321~VrAnd selecting the gamma voltages V according to the pixel data1~VrOne of them is a reference driving voltage VrefThe driving units 340 respectively receive the reference driving voltages V outputted by the digital-to-analog conversion circuits 342ref1~VrefnAnd according to a reference driving voltage VrefGenerates a data driving voltage Vs, and transmits the data driving voltage Vs to the display panel 5 to display the image. The boosting circuit 344 and the boosting unit 346 are the same as those in the embodiment of fig. 6, and therefore, are not described herein again.
The driving units 340 of the present embodiment are also similar to the embodiment of fig. 6, and the driving units 340 simultaneously receive the first supply voltage V generated by the voltage boost circuit 344P1And a second supply voltage V generated by the boost unit 346P2In FIG. 7, the differential unit 3400 receives the first supply voltage VP1As a power source of the differential unit 3400, and the output unit 3402 receives the second supply voltage VP2Thus, the driving circuit of the display panel of the embodiment can also use the respective supply voltages provided by the voltage boost circuit 344 and the voltage boost unit 346 through the differential unit 3400 and the output unit 3402 of the driving unit 340 respectively to improve the stability of the output voltage of the driving unit 340.
Fig. 10 is a circuit diagram of a boosting unit according to a first embodiment of the invention. As shown, the boost unit 346 of the present embodiment may be a power supplyThe boost unit 346 of the capacitive boost circuit includes a fly capacitor 3460, transistors 3461-3464 and a storage capacitor Cs1. The fly capacitor 3460 is used for generating the second supply voltage VP2One terminal of the transistor 3461 is coupled to one terminal of the fly capacitor 3460, and the other terminal of the transistor 3461 receives an input voltage VINAnd controlled by a first control signal XA, the transistor 3462 is coupled to the fly capacitor 3460 and the transistor 3461 and controlled by a second control signal XB to output a second supply voltage VP2One terminal of the transistor 3463 is coupled to the other terminal of the flying capacitor 3460, and the other terminal of the transistor 3463 receives the input voltage VINAnd controlled by the second control signal XB, one end of the transistor 3464 is coupled to the fly capacitor 3460 and the transistor 3463, the other end of the transistor 3464 is coupled to a ground terminal and controlled by the first control signal XA and the storage capacitor Cs1Has one terminal coupled to the transistor 3462 and the storage capacitor Cs1The other end of the first and second voltage sources is coupled to a ground terminal to store and output a second supply voltage VP2. Thus, the boost unit 346 of the present embodiment receives the input voltage VINThen, the transistors 3461-3464 are controlled by the first control signal XA and the second control signal XB to generate the second supply voltage VP2And outputs to the driving units 340.
Fig. 11 is a block diagram of a driving circuit of a display panel according to a fifth embodiment of the invention. As shown, the present embodiment is different from the above embodiments in that the boosting unit 346 of the present embodiment does not need to have the storage capacitor Cs1, that is, there is a connection path between the boosting unit 346 and the driving units 340, and the connection path is not connected to the storage capacitor Cs 1. Furthermore, the design of the boosting unit 346 in fig. 4 without the storage capacitor Cs1 can also be adopted, that is, the boosting unit 346 and the driving units 340 have a connection path therebetween, and the connection path is not connected to the storage capacitor Cs 1. In fig. 5, the design of the boosting units 346 and 348 without the storage capacitors Cs1 and Cs3 may also be adopted, that is, a connection path is provided between the boosting unit 346 and the driving units 340, the storage capacitor Cs1 is not connected to the connection path, and a connection path is provided between the boosting unit 348 and the driving units 340, and the storage capacitor Cs3 is not connected to the connection path.
Referring to fig. 7 again, the driving unit 340 includes a driving unit 3400 and an output unit 3402. Accordingly, the boosting unit 346 shown in fig. 11 does not need to have the storage capacitor Cs1, and it can be designed to have a connection path between the boosting unit 346 and the output unit 3402, and the connection path does not have the storage capacitor Cs1 connected thereto. Furthermore, the design of the boosting unit 346 in fig. 6 without the storage capacitor Cs1 can also be adopted, that is, there is a connection path between the boosting unit 346 and the output unit 3402, and the connection path is not connected with the storage capacitor Cs 1.
In addition, referring to fig. 7 and 8, the driving unit 340 includes differential units 3400, 3404 and output units 3402, 3406. The boosting unit 346 is coupled to the output units 3402, 3406 of the driving unit 340, so that a connection path is formed between the boosting unit 346 and the output units 3402, 3406, and the storage capacitor Cs1 is not connected to the connection path. In addition to the above embodiments, the boosting unit 340 can also be coupled to the differential units 3400, 3404 and the output units 3402, 3406 of the driving unit 340, so that the boosting unit 346 and the differential units 3400, 3404 have connection paths between the output units 3402, 3406, respectively, and the connection paths are not connected with the storage capacitor Cs 1.
Fig. 12 is a circuit diagram of a boosting unit according to a second embodiment of the invention. As shown, the difference between the present embodiment and the embodiment of fig. 10 is that the boosting unit 346 of the present embodiment does not need to use the storage capacitor Cs1Since the boosting unit 346 of the present invention is used for providing the second supply voltage V of the driving units 340P2The driving unit 340 only needs to drive the panel (e.g., the display panel 5 shown in fig. 4) without the function of the digital-to-analog converter circuit (e.g., the digital-to-analog converter circuit 342 shown in fig. 4) to maintain the accurate supply voltage, so that the power source can be allowed to oscillate greatly without the storage capacitor, and therefore, the boost unit 346 of the present embodiment only needs to use the fly capacitor 3460 to generate the second supply voltage VP2Without the need of external storage capacitor Cs1I.e. byCan be used to supply the power required by the driving units 340, so as to reduce the circuit area and further achieve the purpose of reducing the cost.
Fig. 13 is a circuit diagram of a boosting unit according to a third embodiment of the invention. As shown, the boosting unit 346 of the present embodiment is different from the boosting unit 346 of the embodiments of fig. 10 and 12 in that the boosting unit 346 of the present embodiment is an inductive boosting unit, and the boosting unit 346 of the present embodiment includes a control transistor 3470, a diode 3472, a storage inductor 3474 and an output capacitor 3476. One terminal of the control transistor 3470 receives the input voltage VINAnd is controlled by a control signal VCA diode 3472 has one end coupled to the control transistor 3470, another end coupled to the ground terminal, and a storage inductor 3474 coupled to the control transistor 3470 and the diode 3472 for storing the input voltage VINAnd one end of the output capacitor 3476 is coupled to the storage inductor 3474, and the other end of the output capacitor 3476 is coupled to the ground terminal to store the input voltage VINAnd generates a second supply voltage VP2And outputs to the driving units 340. In summary, the present invention is not limited to the boosting unit 346 being a capacitive boosting unit and an inductive boosting unit, as long as the boosting circuit 344 and the boosting unit 346 respectively generate the first supply voltage VP1And a second supply voltage VP2And respectively transmit the first supply voltage VP1And a second supply voltage VP2The digital-to-analog converter circuit 342 and the driving unit 340 are all within the scope of the present invention.
In addition, since the digital-to-analog conversion circuits 342 and the driving units 340 respectively use different supply voltages provided by the boost circuits 344 and the boost units 346, the output capacitor 3476 of the present embodiment does not need to use a large capacitor, and therefore, the output capacitor 3476 of the present embodiment can be built in a chip and does not need to be externally mounted outside the chip, thereby saving circuit area.
Please refer to fig. 14A, which is a schematic structural diagram of a display module. As shown, the display module includes a display panel 5 and a driving module 6. The driving module 6 is electrically connected to the display panel 5 to drive the display panel 5 to display an image. The driving module 6 includes a flexible circuit board 60 and a driving chip 62.
The driving chip 62 is disposed at one side of the display panel 5 and electrically connected to the display panel 5, one side of the flexible printed circuit 60 is connected to one side of the display panel 5 and electrically connected to the driving chip 62, and the storage capacitor Cs2 is externally attached to the flexible printed circuit 60 in this embodiment.
Based on the above, please refer to fig. 14B, which is a schematic structural diagram of the display module of the present invention. As shown, the driving chip 62 of the present embodiment is different from the embodiment of fig. 14A in that the driving chip includes the driving units 340, the digital-to-analog converters 342, a voltage boosting circuit 344, and a voltage boosting unit 346. The connection and operation relationships among the driving units 340, the digital-to-analog converters 342, the voltage boosting circuit 344 and the voltage boosting unit 346 have been described above, and will not be described herein again. Since the digital-to-analog conversion circuits 342 and the driving units 340 respectively use the respective supply voltages provided by the boost circuits 344 and 346, the storage capacitor Cs2 required by the driving chip 62 can be greatly reduced and directly disposed in the driving chip 62, so that the external storage capacitor Cs2 is not required on the flexible circuit board 60, and even the driving chip 62 (including the driving circuit) does not need the external storage capacitor, thereby saving the circuit area and further saving the cost.
Fig. 15 is a flowchart of a manufacturing method of the display panel. As shown in the figure, the steps of the method for manufacturing a display panel according to the present invention first execute step S10 to provide the display panel 5, the flexible circuit board 60 and the driving chip 62, then execute step S12 to dispose the driving chip 62 on the display panel 5 (as shown in fig. 14A), and then execute step S14 to dispose the flexible circuit board 60 on the display panel 5 and electrically connect with the driving chip 62, wherein the flexible circuit board 60 does not need to be disposed with a storage capacitor Cs2 (as shown in fig. 14B).
Based on the above, since the digital-to-analog conversion circuits 342 and the driving units 340 respectively use the respective supply voltages provided by the boost circuits 344 and 346, the storage capacitor Cs2 required by the driving chip 62 can be greatly reduced and directly disposed in the driving chip 62, so that the external storage capacitor Cs2 is not required on the flexible circuit board 60, and even the driving chip 62 (including the driving circuit) does not need an external storage capacitor, therefore, the present invention does not need a plurality of processes for externally attaching the storage capacitor to the flexible circuit board 60, thereby shortening the process time and further reducing the cost.
In addition, the method of manufacturing the display panel of the present invention further includes a step S16 of disposing a backlight module (not shown) below the display panel 5 to provide a light source to the display panel 5.
In summary, in the driving circuit of the display panel of the invention, the plurality of driving units respectively generate a reference driving voltage according to a gamma voltage of a gamma circuit, the plurality of digital-to-analog conversion circuits respectively receive the reference driving voltages output by the driving units and respectively select one of the reference driving voltages as a data driving voltage according to a pixel data, the digital-to-analog conversion circuits transmit the data driving voltages to the display panel to display a picture, the voltage boosting circuit is configured to generate a first supply voltage and provide the first supply voltage to the digital-to-analog conversion circuits, and the at least one voltage boosting unit is configured to generate a second supply voltage and provide the second supply voltage to the driving units. Therefore, the invention uses different supply voltages provided by the booster circuit and the booster unit respectively by the plurality of digital-analog conversion circuits and the plurality of driving units, so that the occupied area of the storage capacitor externally connected with the driving circuit is reduced, even the external storage capacitor is not needed, the circuit area is saved, and the purpose of saving the cost is further achieved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, which is defined by the appended claims.