TFT array substrate structure
Technical Field
The invention relates to the technical field of display, in particular to a TFT array substrate structure.
Background
Thin Film Transistor Liquid Crystal displays (TFT-LCDs) are capable of displaying high-definition, continuous, and fine images, and are increasingly favored by consumers.
The TFT-LCD in the existing market generally includes a housing, a liquid crystal panel disposed in the housing, and a backlight module disposed in the housing. The Liquid Crystal panel is composed of a Color Filter (CF) Substrate, a thin film Transistor Array Substrate (TFT Array Substrate), and a Liquid Crystal Layer (Liquid Crystal Layer) disposed between the two substrates, and its operating principle is to apply a driving voltage to the two glass substrates to control the rotation of Liquid Crystal molecules of the Liquid Crystal Layer, so as to refract the light of the backlight module to generate a picture.
The TFT-LCD needs to display continuous, fine and high-definition pictures and needs to make brightness and darkness consistency change among pixels (pixels). Two continuously-changed pixels can be realized by the brightness difference formed by different switching time differences, but the method is difficult to realize in driving design; in another method, the differential pressure between the upper electrode and the lower electrode or between the driving electrodes is inconsistent by charging different electric quantities into the pixels in the same time, so that the deflection angles of the liquid crystal are inconsistent, the light transmittances are inconsistent, and the requirements of continuous change of brightness and darkness are met. In the prior art, the effects of different charging saturation, different charging charges and inconsistent potential of different pixels in the same charging time are generally realized by reducing the potential of different pixels.
As shown in fig. 1, a design manner of using 3 TFTs as a driving unit has been commonly applied to control the charging saturation of a single pixel, wherein a gate line G is used to turn on a first charging TFT T1, a second charging TFT T2, and a discharging TFT T3, two TFTs, namely, the first charging TFT T1 and the second charging TFT T2, mainly write a data signal transmitted by a data line D into corresponding two adjacent pixels for charging, the discharging TFT T3 is directly electrically connected to the drain of the second charging TFT T2 and a common voltage line Com with a lower potential, and the charges of the pixel electrically connected to the second charging TFT T2 are led out to pull down the potential of the pixel. The advantages of such a design are: the potential of one of the two adjacent pixels can be effectively reduced without sacrificing the aperture ratio.
Referring to fig. 2 and 3 in conjunction with fig. 1, in order to connect the drain electrode D3 of the discharging TFT T3 and the common voltage line Com, the conventional TFT array substrate integrates a through hole V1 'penetrating through the drain electrode D3 of the discharging TFT T3 and the semiconductor active layer 400 therebelow, and a common via hole V2' penetrating through the gate insulating layer 200 between the semiconductor active layer 400 arranged below the drain electrode D3 of the discharging TFT T3 and the common voltage line Com, and the drain electrode D3 of the discharging TFT T3 and the common voltage line Com are connected by depositing a conductive film, such as Indium Tin Oxide (ITO), in the through hole V1 'and the common via hole V2'. In the conventional TFT array substrate, dry etching including both chemical etching and physical etching is used to fabricate the integrated through hole V1 'and the common via hole V2', and the semiconductor active layer 400 and the gate insulating layer 200 under the drain D3 of the discharge TFT T3 are subjected to dry etching with sulfur hexafluoride (SF) gas6) A chemical reaction is performed to generate gas volatilization, and the material composition of the semiconductor active layer 400 (the material composition is amorphous silicon (a-Si) and N-type heavily doped amorphous silicon (N + a-Si)) is different from that of the gate insulating layer 200 (the material composition is silicon nitride (SiNx)) due to the difference between the material compositions of the semiconductor active layer 400 and the gate insulating layer 2006The etching reaction rates of the TFT array substrate are different, and the metal section of the drain electrode D3 of the discharge TFT T3 and the section of the semiconductor active layer 400 are exposed by the via hole V1 'and the common via hole V2', so that a chamfer (underrout) problem (circled by a dotted line ellipse) as shown in fig. 3 is formed at the interface between the drain electrode D3 of the TFT T3 and the semiconductor active layer 400 and at the interface between the semiconductor active layer 400 and the gate insulating layer 200, which easily causes the risk of ITO ramp-off and contact failure, and affects the yield and reliability of the TFT array substrate.
Disclosure of Invention
The invention aims to provide a TFT array substrate structure which can avoid the problem of chamfering, prevent the risks of breakage and poor contact of a conductive film, ensure reliable connection between a discharge TFT and a common voltage line and improve the yield and the reliability of the TFT array substrate.
In order to achieve the above object, the present invention provides a TFT array substrate structure, which includes a first metal layer, a gate insulating layer, a semiconductor active layer, a second metal layer, and a passivation insulating layer, which are stacked in sequence from bottom to top;
the TFT array substrate structure is provided with a plurality of pixel regions which are arranged in an array manner, in two longitudinally adjacent pixel regions, the first metal layer comprises a common voltage line and a gate line which extend along the transverse direction, the second metal layer comprises a data line which extends along the longitudinal direction, a first source electrode which is connected with the data line, a second source electrode which is connected with the data line, a first drain electrode which is arranged opposite to the first source electrode, a second drain electrode which is arranged opposite to the second source electrode, a third source electrode which is connected with the second drain electrode, and a third drain electrode which is arranged opposite to the third source electrode; the passivation insulating layer covers the second metal layer, the semiconductor active layer and the grid electrode insulating layer;
a first through hole penetrating through the passivation insulating layer is formed in the passivation insulating layer, and the first through hole exposes out of part of the surface of the third drain electrode; a second through hole penetrating through the passivation insulating layer and the grid insulating layer is formed in the passivation insulating layer and the grid insulating layer, and the second through hole is exposed out of part of the surface of the common voltage line; the first through hole and the second through hole are arranged at intervals along the transverse direction; and conductive films for connecting the third drain electrode and the common voltage line are deposited in the first through hole, the second through hole and between the first through hole and the second through hole.
The gate line, the first source electrode and the first drain electrode form a first charging TFT, the gate line, the second source electrode and the second drain electrode form a second charging TFT, and the gate line, the third source electrode and the third drain electrode form a discharging TFT;
the first drain electrode is connected with one pixel electrode, and the second drain electrode is connected with the other pixel electrode.
The openings of the first through hole and the second through hole are rectangular or circular.
The opening size of the first through hole is larger than 5 um.
The opening size of the second through hole is larger than 5 um.
The distance between the first through hole and the boundary between the first through hole and the second through hole from the third drain electrode is greater than 4 um.
The distance between the second through hole and the boundary between the first through hole and the second through hole from the third drain electrode is larger than 4 um.
The gate insulating layer and the passivation insulating layer are made of silicon nitride; the conductive film is made of indium tin oxide.
The invention has the beneficial effects that: according to the TFT array substrate structure provided by the invention, a first through hole is formed in a passivation insulating layer, a second through hole is formed in the passivation insulating layer and a grid insulating layer, the first through hole and the second through hole are arranged at intervals along the transverse direction, and conductive films for connecting a third drain electrode and a common voltage line are deposited in the first through hole, the second through hole and between the first through hole and the second through hole; because the metal section of the third drain electrode and the section of the semiconductor active layer are both covered by the passivation insulating layer, under the protection effect of the passivation insulating layer, chamfering does not occur at the interface of the third drain electrode and the semiconductor active layer and the interface of the semiconductor active layer and the grid electrode insulating layer, so that the risks of breakage and poor contact of the conductive film can be prevented, the connection between the discharging TFT and the common voltage line is reliable, and the yield and the reliability of the TFT array substrate are improved.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a circuit diagram of a conventional TFT-based driving circuit;
fig. 2 is a front view of a conventional TFT array substrate structure;
FIG. 3 is a cross-sectional view corresponding to A-A in FIG. 2;
FIG. 4 is a front view of the TFT array substrate structure of the present invention;
fig. 5 is a sectional view corresponding to B-B in fig. 4.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 4 and 5, the present invention provides a TFT array substrate structure, which includes a first metal layer, a gate insulating layer 3, a semiconductor active layer 5, a second metal layer, and a passivation insulating layer 8 stacked in sequence from bottom to top.
The TFT array substrate structure is provided with a plurality of pixel regions which are arranged in an array manner, in two longitudinally adjacent pixel regions, the first metal layer comprises a common voltage line Com which extends along the transverse direction and a gate line G, the second metal layer comprises a data line D which extends along the longitudinal direction, a first source S1 which is connected with the data line D, a second source S2 which is connected with the data line D, a first drain D1 which is opposite to the first source S1, a second drain D2 which is opposite to the second source S2, a third source S3 which is connected with the second drain D2 and a third drain D3 which is opposite to the third source S3; the passivation insulating layer 8 covers the second metal layer, the semiconductor active layer 5, and the gate insulating layer 3. The semiconductor active layer 5 is covered by the respective sources and drains, and connects the first source S1 and the first drain D1, the second source S2 and the second drain D2, and the third source S3 and the third drain D3.
The gate line G, the first source S1, and the first drain D1 form a first charging TFT T1, the gate line G, the second source S2, and the second drain D2 form a second charging TFT T2, and the gate line G, the third source S3, and the third drain D3 form a discharging TFT T3. The first drain electrode D1 is connected to a pixel electrode P1, and the second drain electrode D2 is connected to another pixel electrode P2.
Specifically, the gate insulating layer 3 and the passivation insulating layer 8 are made of SiNx.
Unlike the prior art, in the TFT array substrate structure of the present invention, the passivation insulating layer 8 is provided with a first via V1 penetrating through the passivation insulating layer 8, and the first via V1 exposes a portion of the surface of the third drain D3; a second through hole V2 penetrating through the passivation insulating layer 8 and the gate insulating layer 3 is formed on the passivation insulating layer 8 and the gate insulating layer 3, and the second through hole V2 exposes a part of the surface of the common voltage line Com; the first through hole V1 and the second through hole V2 are arranged at intervals along the transverse direction; a conductive film 9 for connecting the third drain electrode D3 and the common voltage line Com is deposited in the first via hole V1, the second via hole V2, and between the first via hole V1 and the second via hole V2.
As shown in fig. 5, the metal profile of the third drain electrode D3 and the profile of the semiconductor active layer 5 are both covered by the passivation insulating layer 8, due to the protection of the passivation insulating layer 8, the chamfers are prevented from occurring at the interface of the third drain electrode D3 and the semiconductor active layer 5 and at the interface of the semiconductor active layer 5 and the gate insulating layer 3, and only the passivation insulating layer 8 made of SiNx is etched when the first via hole V1 is formed, when the second through hole V2 is manufactured, only the passivation insulating layer 8 and the grid insulating layer 3 which is made of SiNx are required to be etched, the reaction rate of dry etching gas and SiNx is uniform, therefore, the profiles of the first through hole V1 and the second through hole V2 are gentle, the risks of breakage and poor contact of the conductive film 9 can be prevented, the connection between the discharging TFTT3 and the common voltage line Com is reliable, and the yield and the reliability of the TFT array substrate are improved.
Specifically, the material of the conductive thin film 9 is ITO.
Referring to fig. 1, the gate line G is used to turn on the first charging TFT T1, the second charging TFT T2, and the discharging TFT T3, the two TFTs of the first charging TFT T1 and the second charging TFT T2 mainly write the data signal transmitted by the data line D into the corresponding two adjacent pixels for charging, the source S3 and the drain D3 of the discharging TFT T3 are respectively electrically connected to the drain D2 of the second charging TFT T2 and the common voltage line Com with a lower potential, and the charges of the pixel electrically connected to the second charging TFT T2 are led out to pull down the potential of the pixel, so that the potentials of the two adjacent pixels are different.
Further, the opening shapes of the first through hole V1 and the second through hole V2 are both rectangular or circular. The opening size a1 of the first through hole V1 is greater than 5 um; the opening size a2 of the second through hole V2 is greater than 5 um.
In order to ensure that the second via V2 has a sufficient lateral spacing from the first via V1 to block etching of the semiconductor active layer 5 under the drain D3 of the tft t3, it is preferable that the distance b1 of the first via V1 from the boundary of the third drain D3 between the first via V1 and the second via V2 is greater than 4 um; the distance b2 of the second via V2 from the third drain D3 at the boundary between the first via V1 and the second via V2 is greater than 4 um.
In summary, in the TFT array substrate structure of the present invention, a first through hole is formed in a passivation insulating layer, a second through hole is formed in the passivation insulating layer and a gate insulating layer, the first through hole and the second through hole are laterally spaced apart, and a conductive film for connecting a third drain electrode and a common voltage line is deposited in the first through hole, the second through hole, and between the first through hole and the second through hole; because the metal section of the third drain electrode and the section of the semiconductor active layer are both covered by the passivation insulating layer, under the protection effect of the passivation insulating layer, chamfering does not occur at the interface of the third drain electrode and the semiconductor active layer and the interface of the semiconductor active layer and the grid electrode insulating layer, so that the risks of breakage and poor contact of the conductive film can be prevented, the connection between the discharging TFT and the common voltage line is reliable, and the yield and the reliability of the TFT array substrate are improved.
As described above, it will be apparent to those skilled in the art that various other changes and modifications can be made based on the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the appended claims.