CN107204325B - Capacitor array and method of manufacture - Google Patents

Abstract

The embodiment of the invention provides a capacitor array and a manufacturing method thereof. The capacitor array includes: the first group of capacitors comprises a first capacitor and a second capacitor, the second group of capacitors comprises a third capacitor and a fourth capacitor, the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all capacitors with mirror symmetry plane polar plates and comprise an upper polar plate and a lower polar plate, the same-layer plane polar plates of the first capacitor and the second capacitor are distributed in a mirror symmetry mode by taking a first symmetry axis as an axis, the same-layer plane polar plates of the third capacitor and the fourth capacitor are distributed in a mirror symmetry mode by taking a second symmetry axis as an axis, and a preset angle is formed between the first symmetry axis and the second symmetry axis. The signals coupled from one set of capacitors to the other set of capacitors are of substantially equal magnitude and form a common mode signal that can be filtered by the differential signal detection port, thereby improving the interference problem between the different capacitive channels.

Description

Capacitor array and manufacturing method

technical field

The invention relates to the field of electrical components, in particular to a capacitor array and a manufacturing method.

Background technique

Using capacitors to transmit signals between chips or modules with high voltage differences has a wide range of applications in communication modules and data buses. With the improvement of system integration, discrete capacitor devices are gradually replaced by integrated capacitors on chips.

Integrated capacitors mostly adopt a planar structure, including two upper and lower plane metal plates, and the high-voltage isolation and electric field coupling between the capacitor plates are realized through the dielectric layer between the plates. With the shrinking of the system volume and the shortening of the pulse width of the transmission signal, the plate area of the integrated capacitor is correspondingly reduced, and the distance between adjacent capacitors is also continuously reduced. This results in enhanced coupling between plates of different capacitors, and stronger interference signals between capacitors belonging to different signal channels.

Although the traditional differential signal detection method can effectively filter the common-mode interference signal, it cannot eliminate the non-common-mode interference signal caused by the inherent inter-channel coupling of integrated capacitors, especially when using capacitors for bidirectional signal transmission, the inter-channel coupling The situation is more complex and significant. Therefore, how to solve the interference problem of different capacitive channels in the capacitive integration technology is an urgent problem to be solved in this field.

Contents of the invention

In view of this, the present invention provides a capacitor array and a manufacturing method to improve the interference problem of different capacitor channels in the existing capacitor integration technology.

To achieve the above object, the present invention provides the following technical solutions:

A capacitor array, comprising a first group of capacitors and a second group of capacitors, the first group of capacitors includes a first capacitor and a second capacitor, the second group of capacitors includes a third capacitor and a fourth capacitor, the first The capacitor, the second capacitor, the third capacitor and the fourth capacitor are all capacitors with mirror-image symmetrical plane plates, including an upper plate and a lower plate, and the same layer plates of the first capacitor and the second capacitor are separated by the first The axis of symmetry is a mirror-image symmetrical distribution of the axis, and the plates of the same layer of the third capacitor and the fourth capacitor are distributed in a mirror-symmetrical manner with the second axis of symmetry as an axis, and there is a predetermined gap between the first and second symmetry axes. set angle.

A method for manufacturing a capacitor array, which is used to manufacture the above-mentioned capacitor array, the method comprising: depositing a first dielectric layer on a substrate; using a metal material to form a first plate of a capacitor on the first dielectric layer; Form the second dielectric layer on the surface of the first pole plate and the surface of the first dielectric layer; use metal materials to form the second pole plate of the capacitor on the second dielectric layer; form the second pole plate on the surface of the second pole plate and the second The surface of the dielectric layer forms a third dielectric layer.

The beneficial effects of the capacitor array and manufacturing method provided by the embodiments of the present invention are:

The capacitor array and manufacturing method provided by the embodiments of the present invention include a first group of capacitors and a second group of capacitors, wherein the first group of capacitors includes a first capacitor and a second capacitor, the second group of capacitors includes a third capacitor and a fourth capacitor, and the second group of capacitors includes a third capacitor and a fourth capacitor. A capacitor, the second capacitor, the third capacitor and the fourth capacitor are all capacitors with mirror-image symmetrical plane plates, including an upper plate and a lower plate, and the same layer plates of the first capacitor and the second capacitor are separated by the first The axis of symmetry is distributed mirror-symmetrically to the axis, the plates of the same layer of the third capacitor and the fourth capacitor are distributed symmetrically to the axis of the second axis of symmetry, and the first axis of symmetry and the second axis of symmetry have a preset angle. The respective planar plates of the first capacitor and the second capacitor are mirror-symmetrical about the second axis of symmetry, and the respective planar plates of the third capacitor and the fourth capacitor are mirror-symmetrical about the first axis of symmetry, so the upper (lower) of the first capacitor The parasitic capacitance between the upper plate and the third capacitor, the fourth capacitor upper plate or the lower plate is symmetrical (equal), the second capacitor upper (lower) layer plate and the third capacitor, the fourth capacitor upper plate The parasitic capacitance between the plates or the lower plate is symmetrical (equal), and the parasitic capacitance between the upper (lower) plate of the third capacitor and the first capacitor, the upper plate or the lower plate of the second capacitor is symmetrical ( equal), the parasitic capacitance between the upper (lower) plate of the fourth capacitor and the first capacitor, the upper plate or the lower plate of the second capacitor is symmetrical (equal). Therefore, the magnitudes of signals coupled from one set of capacitors to another set of capacitors are completely equal, forming a common-mode signal, which can be filtered by the differential signal detection port, thereby improving the interference problem of different capacitor channels.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic top view of a partial structure of a capacitor array provided by the first embodiment of the present invention;

2 is a schematic top view of a single-layer plate of a specific embodiment of the capacitor array provided by the first embodiment of the present invention;

3a is a schematic top view of the upper plate of the capacitor array provided by the first embodiment of the present invention;

3b is a schematic top view of the lower plate of the capacitor array provided by the first embodiment of the present invention;

Fig. 4a is a schematic structural diagram of a capacitor array provided by a second embodiment of the present invention;

Fig. 4b is a schematic top view of the upper plate of the capacitor array shown in Fig. 4a;

Fig. 4c is a schematic top view of the lower plate of the capacitor array shown in Fig. 4a;

5 is a step-by-step schematic diagram of a method for manufacturing a capacitor array shown in an embodiment of the present invention;

FIG. 6 is a schematic flowchart of a method for manufacturing a capacitor array shown in an embodiment of the present invention.

Icon: 10-capacitor array; 110-first capacitor; 111-first capacitor; 112-second capacitor; 120-second capacitor; 121-third capacitor; 122-fourth capacitor; 130-first symmetry Axis; 140-second symmetry axis; 150-conductor structure; 161-first routing; 162-second routing; 163-third routing; 164-fourth routing; 171-first pad; 172 - second pad; 173 - third pad; 174 - fourth pad; 180 - parasitic capacitance; 191 - upper plate; 192 - lower plate; 193 - sub-plate; 201 - first opening; 202 - second opening; 210 - substrate; 220 - first dielectric layer; 230 - first polar plate; 240 - second dielectric layer; 250 - second polar plate; 260 - third dielectric layer.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. The following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

Please refer to FIG. 1 for details. FIG. 1 shows a schematic top view of a capacitor array 10 provided by a first embodiment of the present invention. The capacitor array 10 includes a first set of capacitors 110 and a second set of capacitors 120 . Wherein, the first set of capacitors 110 includes a first capacitor 111 and a second capacitor 112 , and the second set of capacitors 120 includes a third capacitor 121 and a fourth capacitor 122 .

The above capacitors all include an upper plate 191 and a lower plate 192 . The lower pole plate 192 of the above-mentioned capacitor is made by the same process step, and is roughly located in a plane; the upper pole plate 191 of the above-mentioned capacitor is also made by the same process step, and is also roughly positioned in a plane; so the upper pole plate 191 and the bottom pole of the capacitor Plates 192 are planar plates. The positions and shapes of the upper and lower pole plates of the above-mentioned capacitor correspond to each other in the vertical direction, so the upper pole plate and the lower pole plate of the capacitor overlap in the schematic plan view. The top view schematic diagram shown in FIG. It represents a schematic top view of the lower plate 192 .

Mirror symmetry in the present invention means that the figure is folded along the axis of symmetry, and the parts on both sides of the axis of symmetry can overlap with each other. The mirror image symmetry of a three-dimensional structure such as a plane polar plate in the present invention means that the top view of the three-dimensional structure is mirror image symmetric.

The first capacitor 111 is a capacitor with a mirror-symmetrical plane plate, specifically, the upper and lower plane plates of the first capacitor 111 are both mirror-symmetrical in plan view. Similarly, the second capacitor 112 is a capacitor with a mirror-symmetrical plane plate, specifically, the upper and lower plane plates of the second capacitor 112 are both mirror-symmetrical in top view. In the plan view of the first capacitor 111 and the second capacitor 112 , the plates of the same layer are distributed symmetrically in mirror image with the first axis of symmetry 130 as the axis.

The third capacitor 121 is a capacitor with a mirror-symmetrical plane plate, specifically, the upper and lower plane plates of the third capacitor 121 are both mirror-symmetrical in plan view. Similarly, the fourth capacitor 122 is a capacitor with a mirror-symmetrical plane plate, specifically, the plan view shapes of the upper and lower plane plates of the fourth capacitor 122 are mirror-symmetrical figures. The shape of the plates of the third capacitor 121 may be different from the shape of the plates of the first capacitor 111 or the shape of the plates of the second capacitor 112 . The plan views of the same-layer plates of the third capacitor 121 and the fourth capacitor 122 are mirror-symmetrically distributed with the second axis of symmetry 140 as an axis.

Both the first capacitor 111 and the second capacitor 112 can be capacitors having mirror-image symmetrical plane plates with the second axis of symmetry 140 as the axis, and both the third capacitor 121 and the fourth capacitor 122 can be capacitors with the first axis of symmetry 130 as the axis. Axis of a capacitor with mirror-symmetric plane plates. Mathematically, it can be proved that when the plane plates of the first capacitor 111 and the second capacitor 112 are mirror-symmetrical about the second axis of symmetry 140, the plane plates of the first capacitor 111 and the second capacitor 112 are in the same layer with respect to the first The axis of symmetry 130 is mirror symmetrical; When the axis of symmetry 140 is mirror-symmetrical, and the preset included angle between the first axis of symmetry 130 and the second axis of symmetry 140 is 90°, the capacitor array has the best symmetry and its technical effect.

There is a preset angle between the first axis of symmetry 130 and the second axis of symmetry 140, specifically, the preset angle between the first axis of symmetry 130 and the second axis of symmetry 140 can be 80° to 100°, preferably, the first The preset angle between a symmetry axis 130 and the second symmetry axis 140 may be 90°.

In a specific implementation of the capacitor array 10 provided in the first embodiment of the present invention, it also includes a conductor structure 150, and the conductor structure 150 can be respectively arranged on the first capacitor 111, the second capacitor 112, the third capacitor 121, and the fourth capacitor For the edge position of the 122 pole plate, please refer to Figure 2 for details. The shape of the conductor structure 150 at the edge of the upper and lower plates of the same capacitor can be set independently, that is, its shape is determined according to the specific application needs of the upper and lower plates, so the edge conductor structures belonging to the upper and lower plates can have the same or different shapes. shape.

The area of the conductor structure 150 arranged on the edge of the first capacitor 111 plate is smaller than the area of the first capacitor 111. Preferably, the area of the conductor structure 150 arranged on the edge of the first capacitor 111 is less than or equal to 50% of the area of the plates of the first capacitor 111 .

The area of the conductor structure 150 arranged at the edge of the pole plate of the second capacitor 112 is smaller than the area of the pole plate of the second capacitor 112. Preferably, the area of the conductor structure 150 arranged at the edge of the pole plate of the second capacitor 112 is less than or equal to 50% of the area of the plates of the second capacitor 112 .

The area of the conductor structure 150 arranged at the edge of the pole plate of the third capacitor 121 is smaller than the area of the pole plate of the third capacitor 121; preferably, the area of the conductor structure 150 arranged at the edge of the pole plate of the third capacitor 121 is less than or equal to 50% of the area of the plate of the third capacitor 121 .

The area of the conductive structure 150 disposed on the edge of the plate of the fourth capacitor 122 is smaller than the area of the plate of the fourth capacitor 122 . Preferably, the area of the conductor structure 150 disposed at the edge of the plate of the fourth capacitor 122 is less than or equal to 50% of the area of the plate of the fourth capacitor 122 .

The conductor structure 150 arranged at the edge of the capacitor can form a structure that does not have the aforementioned symmetry with the pole plate of the capacitor or form a mirror-symmetric structure with other symmetry axes as axes. For example, referring to FIG. 2, the first capacitor 111 and the first capacitor 111 The top view pattern formed by the conductor structure 150 at the edge of the pole plate and the top view pattern formed by the second capacitor 112 and the conductor structure 150 at the edge of the second capacitor 112 do not have mirror symmetry. The shape of the conductor structure 150 at the edge of the upper and lower plates of the same capacitor can be set independently, that is, its shape is determined according to the specific application needs of the upper and lower plates, so the edge conductor structures belonging to the upper and lower plates can have the same or different shapes. Figure 2 only shows the top view of a layer of pole plates and their edge conductors.

The capacitor array 10 provided in the first embodiment of the present invention further includes a first wire 161, a second wire 162, a third wire 163, a fourth wire 164, a first pad 171, a second pad 172, a The third pad 173 and the fourth pad 174 .

Please refer to FIG. 3 a for details. In the upper plate 191 of the entire capacitor array 10 shown in the first embodiment, the first pad 171 , the second pad 172 , the third pad 173 and the fourth pad 174 are arranged as shown in FIG. The upper part shown in Figure 3a.

Wherein, the first capacitor 111 and the second capacitor 112 are distributed left and right, the third capacitor 121 and the fourth capacitor 122 are distributed up and down, and the shapes of the third capacitor 121 and the fourth capacitor 122 are respectively the same as those of the first capacitor 111 and the second capacitor 112. Shapes form relatively tight layouts. The first capacitor 111 is connected to the first pad 171 through the first wire 161, the second capacitor 112 is connected to the second pad 172 through the second wire 162, and the third capacitor 121 is connected to the third solder pad through the third wire 163. The pad 173 is connected, and the fourth capacitor 122 is connected to the fourth pad 174 through the fourth wire 164 .

Referring to FIG. 3 b for details, in the lower plate 192 of the entire capacitor array 10 shown in the first embodiment, the first pad 171 , the second pad 172 , the third pad 173 and the fourth pad 174 are arranged as shown in FIG. Lower part shown in 3b.

Wherein, the first capacitor 111 and the second capacitor 112 are distributed left and right, the third capacitor 121 and the fourth capacitor 122 are distributed up and down, and in the lower plate 192, the positions of the first capacitor 111 to the fourth capacitor 122 are the same as those on the upper plate. Corresponds to the position in 191. The first capacitor 111 is connected to the first pad 171 through the first wire 161, the second capacitor 112 is connected to the second pad 172 through the second wire 162, and the third capacitor 121 is connected to the third solder pad through the third wire 163. The pad 173 is connected, and the fourth capacitor 122 is connected to the fourth pad 174 through the fourth wire 164 . Therefore, in the upper plate 191 and the lower plate 192 of the capacitor array 10 shown in the first embodiment, except for the first pad 171, the second pad 172, the third pad 173, the fourth pad 174 and their respective The positions of the first wiring 161, the second wiring 162, the third wiring 163 and the fourth wiring 164 connected respectively are different, and the upper plate 191 and the lower plate 192 of the first capacitor 111 to the fourth capacitor 122 corresponding to the same position.

Moreover, the sum of the areas of the first wiring 161 and the first pad 171 may be smaller than the area of the plate of the first capacitor 111, and the sum of the areas of the second wiring 162 and the second pad 172 may be less than The area of the pole plate of the second capacitor 112, the sum of the areas of the third wiring 163 and the third pad 173 may be smaller than the area of the pole plate of the third capacitor 121, the fourth wiring 164 and the fourth welding pad The sum of the areas of the plates 174 may be smaller than the area of the plates of the fourth capacitor 122 .

Please refer to FIG. 4a for details. FIG. 4a shows a schematic structural diagram of the capacitor array 10 provided by the second embodiment of the present invention. The plates of the first capacitor 111 , the second capacitor 112 , the third capacitor 121 and the fourth capacitor 122 each include at least one sub-plate 193 . Using the sub-plate can shorten the distance from the plate to the pad and reduce the parasitic parameters.

The first capacitor 111 may include two sub-plates, please refer to FIG. 4a , FIG. 4b and FIG. 4c for details. Specifically, the two sub-plates may be connected by a conductor structure 150 . In the upper plate 191 of the capacitor array 10 shown in the second embodiment, the first pad 171, the second pad 172, the third pad 173 and the fourth pad 174 are located on the right side as shown in Fig. 4a and Fig. 4b . In the lower plate 192 of the capacitor array 10 shown in the second embodiment, the first pad 171, the second pad 172, the third pad 173 and the fourth pad 174 are located on the left side as shown in Fig. 4a and Fig. 4c .

In the upper plate 191 , please refer to FIG. 4 b , the first capacitor 111 is connected to the first pad 171 via the first wiring 161 through the conductor structure 150 connecting the two sub-plates. The two sub-plates of the second capacitor 112 can be connected to the second pad 172 through their respective second wires 162, the third capacitor 121 is connected to the third pad 173 through the third wire 163, and the fourth capacitor 122 It is connected to the fourth pad 174 through the fourth wire 164 .

In the lower plate 192, please refer to FIG. 4c, the two sub-plates 193 of the first capacitor 111 can be connected to the first pad 171 through their respective first wires 161, and the second capacitor 112 can be connected to the two sub-plates through the The conductor structure 150 is connected to the second pad 172 via the first trace 161 . The third capacitor 121 is connected to the third pad 173 through the third wire 163 , and the fourth capacitor 122 is connected to the fourth pad 174 through the fourth wire 164 .

Similarly, the third capacitor and the fourth capacitor may also include sub-plates, which will not be repeated here.

The working principle of the capacitor array 10 provided by the embodiment of the present invention is as follows:

The first set of capacitors 110 and the second set of capacitors 120 are respectively used to transmit two sets of different differential signals. Next, the second capacitor 112 is taken as an example for illustration:

Referring to FIG. 1 , since the planar plate of the second capacitor 112 has a mirror-symmetric top view shape, and in the first embodiment shown in FIG. is a mirror image of the axis. Therefore, in the absence of external interference, the second capacitor 112 is a symmetrical potential body during operation, that is, the electric field lines and potential distribution emitted by the second capacitor 112 are also about the plane perpendicular to the plane where the plane plate is located and passing through the second symmetrical potential body. The plane of the axis 140 is mirror-symmetrical. The electric fields that are mirror-symmetrical to the plane perpendicular to the plane where the planar pole plate is located and pass through the second axis of symmetry 140 are respectively coupled to the electric fields that are also mirror-symmetrically distributed about the plane that is perpendicular to the plane where the plane pole plate is located and passes through the second axis of symmetry 140. The third capacitor 121 and the fourth capacitor 122 . Therefore, the generated interference signal is also symmetrical.

Specifically referring to FIG. 1, a plurality of parasitic capacitances 180 are distributed between the second capacitor 112 and the third capacitor 121, such as the four parasitic capacitances 180 on the upper side shown in FIG. 1; between the second capacitor 112 and the fourth capacitor 122 Likewise, a plurality of parasitic capacitors 180 are also distributed, such as the four parasitic capacitors 180 on the lower side shown in FIG. 1 .

Since the parasitic capacitance 180 distributed between the second capacitor 112 and the third capacitor 121 and the parasitic capacitance 180 distributed between the second capacitor 112 and the fourth capacitor 122 are symmetrical, the second capacitor 112 is coupled to the third capacitor 121 And the signals coupled from the second capacitor 112 to the fourth capacitor 122 are completely equal in magnitude, forming a common mode signal. This common mode signal will be filtered by the differential signal detection port, so that no wrong signal will be generated on the signal channel corresponding to the second capacitor 112, and no wrong signal will be generated on the signal channel corresponding to the third capacitor 121 and the fourth capacitor 122. .

Similarly, the first capacitor 111, the third capacitor 121, and the fourth capacitor 122 can be verified one by one. The interference signal generated by the first capacitor 110 in the second capacitor 120 is a common mode signal with the same magnitude and the same direction. The interference signal generated by the second set of capacitors 120 in the first set of capacitors 110 is also a common-mode signal with the same magnitude and the same direction, and the common-mode signal can be filtered by the differential signal detection port.

The angle between the first axis of symmetry 130 and the second axis of symmetry 140 is 90 degrees, which is a better way to eliminate interference signals. Since the plates of the capacitor need to be connected to other components and circuits through wires and pads, the first The first set of capacitors 110 and the second set of capacitors 120 do not necessarily have strict symmetry, and the area of the portion without strict symmetry (such as the conductor structure 150 , traces, and pads) is smaller than the area of the symmetrical portion of the plate.

Therefore, the included angle between the first axis of symmetry 130 and the second axis of symmetry 140 can be in a range, for example, between 80 degrees and 100 degrees, or the area of the conductor structure 150 without symmetry is smaller than or equal to that of the one with symmetry. Half the area of the plate, the interference signal generated by the above-mentioned asymmetrical conductor structure 150 is relatively small, and the non-strictly symmetrical capacitor array 10 can still significantly reduce the intensity of the interference signal.

Refer to FIG. 6 for details. FIG. 6 shows the process of manufacturing the capacitor array 10, which specifically includes the following steps:

Step S110 , depositing a first dielectric layer 220 on the substrate 210 .

The substrate 210 may be a PCB board, a silicon wafer, glass or an organic substrate, as shown in FIG. 5( a ). The first dielectric layer 220 is deposited on the substrate 210. Commonly used materials for the first dielectric layer 220 include silicon oxide, silicon nitride, aluminum oxide, and polymers (such as polyimide, benzocyclobutene, etc.), as shown in Figure 5 (b) shown. This step can be omitted if the substrate is an insulator.

Step S120 , forming the first plate 230 of the capacitor on the first dielectric layer 220 using metal material.

The first pole plate 230 can be the above-mentioned lower pole plate 192, that is, the first pole plate 230 can be formed on the surface of the first dielectric layer 220 with a metal material (such as copper or aluminum) according to the shape shown in Figure 3b or Figure 4c , as shown in Figure 5(c).

Step S130 , forming a second dielectric layer 240 on the surface of the first electrode plate 230 and the surface of the first dielectric layer 220 .

Referring to Fig. 5(d), the surface of the first pole plate 230 and the first dielectric layer 220 is covered with the second dielectric layer 240. Since the lower pole plate 192 needs to be drawn out, it can be left on the upper left side of Fig. 5(d) The first opening 201 . If a thicker second dielectric layer 240 is required, it can be formed by multiple depositions.

Step S140 , forming the second plate 250 of the capacitor on the second dielectric layer 240 using a metal material.

The second pole plate 250 is the above-mentioned upper pole plate 191, specifically, it can be formed on the surface of the second dielectric layer 240 with a metal material according to the shape of Fig. 3a or Fig. 4b, see Fig. 5(e).

Step S150 , forming a third dielectric layer 260 on the surface of the second electrode plate 250 and the surface of the second dielectric layer 240 .

The surface of the second pole plate 250 and the second dielectric layer 240 is covered with the second pole plate 250 , and the second pole plate 250 may also be provided with a second opening 202 for leading out the upper pole plate 191 , see FIG. 5( f ).

The capacitor array 10 and the manufacturing method provided by the embodiment of the present invention include a first group of capacitors 110 and a second group of capacitors 120, wherein the first group of capacitors 110 includes a first capacitor 111 and a second capacitor 112, and the second group of capacitors 120 includes a third The capacitor 121 and the fourth capacitor 122, the first capacitor 111, the second capacitor 112, the third capacitor 121 and the fourth capacitor 122 are mirror symmetrical capacitors, and the top view of the plane plates of the first capacitor 111 and the second capacitor 112 Take the first symmetry axis 130 as the axis to form a mirror image symmetrical distribution, the planar plate top view figures of the third capacitor 121 and the fourth capacitor 122 take the second symmetry axis 140 as the axis to form a mirror image symmetrical distribution, and the first symmetry axis 130 and the second The axis of symmetry 140 has a preset angle. Since the first capacitor 111, the second capacitor 112, the third capacitor 121, and the fourth capacitor 122 are all mirror-symmetrical, and the first capacitor 111 and the second capacitor 112 are distributed mirror-symmetrically, the third capacitor 121 and the fourth capacitor 122 Mirror symmetrical distribution, so the parasitic capacitance 180 between the first capacitor 111 and the third capacitor 121, the fourth capacitor 122 is symmetrical, the parasitic capacitance 180 between the second capacitor 112 and the third capacitor 121, the fourth capacitor 122 is symmetrical. Similarly, the parasitic capacitance 180 of the third capacitor 121 and the fourth capacitor 122 in the first group of capacitors 110 is also symmetrical. Therefore, the magnitudes of signals coupled from one set of capacitors to another set of capacitors are completely equal, forming a common-mode signal, which can be filtered by the differential signal detection port, thereby improving the interference problem of different capacitor channels.

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention have been clearly and completely described above in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Accordingly, the above detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention but represents only selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship that is usually placed when the product of the invention is used, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying References to devices or elements must have a particular orientation, be constructed, and operate in a particular orientation and therefore should not be construed as limiting the invention. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions, and should not be construed as indicating or implying relative importance.

In the description of the present invention, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation", "installation", "connection" and "connection" should be understood in a broad sense, for example, it may be a fixed connection, It can also be a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

Claims (8)

1. A capacitor array, characterized in that, the capacitor array includes: a first group of capacitors and a second group of capacitors, the first group of capacitors includes the first capacitor and the second capacitor, and the second group of capacitors includes the first Three capacitors and a fourth capacitor, The first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all capacitors with mirror-image symmetrical plane plates, and include an upper plate and a lower plate, The same-layer planar plates of the first capacitor and the second capacitor are mirror-symmetrically distributed with the first symmetry axis as the axis, and the same-layer planar plates of the third capacitor and the fourth capacitor are arranged with the second symmetry axis as the axis. Mirror symmetrical distribution, the first symmetry axis and the second symmetry axis have a preset angle; Wherein, the mirror symmetry refers to folding the image along the axis of symmetry, and the parts on both sides of the axis of symmetry can overlap each other; the angle range of the preset angle between the first axis of symmetry and the second axis of symmetry is [80 °,90°)∪(90°,100°]. 2. The capacitor array according to claim 1, characterized in that: The plates of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor all include at least one sub-plate. 3. The capacitor array according to claim 2, further comprising a conductor structure, Both the pole plates of the first capacitor and the pole plates of the second capacitor include a plurality of sub-plates, the multiple sub-plates of the pole plates of the first capacitor are connected through the conductor structure, and the pole plates of the second capacitor The plurality of sub-plates are connected through the conductor structure. 4. The capacitor array according to claim 1, characterized in that: it also includes a conductor structure, and the conductor structure is respectively arranged at the edge positions of the plates of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor , the conductor structure shapes of the upper and lower plates are set independently, and: the area of the conductor structure disposed at the edge of the plate of the first capacitor is smaller than the area of the plate of the first capacitor; The area of the conductor structure disposed at the edge of the plate of the second capacitor is smaller than the area of the plate of the second capacitor; The area of the conductor structure disposed at the edge of the pole plate of the third capacitor is smaller than the area of the pole plate of the third capacitor; The area of the conductor structure disposed at the edge of the pole plate of the fourth capacitor is smaller than the area of the pole plate of the fourth capacitor. 5. The capacitor array according to claim 4, characterized in that: The area of the conductor structure disposed at the edge of the plate of the first capacitor is less than or equal to half the area of the plate of the first capacitor; The area of the conductor structure disposed at the edge of the plate of the second capacitor is less than or equal to half the area of the plate of the second capacitor; The area of the conductor structure disposed at the edge of the plate of the third capacitor is less than or equal to half the area of the plate of the third capacitor; The area of the conductor structure disposed at the edge of the pole plate of the fourth capacitor is less than or equal to half of the area of the pole plate of the fourth capacitor. 6. The capacitor array according to claim 1, further comprising a first wiring, a second wiring, a third wiring, a fourth wiring, a first pad, a second pad, a third pad and the fourth pad, The first capacitor is connected to the first pad through a first wiring; The second capacitor is connected to the second pad through a second wire; The third capacitor is connected to the third pad through a third wire; The fourth capacitor is connected to the fourth pad through a fourth wire. 7. The capacitor array according to claim 6, characterized in that: The sum of the areas of the first wiring and the first pad is smaller than the area of the plate of the first capacitor; The sum of the areas of the second wiring and the second pad is smaller than the area of the plate of the second capacitor; The sum of the areas of the third wiring and the third pad is smaller than the area of the plate of the third capacitor; The sum of the areas of the fourth wiring and the fourth pad is smaller than the area of the plate of the fourth capacitor. 8. A method for manufacturing a capacitor array, used to manufacture the capacitor array as claimed in claim 1, characterized in that: Depositing a first dielectric layer on the substrate; forming a first plate of a capacitor on the first dielectric layer by using a metal material; forming a second dielectric layer on the surface of the first pole plate and the surface of the first dielectric layer; forming a second plate of the capacitor on the second dielectric layer using a metal material; A third dielectric layer is formed on the surface of the second polar plate and the surface of the second dielectric layer.

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