CN107204205A - Memory management method, memory control circuit unit and memory storage device - Google Patents

Abstract

The present invention provides a memory management method, a memory control circuit unit and a memory storage device. The method includes: setting a read disturbance threshold value for each physical erase unit; adjusting the read disturbance threshold value of the first physical erase unit according to the status information of the rewritable non-volatile memory module; and performing a read disturbance prevention operation according to the read disturbance threshold value of the first physical erase unit. Based on the above, the present invention proposes to dynamically adjust the read disturbance threshold value according to the number of erase times of the physical erase unit, so as to effectively reduce the probability of wear of the physical erase unit or the probability of read disturbance occurrence.

Description

Memory management method, memory control circuit unit and memory storage device

technical field

The invention relates to a memory management method, a memory control circuit unit and a memory storage device.

Background technique

The rapid growth of digital cameras, mobile phones, and MP3 players has led to a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility of data, power saving, small size, no mechanical structure, and fast read and write speed, it is most suitable for portable electronic products, such as notebook computers. A solid state drive is a memory storage device that uses a fast memory module as a storage medium. Therefore, the fast memory industry has become a very popular part of the electronics industry in recent years.

Generally speaking, a rewritable non-volatile memory module usually includes a plurality of physical erasing units, and each physical erasing unit includes a plurality of physical programming pages. In particular, the erasing times of the physical erasing unit in the rewritable non-volatile memory module are limited. For example, a physical erasing unit will wear out after 10,000 erasing operations. And when a physical erasing unit wears out, it will cause error bits to be generated when data is programmed (also called, written) to this physical erasing unit, and what is more serious will also cause disadvantages such as data loss or inability to store data. influences.

In addition, when the data stored in a physical programming unit in a physical erasing unit is read multiple times (for example, from one hundred thousand to one million times of reading), the data stored in the physical programming unit It is very likely that the data in the data will be wrong or lost due to the applied read voltage, and it may even cause the data stored in the same physical erasing unit to be wrong or lost in other physical programming units. Such phenomenon is commonly referred to as "read-disturb" by those skilled in the art of the present invention.

The rewritable non-volatile memory module has the phenomenon that the physical erasing unit will cause wear and read interference with use. These phenomena all drive manufacturers to develop various memory management methods to effectively reduce The probability of physically erasing unit wear or suppressing the probability of read disturb.

Contents of the invention

The present invention provides a memory management method, a memory control circuit unit and a memory storage device, which can effectively reduce the probability of physical erasing unit wear or suppress the probability of read interference, thereby improving the life of the rewritable non-volatile memory module cycle and reliability.

The present invention proposes a memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of entity erasing units, and each of the entity erasing units has a plurality of entities For programming units, the memory management method includes: setting a read disturbance threshold for each physical erasing unit; adjusting the read disturbance threshold of the first physical erasing unit according to the state information of the rewritable non-volatile memory module value; and perform a read disturb prevention operation according to the read disturb threshold value of the first physical erasing unit.

In an exemplary embodiment of the present invention, the above-mentioned step of adjusting the read disturbance threshold value of the first physical erasing unit according to the state information of the rewritable non-volatile memory module includes: recording the erasure of each physical erasing unit In addition to counting; and when the erasing count of the first physical erasing unit increases from the first count value to the second count value, adjusting the read disturbance threshold of the first physical erasing unit from the first threshold to the second A threshold value, wherein the second count value is greater than the first count value, and the second threshold value is smaller than the first threshold value.

In an exemplary embodiment of the present invention, the step of performing the read disturb prevention operation according to the read disturb threshold of the first physical erasing unit includes: determining the first physical programming unit corresponding to the first physical erasing unit Whether the number of times of reading is greater than the read disturbance threshold value of the first physical erasing unit; The data of the first physical erasing unit is copied to the second physical erasing unit among the physical erasing units.

In an exemplary embodiment of the present invention, the above-mentioned step of adjusting the read disturbance threshold value of the first physical erasing unit according to the state information of the rewritable non-volatile memory module includes: recording the erasure of each physical erasing unit counting, and when the erasing count of the first physical erasing unit increases from the first counting value to the second counting value, adjusting the read disturbance threshold of the first physical erasing unit from the third threshold to the fourth threshold The threshold value, wherein the second count value is greater than the first count value, and the fourth threshold value is greater than the third threshold value.

In an exemplary embodiment of the present invention, according to the read disturb threshold value of the first physical erasing unit, the step of performing the read disturb preventing operation includes: reading from the first physical programming unit of the first physical erasing unit Take a read data; judge whether the number of error bits of the read data read from the first physical programming unit is greater than the read disturbance threshold value of the first physical erasing unit; When the number of error bits in the read data is greater than the read disturbance threshold value of the first physical erasing unit, the data stored in the first physical erasing unit is copied to the second physical erasing unit in the physical erasing unit. remove the unit.

In an exemplary embodiment of the present invention, the step of adjusting the read disturbance threshold of the first physical erasing unit according to the state information of the rewritable non-volatile memory module includes: checking the rewritable non-volatile memory module temperature; and adjust the read disturb threshold of the first physical erasing unit according to the temperature of the rewritable non-volatile memory module.

In an exemplary embodiment of the present invention, the step of adjusting the read disturb threshold value of the first physical erasing unit according to the temperature of the rewritable non-volatile memory module includes: when the temperature of the rewritable non-volatile memory module When increasing from the first temperature value to the second temperature value, adjust the read disturbance threshold value of the first physical erasing unit from the fifth threshold value to the sixth threshold value, wherein the second temperature value is greater than the first temperature value, and the second temperature value is greater than the first temperature value, The sixth threshold is greater than the fifth threshold.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes: a host interface for electrically connecting to a host system; a memory interface for electrically connecting to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has multiple entities The erasing unit, each of the physical erasing units has a plurality of physical programming units; and a memory management circuit electrically connected to the host interface and the memory interface. The memory management circuit is used to set the read disturb threshold value for each physical erasing unit, adjust the read disturb threshold value of the first physical erasing unit according to the state information of the rewritable non-volatile memory module, and adjust the read disturb threshold value according to the first The read disturb threshold of the physical erase unit is used to prevent read disturb operations.

In an exemplary embodiment of the present invention, in the operation of adjusting the read disturbance threshold of the first physical erasing unit according to the state information of the rewritable non-volatile memory module, the memory management circuit is also used to record each The erasing count of the physical erasing unit, when the erasing count of the first physical erasing unit increases from the first count value to the second count value, the memory management circuit is also used to disturb the read of the first physical erasing unit The threshold value is adjusted from the first threshold value to a second threshold value, wherein the second count value is greater than the first count value, and the second threshold value is smaller than the first threshold value.

In an exemplary embodiment of the present invention, in the operation of performing the read disturb prevention operation according to the read disturb threshold value of the first physical erasing unit, the memory management circuit is also used to determine the corresponding first physical erasing unit Whether the reading frequency of the first physical programming unit is greater than the read disturbance threshold of the first physical erasing unit, if the corresponding reading frequency of the first physical programming unit is greater than the read disturbance threshold of the first physical erasing unit At this time, the memory management circuit is also used to copy the data stored in the first physical erasing unit to the second physical erasing unit among the physical erasing units.

In an exemplary embodiment of the present invention, in the operation of adjusting the read disturbance threshold of the first physical erasing unit according to the state information of the rewritable non-volatile memory module, the memory management circuit is also used to record each The erasing count of the physical erasing unit, when the erasing count of the first physical erasing unit increases from the first count value to the second count value, the memory management circuit is also used to disturb the read of the first physical erasing unit The threshold value is adjusted from the third threshold value to a fourth threshold value, wherein the second count value is greater than the first count value, and the fourth threshold value is greater than the third threshold value.

In an exemplary embodiment of the present invention, in the operation of performing the read disturb prevention operation according to the read disturb threshold value of the first physical erasing unit, the memory management circuit is further configured to erase the first physical erasing unit from the first physical erasing unit A physical programming unit reads a read data, and the memory management circuit is also used to determine whether the number of error bits of the read data read from the first physical programming unit is greater than the read disturbance of the first physical erasing unit Threshold value, if the number of error bits of the read data read from the first physical programming unit is greater than the read disturbance threshold value of the first physical erasing unit, the memory management circuit is also used to store in the first physical The data of the erasing unit is copied to the second physical erasing unit among the physical erasing units.

In an exemplary embodiment of the present invention, in the operation of adjusting the read disturbance threshold value of the first physical erasing unit according to the state information of the rewritable non-volatile memory module, the memory management circuit is also used to check the rewritable The memory management circuit is also used to adjust the read disturb threshold of the first physical erasing unit according to the temperature of the rewritable non-volatile memory module.

In an exemplary embodiment of the present invention, in the operation of adjusting the read disturbance threshold value of the first physical erasing unit according to the temperature of the rewritable non-volatile memory module, when the temperature of the rewritable non-volatile memory module When increasing from the first temperature value to the second temperature value, the memory management circuit is also used to adjust the read disturbance threshold value of the first physical erasing unit from the fifth threshold value to the sixth threshold value, wherein the second temperature value is greater than For the first temperature value, the sixth threshold value is greater than the fifth threshold value.

An exemplary embodiment of the present invention provides a memory storage device. It includes: a connection interface unit electrically connected to the host system, a rewritable non-volatile memory module, and a memory control circuit unit electrically connected to the connection interface unit and the rewritable non-volatile memory module. The rewritable non-volatile memory has a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units. The memory control circuit unit is used to set the read disturbance threshold value for each physical erasing unit, adjust the read disturbing threshold value of the first physical erasing unit according to a state information of the rewritable non-volatile memory module, and according to The read disturb threshold value of the first physical erasing unit is used to prevent the read disturb operation.

In an exemplary embodiment of the present invention, in the operation of adjusting the read disturbance threshold of the first physical erasing unit according to the state information of the rewritable non-volatile memory module, the memory control circuit unit is also used to record each The erasing count of a physical erasing unit, when the erasing count of the first physical erasing unit increases from the first count value to the second counting value, the memory control circuit unit is also used to read the first physical erasing unit The interference threshold value is adjusted from the first threshold value to a second threshold value, wherein the second count value is greater than the first count value, and the second threshold value is smaller than the first threshold value.

In an exemplary embodiment of the present invention, in the operation of performing the read disturb prevention operation according to the read disturb threshold value of the first physical erasing unit, the memory control circuit unit is also used to determine the corresponding first physical erasing unit Whether the read frequency of the first physical programming unit is greater than the read disturbance threshold of the first physical erasing unit, if the corresponding reading frequency of the first physical programming unit is greater than the read disturbance threshold of the first physical erasing unit When the value is high, the memory control circuit unit is also used to copy the data stored in the first physical erasing unit to the second physical erasing unit among the physical erasing units.

In an exemplary embodiment of the present invention, in the operation of adjusting the read disturbance threshold of the first physical erasing unit according to the state information of the rewritable non-volatile memory module, the memory control circuit unit is also used to record each The erasing count of a physical erasing unit, when the erasing count of the first physical erasing unit increases from the first count value to the second counting value, the memory control circuit unit is also used to read the first physical erasing unit The interference threshold is adjusted from the third threshold to the fourth threshold, wherein the second count is greater than the first count, and the fourth threshold is greater than the third threshold.

In an exemplary embodiment of the present invention, in the operation of performing the read disturb prevention operation according to the read disturb threshold value of the first physical erase unit, the memory control circuit unit is also used for erasing the first physical unit from the first physical erase unit The first physical programming unit reads a read data, and the memory control circuit unit is also used to judge whether the number of error bits of the read data read from the first physical programming unit is greater than that of the first physical erasing unit read disturbance threshold value, if the number of error bits of the read data read from the first physical programming unit is greater than the read disturbance threshold value of the first physical erasing unit, the memory control circuit unit is also used to store The data in the first physical erasing unit is copied to the second physical erasing unit among the physical erasing units.

In an exemplary embodiment of the present invention, in the operation of adjusting the read disturbance threshold of the first physical erasing unit according to the state information of the rewritable non-volatile memory module, the memory control circuit unit is also used to check the The temperature of the rewritable non-volatile memory module, the memory control circuit unit is also used to adjust the read disturb threshold of the first physical erasing unit according to the temperature of the rewritable non-volatile memory module.

In an exemplary embodiment of the present invention, in the operation of adjusting the read disturbance threshold value of the first physical erasing unit according to the temperature of the rewritable non-volatile memory module, when the temperature of the rewritable non-volatile memory module When increasing from the first temperature value to the second temperature value, the memory control circuit unit is also used to adjust the read disturbance threshold value of the first physical erasing unit from the fifth threshold value to the sixth threshold value, wherein the second temperature value greater than the first temperature value, and the sixth threshold value is greater than the fifth threshold value.

Based on the above, the present invention proposes to dynamically adjust the read disturbance threshold according to the erasing times of the physical erasing unit, so as to effectively reduce the probability of wear of the physical erasing unit or the occurrence of read disturbance.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment;

2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another exemplary embodiment;

3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 4 is a schematic block diagram of a host system and a memory storage device according to an exemplary embodiment;

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment.

FIG. 6 and FIG. 7 are exemplary schematic diagrams of a management entity erasing unit shown according to an exemplary embodiment;

FIG. 8 is a flowchart of a memory management method according to an exemplary embodiment;

FIG. 9 is a schematic diagram of adjusting the read disturb threshold according to the erasure count according to the first exemplary embodiment;

FIG. 10 is a flow chart of adjusting the read disturb threshold according to the erasure count according to the first exemplary embodiment;

FIG. 11 is a flow chart of performing read disturb prevention operations according to the first exemplary embodiment;

FIG. 12 is a schematic diagram of adjusting the read disturb threshold according to the erasure count according to the second exemplary embodiment;

FIG. 13 is a flow chart of adjusting the read disturb threshold according to the erase count according to the second exemplary embodiment;

FIG. 14 is a flow chart of performing read disturb prevention operations according to a second exemplary embodiment;

15A, 15B and 15C are schematic diagrams of adjusting the read disturb threshold according to the temperature of the rewritable non-volatile memory module according to the third exemplary embodiment;

FIG. 16 is a flow chart of adjusting the read disturb threshold according to the temperature according to the third exemplary embodiment.

Explanation of reference signs:

10: memory storage device;

11: host system;

12: input/output (I/O) device;

110: system bus;

111: processor;

112: random access memory (RAM);

113: read-only memory (ROM);

114: data transmission interface;

20: main board;

204: wireless memory storage device;

205: a global positioning system module;

206: network interface card;

207: wireless transmission device;

208: keyboard;

209: screen;

210: Horn;

30: memory storage device;

31: host system;

32: SD card;

33: CF card;

34: embedded storage device;

341: embedded multimedia card;

342: Embedded multi-chip package storage device;

402: connect the interface unit;

404: memory control circuit unit;

406: rewritable non-volatile memory module;

410(0)～410(N): Entity erasing unit;

502: memory management circuit;

504: host interface;

506: memory interface;

508: buffer memory;

510: power management circuit;

512: error checking and correction circuit;

514: temperature sensing circuit;

602: data area;

604: idle area;

606: system area;

608: replace area;

LBA(0)～LBA(H): logical address;

LZ(0)～LZ(M): logical area;

S801: A step of setting a reading interference threshold for each physical erasing unit;

S803: A step of adjusting the read disturbance threshold of the first physical erasing unit according to the state information of the rewritable non-volatile memory module;

S805: According to the read disturbance threshold value of the first physical erasing unit, perform the step of preventing the read disturbance operation;

S1001: A step of performing an erasing operation on the first physical erasing unit;

S1003: A step of updating the erase count of the first physical erase unit;

S1005: When the erasing count of the first physical erasing unit increases from the first count value to the second count value, adjust the read disturbance threshold of the first physical erasing unit from the first threshold to the second threshold , wherein the second count value is greater than the first count value, and the second threshold value is less than the first threshold value;

S1101: A step of performing a read operation on the first physical programming unit of the first physical erasing unit;

S1103: A step of updating the reading times corresponding to the first entity programming unit;

S1105: A step of judging whether the reading times of the first physical programming unit corresponding to the first physical erasing unit is greater than the read disturbance threshold of the first physical erasing unit;

S1107: A step of copying the data stored in the first physical erasing unit to the second physical erasing unit among the physical erasing units;

S1301: A step of performing an erasing operation on the first physical erasing unit;

S1303: A step of updating the erase count corresponding to the first physical erase unit;

S1305: When the erasing count of the first physical erasing unit increases from the first count value to the second count value, adjust the read disturb threshold of the first physical erasing unit from the third threshold to the fourth threshold , a step in which the second count value is greater than the first count value, and the fourth threshold value is greater than the third threshold value;

S1401: A step of reading read data from the first physical programming unit of the first physical erasing unit;

S1403: A step of judging whether the number of error bits in the read data read from the physical programming unit is greater than the read disturbance threshold of the first physical erasing unit;

S1405: A step of copying the data stored in the first physical erasing unit to the second physical erasing unit among the physical erasing units;

S1601: a step of checking the temperature of the rewritable non-volatile memory module;

S1603: When the temperature of the rewritable non-volatile memory module increases from the first temperature value to the second temperature value, adjust the read disturbance threshold value of the first physical erasing unit from the fifth threshold value to the sixth threshold value , wherein the second temperature value is greater than the first temperature value, and the sixth threshold value is greater than the fifth threshold value.

detailed description

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit unit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment, and FIG. 2 is a schematic diagram of a host system, a memory storage device, according to another exemplary embodiment. Schematic diagram of the device and input/output (I/O) devices.

Please refer to FIG. 1 and FIG. 2 , the host system 11 generally includes a processor 111 , a random access memory (random access memory, RAM) 112 , a read only memory (read only memory, ROM) 113 and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 and the data transmission interface 114 are all electrically connected to the system bus 110 .

In this exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114 . For example, the host system 11 can write data into the memory storage device 10 or read data from the memory storage device 10 through the data transmission interface 114 . In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O devices 12 through system bus 110 .

In this exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11 . The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114 , the motherboard 20 can be electrically connected to the memory storage device 10 by wire or wirelessly. The memory storage device 10 may be, for example, a USB flash drive 201 , a memory card 202 , a solid state drive (Solid State Drive, SSD) 203 or a wireless memory storage device 204 . The wireless memory storage device 204 may be, for example, a Near Field Communication Storage (NFC) memory storage device, a Wireless Fidelity (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device or a Bluetooth low energy storage device (such as , iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be electrically connected to a Global Positioning System (GPS) module 205 , a network interface card 206 , a wireless transmission device 207 , a keyboard 208 , a screen 209 , and a speaker 210 through the system bus 110 . I/O devices. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

In an example embodiment, reference to a host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiments, the host system is described as a computer system, however, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Please refer to FIG. 3 , in another exemplary embodiment, the host system 31 can also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be used for it SD card 32, CF card 33 or embedded storage device 34 and other non-volatile memory storage devices. The embedded storage device 34 includes various types such as an embedded multimedia card (embedded MMC, eMMC) 341 and/or an embedded multi-chip package storage device (embedded Multi Chip Package, eMCP) 342. The memory module is directly electrically connected to the host system. Embedded storage device on substrate.

FIG. 4 is a schematic block diagram of a host system and a memory storage device according to an exemplary embodiment.

Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed II (Ultra High Speed-II, UHS-II) interface standard, Secure Digital (Secure Digital, SD) interface standard, Memory Stick (Memory Stick, MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, multimedia storage Card (Multi Media Card, MMC) interface standard, Embedded Multimedia Card (eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi Chip Package (embedded Multi Chip Package, eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. In this exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 can be packaged in one chip, or the connection interface unit 402 is arranged outside a chip including the memory control circuit unit.

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or software, and write and read data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11. Fetch and erase operations.

The rewritable non-volatile memory module 406 is electrically connected to the memory control circuit unit 404 and used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 has physical erasing units 410(0)˜410(N). For example, the physical erase units 410(0)˜410(N) may belong to the same memory die or belong to different memory dies. Each physical erasing unit has a plurality of physical programming units, wherein the physical programming units belonging to the same physical erasing unit can be written independently and erased simultaneously. However, it must be understood that the present invention is not limited thereto, and each physical erasing unit may be composed of 64 physical programming units, 256 physical programming units, or any other number of physical programming units.

In more detail, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains the minimum number of memory cells to be erased together. Entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. Each physical programming unit generally includes a data bit field and a redundant bit field. The data bit area contains a plurality of physical access addresses for storing user data, and the redundant bit area is used for storing system data (eg, control information and error correction code). In this exemplary embodiment, the data byte area of each physical programming unit includes 8 physical access addresses, and the size of one physical access address is 512 bytes. However, in other exemplary embodiments, the data bit area may also include more or less physical access addresses, and the present invention does not limit the size and number of physical access addresses. For example, in an exemplary embodiment, the physical erasing unit is a physical block, and the physical programming unit is a physical page or a physical sector, but the invention is not limited thereto.

In this exemplary embodiment, the rewritable non-volatile memory module 406 is a complex number-level storage cell (Trinary Level Cell, TLC) NAND fast memory module (that is, a fast memory that can store 3 data bits in one storage unit) module). However, the present invention is not limited thereto, and the rewritable non-volatile memory module 406 may also be a multi-level memory cell (Multi Level Cell, MLC) NAND type fast memory module (that is, a memory cell that can store 2 data bits flash memory module) or other memory modules with the same characteristics.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment.

Referring to FIG. 5 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 and a memory interface 506 , a buffer memory 508 , a power management circuit 510 , an error checking and correction circuit 512 and a temperature sensing circuit 514 .

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data.

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in software. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

FIG. 6 and FIG. 7 are exemplary schematic diagrams of a management entity erasing unit according to an exemplary embodiment.

It must be understood that when describing the operation of the physical erasing unit of the rewritable non-volatile memory module 406, words such as "extract", "group", "divide", and "associate" are used to operate the physical erasing unit is a logical concept. That is to say, the actual position of the physical erasing unit of the rewritable non-volatile memory module is not changed, but the physical erasing unit of the rewritable non-volatile memory module is logically operated.

Please refer to FIG. 6, the memory control circuit unit 404 (or the memory management circuit 502) will logically group the physical erasing units 410(0)-410(N) into a data area 602, an idle area 604, a system area 606 and a replacement area. 608.

The physical erase units logically belonging to the data area 602 and the spare area 604 are used to store data from the host system 11 . Specifically, the physical erasing unit of the data area 602 is regarded as the physical erasing unit of stored data, and the physical erasing unit of the spare area 604 is used to replace the physical erasing unit of the data area 602 . That is to say, when receiving the write command and the data to be written from the host system 11, the memory management circuit 502 will use the entity erase unit extracted from the spare area 604 to write the data to replace the entity of the data area 602 Erase the unit.

The physical erase unit logically belonging to the system area 606 is used to record system data. For example, the system data includes the manufacturer and model of the rewritable non-volatile memory module, the number of physically erased units of the rewritable non-volatile memory module, the number of physically programmed units of each physically erased unit, and the like.

The physical erase units logically belonging to the replacement area 608 are used in the bad physical erase unit replacement process to replace the damaged physical erase units. Specifically, if there are still normal physical erasing units in the replacement area 608 and the physical erasing units in the data area 602 are damaged, the memory management circuit 502 will extract normal physical erasing units from the replacement area 608 to replace the damaged ones. The physical erasing unit.

In particular, the number of physical erasing units in the data area 602 , the spare area 604 , the system area 606 and the replacement area 608 varies according to different memory specifications. In addition, it must be understood that during the operation of the memory storage device 10 , the grouping relationship of the physical erasing unit associated with the data area 602 , the spare area 604 , the system area 606 and the replacement area 608 will change dynamically. For example, when the physical erasing unit in the spare area 604 is damaged and replaced by the physical erasing unit in the replacement area 608 , the original physical erasing unit in the replacement area 608 will be associated with the spare area 604 .

Referring to FIG. 7, the memory control circuit unit 404 (or the memory management circuit 502) configures logical addresses LBA(0)-LBA(H) to map the physical erasing units of the data area 602, wherein each logical address has multiple logical units to map the physical programming units of the corresponding physical erasing units. Moreover, when the host system 11 intends to write data to the logical address or update the data stored in the logical address, the memory control circuit unit 404 (or the memory management circuit 502) will extract a physical erase unit from the spare area 604 Write data as an active physical erasing unit to alternate the physical erasing units of the data area 602 . And, when this physical erasing unit as the active physical erasing unit is full, the memory control circuit unit 404 (or the memory management circuit 502) will extract an empty physical erasing unit from the idle area 504 as an active The physical erasing unit is used to continue writing update data corresponding to a write command from the host system 1000 . In addition, when the number of available physical erasing units in the spare area 604 is less than a preset value, the memory control circuit unit 404 (or the memory management circuit 502) will perform a valid data consolidation procedure (also called garbage collecting) program) to organize the valid data in the data area 602, so as to re-associate the physical erasing units in the data area 602 that do not store valid data to the spare area 604.

In order to identify which physical erasing unit the data of each logical address is stored in, in this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) will record the data between the logical address and the physical erasing unit map. For example, in this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores a logical address-physical address mapping table in the rewritable non-volatile memory module 406 to record each logical address The mapped entity erase unit. When accessing data, the memory control circuit unit 404 (or the memory management circuit 502) will load the logical address-physical address mapping table into the buffer memory 508 for maintenance, and perform the logical address-physical address mapping table according to the logical address-physical address mapping table Write or read data.

It is worth mentioning that due to the limited capacity of the buffer memory 508, it is impossible to store a mapping table that records the mapping relationship of all logical addresses. Therefore, in this exemplary embodiment, the memory control circuit unit 404 (or memory management circuit 502) will The logical addresses LBA(0)-LBA(H) are grouped into a plurality of logical zones LZ(0)-LZ(M), and a logical address-physical address mapping table is configured for each logical zone. In particular, when the memory control circuit unit 404 (or the memory management circuit 502) intends to update the mapping of a certain logical address, the logical address-physical address mapping table corresponding to the logical region to which the logical address belongs will be loaded to the buffer memory 508 to be updated.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 (for example, the system area dedicated to storing system data in the memory module) )middle. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a driver code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the driver code segment to store the control code stored in the rewritable non-volatile memory module 406. The instructions are loaded into random access memory of the memory management circuit 502 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 may also be implemented in a hardware manner. For example, the memory management circuit 502 includes a microcontroller, a memory unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The storage unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. Wherein, the storage unit management circuit is used to manage the physical erasing unit of the rewritable non-volatile memory module 406; the memory writing circuit is used to issue a write command to the rewritable non-volatile memory module 406 to write data into In the rewritable non-volatile memory module 406; the memory read circuit is used to issue a read instruction to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406; memory erase The circuit is used to issue an erase command to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406; and the data processing circuit is used to process the The data of the volatile memory module 406 and the data read from the rewritable non-volatile memory module 406.

Referring to FIG. 5 again, the host interface 504 is electrically connected to the memory management circuit 502 and used to electrically connect to the connection interface unit 402 to receive and identify commands and data transmitted by the host system 11 . That is to say, the commands and data sent by the host system 11 are sent to the memory management circuit 502 through the host interface 504 . In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 through the memory interface 506 .

The buffer memory 508 is electrically connected to the memory management circuit 502 and used for temporarily storing temporary data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 .

The power management circuit 510 is electrically connected to the memory management circuit 502 and used to control the power of the memory storage device 10 .

The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and used for executing error checking and correcting procedures to ensure the correctness of data. For example, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 512 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code, ECC Code) for the data corresponding to the write command. ), and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC code into the rewritable non-volatile memory module 406 . Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 512 will check and correct the code according to the error checking and correction code. The code performs error checking and correction procedures on the read data.

The temperature sensing circuit 514 is electrically connected to the memory management circuit 502 and used for checking the temperature of the rewritable non-volatile memory module 406 .

It should be noted that, assuming that the data stored in the first physical programming unit (also referred to as the physical programming unit 410(0)-1) in the physical erasing unit 410(0) is stored by the memory control circuit unit 404 When (or the memory management circuit 502) performs multiple reads (for example, the number of reads from one hundred thousand to one million times), since the memory control circuit unit 404 (or the memory management circuit 502) is A read voltage is applied to the storage cells in the physical programming unit 410(0)-1, and the data stored in the physical programming unit 410(0)-1 is likely to be generated due to the repeated application of the reading voltage to the storage cells Wrong bits or loss may even cause data stored in other physical programming units in the physical erasing unit 410(0) to have wrong bits or loss, which causes the problem of “read disturbance”.

Generally speaking, data error or loss caused by read disturbance can be avoided by judging whether the "read count" is greater than a read disturbance value. Specifically, taking the above-mentioned example where the memory control circuit unit 404 (or the memory management circuit 502) repeatedly reads the physical programming unit 410(0)-1, since the physical programming unit 410(0)-1 is After reading, error bits or data loss may occur in the physical erasing unit 410 (0), and the memory control circuit unit 404 (or memory management circuit 502) can determine that the corresponding memory is stored in the physical programming unit 410 (0)- Whether the number of times the data of 1 is read (ie, the number of reads) is greater than the read disturbance threshold is used to determine whether to move the data stored in the physical erasing unit 410 ( 0 ). Wherein if the number of reads corresponding to the data stored in the physical programming unit 410(0)-1 is greater than the read disturbance threshold, the memory control circuit unit 404 (or memory management circuit 502) will store the physical programming unit 410(0) )-1 is moved to, for example, other idle physical programming units, so as to prevent the data originally stored in the physical programming unit 410(0)-1 from being repeatedly read and generate too many error bits or data loss.

In addition, it is also possible to avoid data error or loss caused by read disturbance by judging whether the “number of error bits” of the read data is greater than a read disturbance value. Specifically, when the memory control circuit unit 404 (or the memory management circuit 502) reads a read data from the physical programming unit 410(0)-1 in the physical erasing unit 410(0), the memory control circuit unit 404 (or the memory management circuit 502) will read the error checking and correction code corresponding to the read data at the same time, and perform an error on the read data according to the error checking and correction code by the error checking and correction circuit 512. The check and correction program further calculates the number of error bits for the physical programming unit 410(0)-1 according to the number of error bits of the data stored in the physical programming unit 410(0)-1. Afterwards, the memory control circuit unit 404 (or the memory management circuit 502 ) can determine whether the number of error bits of the read data read from the physical programming unit 410(0)-1 is greater than the read disturb threshold. If the number of error bits in the read data read from the physical programming unit 410(0)-1 is greater than the read disturbance threshold, the memory control circuit unit 404 (or the memory management circuit 502) will program the physical programming unit The data in 410(0)-1 is moved to, for example, other idle entity programming units, to prevent the data stored in entity programming unit 410(0)-1 from being repeatedly read and generate more Bad bits or missing data.

However, it should be noted that in the prior art method of using "read times" or "number of error bits" to avoid read disturbance, the "read disturbance threshold" does not have a dynamic change mechanism, and this These methods do not take into account the wear and tear of the physical erasing unit. Wherein, it is assumed that when the physical erasing unit 410(0) wears out, it will cause the memory control circuit unit 404 (or the memory management circuit 502) to program data to the physical programming unit 410( When 0)-1, too many error bits will be generated, and more serious cases will cause, for example, data loss or failure to store data.

Based on this, the present invention proposes a memory management method, by dynamically adjusting the "read disturbance threshold" corresponding to the physical erasing unit according to the status information of the rewritable non-volatile memory module 406, so as to effectively reduce the The probability of physically erasing unit wear or suppressing the probability of read disturb.

FIG. 8 is a flow chart of a memory management method according to an exemplary embodiment.

Referring to FIG. 8 , in step S801 , the memory control circuit unit 404 (or the memory management circuit 502 ) sets a read disturb threshold for each physical erasing unit 410 ( 0 )˜410 (N).

Taking the physical erasing unit 410(0) as an example, in an exemplary embodiment of the present invention, the read disturbance threshold corresponding to the physical erasing unit 410(0) may be used to determine whether the physical erasing unit 410(0) ) to determine whether to move the data in the physical erasing unit 410(0) or not, whether the "reading times" of data stored in one of the physical programming units in ) is greater than a specific value.

In another exemplary embodiment of the present invention, the read disturb threshold corresponding to the physical erasing unit 410(0) may be one of the elements for judging from the physical programming unit in the physical erasing unit 410(0). Whether the "number of error bits" of the read data is greater than a specific value is used to determine whether to move the data in the physical erasing unit 410(0).

Next, in step S803 , the memory control circuit unit 404 (or the memory management circuit 502 ) adjusts the read disturb threshold of the first physical erasing unit according to the state information of the rewritable non-volatile memory module 406 . And in step S805, the memory control circuit unit 404 (or the memory management circuit 502) executes the read disturb prevention operation according to the read disturb threshold of the first physical erasing unit.

In an exemplary embodiment, the state information of the rewritable non-volatile memory module 406 may be an erase count of each physical erase unit 410( 0 )˜410(N) in the rewritable non-volatile memory module 406 . For example, the memory control circuit unit 404 (or the memory management circuit 502 ) records the erase count of each physical erase unit 410 ( 0 )˜410 (N). Specifically, in this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores an erase counter table in the rewritable non-volatile memory module 406 to record each physical erase unit 410 ( 0) to 410 (N) erase counts, and the memory control circuit unit 404 (or memory management circuit 502 ) will load the erase count table into the buffer memory 508 for maintenance. The memory control circuit unit 404 (or the memory management circuit 502 ) may correspondingly record ( or update) the erase count of the physical erase unit to be erased. Taking the physical erasing unit 410(0) as an example, assuming that the memory control circuit unit 404 (or memory management circuit 502) performs an erasing operation on the physical erasing unit 410(0), the memory control circuit unit 404 (or memory The management circuit 502) may add one to the erase count value corresponding to the physical erase unit 410(0) in the erase count table.

Afterwards, the memory control circuit unit 404 (or the memory management circuit 502) dynamically adjusts the read value corresponding to the physical erase unit 410(0) according to the erase count corresponding to the physical erase unit 410(0) in the erase count table. The interference threshold is used to change the timing of moving entity erasing data in the unit 410(0). Wherein, the read disturb prevention operation may be moving the data in the physical erasing unit 410(0), that is, copying the data in the physical erasing unit 410(0) to the physical erasing unit 410(0)～ In other entity erasing units in 410(N).

In addition, in another exemplary embodiment, the status information of the rewritable non-volatile memory module 406 may be the temperature of the rewritable non-volatile memory module 406 . For example, the memory controller 404 (or the memory management circuit 502) will check the temperature of the rewritable non-volatile memory module 406 through the temperature sensing circuit 514, and adjust the physical wiper according to the temperature of the rewritable non-volatile memory module 406. The read disturb thresholds of the units 410 ( 0 )˜ 410 (N) are divided. It is used to change the timing of moving the data in the physical erase unit 410(0). Wherein, the read disturb prevention operation may be moving the data in the physical erasing unit 410(0), that is, copying the data in the physical erasing unit 410(0) to the physical erasing unit 410(0)～ In other entity erasing units in 410(N).

Through the above method, the probability of wear of the physical erasing units 410 ( 0 )˜410 (N) can be reduced or the probability of read disturbance can be suppressed. Several exemplary embodiments are provided below for more detailed description.

First Exemplary Embodiment

In the first exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) will record the erase count of each physical erase unit 410(0)-410(N) in the erase count table , and dynamically adjust the read disturb threshold corresponding to the physical erase unit 410(0) according to the erase count corresponding to the physical erase unit 410(0) in the erase count table. In particular, in the first exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) judges the physical programming unit 410(0)-1 of the physical erasing unit 410(0) Whether the "read times" of the data is greater than the read disturbance threshold is used to determine whether to perform the read disturbance prevention operation. Based on the fact that the physical erasing unit will wear out due to too many times of erasing, it is assumed that when the physical erasing unit 410(0) wears out, it may cause data to be programmed to the physical programming unit 410(0)- When 1, an error bit is generated. At this time, if only a fixed read disturb threshold is used to avoid the read disturb of the physical erase unit 410 (0), in this case, when the memory control circuit unit 404 (or the memory management circuit 502) reads repeatedly When getting the data of the entity programming unit 410(0)-1 in the worn entity erasing unit 410(0), then the entity programming unit 410(0)-1 is likely to be in the entity programming unit 410(0) )-1 is not yet greater than the read disturbance threshold, due to the wear and tear of the physical erasing unit 410 (0) and repeated reading by the memory control circuit unit 404 (or memory management circuit 502). Too many error bits. That is to say, when the number of readings of the physical programming unit 410(0)-1 is not greater than the read interference threshold, the physical programming unit 410(0)-1 may be caused by the physical erasing unit 410(0) The erroneous bits generated by wear and tear, plus the additional erroneous bits that the physical programming unit 410(0)-1 is repeatedly read, result in the data stored in the physical programming unit 410(0)-1 Too many error bits are generated.

Therefore, in the first exemplary embodiment of the present invention, it is assumed that when the erasing times of the physical erasing unit 410(0) increase, the memory control circuit unit 404 (or the memory management circuit 502) will dynamically change the corresponding The read disturb number threshold of the erasing unit 410(0) is lowered, so as to prevent the data in the physical programming unit 410(0)-1 from generating too many error bits.

Specifically, assuming that when the memory control circuit unit 404 (or the memory management circuit 502) performs an erase operation on the physical erasing unit 410 (0) (hereinafter referred to as the first physical erasing unit), the memory control circuit unit 404 (or the memory management circuit 502) correspondingly increases the erase count of the first physical erase unit by one. Afterwards, when the erase count of the physical erase unit 410(0) increases from the first count value to the second count value, the memory control circuit unit 404 (or the memory management circuit 502) reads the read count of the physical erase unit 410(0) The interference threshold value is adjusted from the first threshold value to a second threshold value, wherein the second count value is greater than the first count value, and the second threshold value is smaller than the first threshold value.

For example, FIG. 9 is a schematic diagram of adjusting the read disturb threshold according to the erase count according to the first exemplary embodiment. Please refer to FIG. 9, in a state, assume that the erase count corresponding to the entity erase unit 410 (0) is recorded as 7000 (ie, the first count value), and the erase count corresponding to the entity erase unit 410 (0) The read disturb threshold is set to 90000 (ie, the first threshold). Assume that after a period of time, the memory control circuit unit 404 (or the memory management circuit 502) erases the erase operation corresponding to the physical erase unit 410 (0) due to performing 1000 erase operations on the physical erase unit 410 When the count increases to 8000 (that is, the second count value), the memory control circuit unit 404 (or the memory management circuit 502) will, for example, increase the erase count of the physical erase unit 410(0) to 8000, corresponding to The read disturbance threshold value of the physical erasing unit 410(0) is adjusted from 7000 to 9000 (ie, the second threshold value), so that when the number of times the physical erasing unit 410(0) is erased increases, the memory control circuit The unit 404 (or the memory management circuit 502 ) dynamically lowers the read disturb threshold corresponding to the physical erase unit 410(0). However, it should be noted that the present invention is not intended to limit the values of the above erase count and read disturb threshold, and the best correspondence between erase count and read disturb threshold can be determined according to different types of memory storage devices. Obtained by repeated experiments.

In addition, the memory control circuit unit 404 (or the memory management circuit 502) will also program each physical programming unit according to the number of times each physical programming unit in the physical erasing units 410(0)-410(N) is read. Records the read count.

For example, the memory control circuit unit 404 (or the memory management circuit 502) can be read according to the physical programming unit 410(0)-1 (ie, the first physical programming unit) in the physical erasing unit 410(0). The number of reads corresponding to the physical programming unit 410(0)-1 is recorded in the read count table. In this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores a read count table in the rewritable non-volatile memory module 406 to record each physical erase in each physical erase unit. The read count of the division unit, and the memory control circuit unit 404 (or the memory management circuit 502 ) loads the read count table into the buffer memory 508 for maintenance.

Afterwards, the memory control circuit unit 404 (or the memory management circuit 502) will judge whether the reading frequency of the physical programming unit 410(0)-1 corresponding to the physical erasing unit 410(0) is greater than the above-mentioned physical erasing unit 410(0) ) for the read disturb threshold. If the number of reads corresponding to the physical programming unit 410(0)-1 is greater than the read disturbance threshold of the physical erasing unit 410(0), the memory control circuit unit 404 (or the memory management circuit 502) will store the data stored in the physical erasing unit 410(0) The data of the erasing unit 410(0) is copied to a physical erasing unit among the physical erasing units 410(0)˜410(N).

In detail, since the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read erase count corresponding to the physical erase unit 410 (0) to 8000, the memory control circuit unit 404 (or the memory management circuit 502) Adjust the read disturbance threshold corresponding to the physical erasing unit 410(0) to 9000, assuming that the memory control circuit unit 404 (or the memory management circuit 502) continuously performs the physical program of the physical erasing unit 410(0). The programming unit 410(0)-1 performs a read operation, and the memory control circuit unit 404 (or the memory management circuit 502) can copy the The data stored in the physical erasing unit 410(0) is sent to, for example, the physical erasing unit 410(F) in the free area 604, and the erasing operation is performed on the physical erasing unit 410(0), and then the physical erasing unit 410(0) is associated to spare area 604 and physically erased unit 410(F) is associated to data area 602. However, it should be noted that the present invention is not intended to limit the manner of moving the data in the first physical erasing unit. In an exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ), for example, can copy and store in the physical programming unit 410(0)-1 after the 9001st read operation The data in 410(0)-1 is transferred to, for example, buffer memory 508, and after the erase operation is performed on the physical erasing unit 410(0), the data originally stored in the physical programming unit 410(0)-1 is reset from The buffer memory 508 is written back to the physical erase unit 410(0).

By means of the above method, when the number of erasing of the physical erasing unit 410 (0) increases, the memory control circuit unit 404 (or the memory management circuit 502) will dynamically change the read data corresponding to the physical erasing unit 410 (0) to The interference threshold is lowered to prevent the physical programming unit 410(0)-1 from being erased by the The erroneous bits generated by the wear and tear of 410(0) plus the additional erroneous bits caused by the repeated reading of the physical programming unit 410(0)-1 cause the physical programming unit 410(0)-1 to produce Too many error bits.

FIG. 10 is a flow chart of adjusting the read disturb threshold according to the erase count according to the first exemplary embodiment.

Referring to FIG. 10 , in step S1001 , the memory control circuit unit 404 (or the memory management circuit 502 ) performs an erase operation on the first physical erase unit. After that, in step S1003, the memory control circuit unit 404 (or the memory management circuit 502) updates the erase count of the first physical erase unit. Finally, in step S1005, when the erase count of the first physical erasing unit increases from the first count value to the second count value, the memory control circuit unit 404 (or the memory management circuit 502) sets the first physical erasing unit The read disturb threshold value is adjusted from the first threshold value to a second threshold value, wherein the second count value is greater than the first count value, and the second threshold value is smaller than the first threshold value.

FIG. 11 is a flow chart of performing read disturb prevention operations according to the first exemplary embodiment.

Referring to FIG. 11 , in step S1101 , the memory control circuit unit 404 (or the memory management circuit 502 ) performs a read operation on the first physical programming unit of the first physical erasing unit. Next, in step S1103, the memory control circuit unit 404 (or the memory management circuit 502) updates the reading times corresponding to the first physical programming unit. Afterwards, in step S1105, the memory control circuit unit 404 (or the memory management circuit 502) judges whether the read frequency of the first physical programming unit corresponding to the first physical erasing unit is greater than the read disturbance threshold of the first physical erasing unit value. If the reading times of the first physical programming unit corresponding to the first physical erasing unit is not greater than the read disturbance threshold of the first physical erasing unit, then step S1101 is executed. If the read frequency of the first physical programming unit corresponding to the first physical erasing unit is greater than the read disturbance threshold of the first physical erasing unit, then in step S1107, the memory control circuit unit 404 (or the memory management circuit 502) Copy the data stored in the first physical erasing unit to the second physical erasing unit in the physical erasing unit.

Therefore, in the first exemplary embodiment of the present invention, when the number of erasing times of a physical erasing unit increases, the memory control circuit unit 404 (or the memory management circuit 502) will dynamically change the number corresponding to the physical erasing unit The read disturb threshold of the physical erasing unit is lowered to avoid excessive error bits or data when the read count of one of the physical programming units in the physical erasing unit is not yet greater than the read disturb threshold lost.

Second exemplary embodiment

In the second exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) will record the erase count of each physical erase unit 410(0)-410(N) in the erase count table , and dynamically adjust the read disturb threshold corresponding to the physical erase unit 410(0) according to the erase count in the erase count table. In particular, in the second exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) judges whether the physical programming unit 410(0)-1 of the physical erasing unit 410(0) Whether the "error bit number" of the read data is greater than the read disturbance threshold value is used to determine whether to execute the read disturbance prevention operation. Based on the fact that the physical erasing unit will wear out due to too many times of erasing, it is assumed that when the physical erasing unit 410(0) wears out, it may cause data to be programmed to the physical programming unit 410(0)- When 1, an error bit is generated. If only a fixed read disturb threshold is used to avoid the read disturbance of the physical erasing unit 410(0), the wear and tear of the physical erasing unit 410(0) may cause data to be written into the physical programming unit 410 ( 0)-1 produces more error bits than the number of error bits. At this time, the memory control circuit unit 404 (or the memory management circuit 502 ) will move the data in the physical erasing unit 410(0) and execute the erasing operation on the physical programming unit 410(0). In this case, if the memory control circuit unit 404 (or the memory management circuit 502) repeatedly writes to one of the physical programming units in the worn physical erasing unit 410(0), it may be caused by writing data The number of error bits is greater than the error bit count threshold, causing the physical programming unit 410 ( 0 ) to be repeatedly erased, thereby increasing the wear and tear of the physical programming unit 410 ( 0 ).

Therefore, in the second exemplary embodiment of the present invention, it is assumed that when the erasing times of the entity erasing unit 410(0) increase, the memory control circuit unit 404 (or the memory management circuit 502) will dynamically change the corresponding entity The read disturb threshold of the erasing unit 410 ( 0 ) is increased to prevent the physical erasing unit 410 ( 0 ) from being subjected to excessive erasing operations and causing more serious wear and tear.

Specifically, assuming that when the memory control circuit unit 404 (or the memory management circuit 502) performs an erase operation on the physical erasing unit 410 (0) (hereinafter referred to as the first physical erasing unit), the memory control circuit unit 404 (or the memory management circuit 502) correspondingly increases the erase count of the first physical erase unit by one. Afterwards, when the erase count of the physical erase unit 410(0) increases from the first count value to the second count value, the memory control circuit unit 404 (or the memory management circuit 502) reads the read count of the physical erase unit 410(0) The interference threshold is adjusted from the third threshold to the fourth threshold, wherein the second count value is greater than the first count value, and the fourth threshold value is greater than the third threshold value.

For example, FIG. 12 is a schematic diagram of adjusting the read disturb threshold according to the erase count according to the second exemplary embodiment. Please refer to FIG. 12, in a state, assume that the erase count corresponding to the entity erase unit 410 (0) is recorded as 7000 (ie, the first count value), and the erase count corresponding to the entity erase unit 410 (0) The read disturb threshold is set to 90 (ie, the third threshold). Assume that after a period of time, the memory control circuit unit 404 (or the memory management circuit 502) erases the erase operation corresponding to the physical erase unit 410 (0) due to performing 1000 erase operations on the physical erase unit 410 When the count increases to 8000 (that is, the second count value), the memory control circuit unit 404 (or the memory management circuit 502) will, for example, adjust the read disturb threshold corresponding to the physical erasing unit 410 (0) from 90 to 100 (that is, the fourth threshold value), so that when the number of erasing of the physical erasing unit 410 (0) increases, the memory control circuit unit 404 (or the memory management circuit 502) will dynamically corresponding to the physical erasing unit 410 (0) read disturb threshold increased. However, it should be noted that the present invention is not intended to limit the values of the above erase count and read disturb threshold, and the best correspondence between erase count and read disturb threshold can be determined according to different types of memory storage devices. Obtained by repeated experiments.

In addition, the memory control circuit unit 404 (or the memory management circuit 502) will also program the first entity according to the number of error bits of the read data read by the first entity programming unit in the first entity erasing unit. The unit calculates the error bit count.

For example, when the memory control circuit unit 404 (or memory management circuit 502) reads from the physical programming unit 410(0)-1 (ie, the first physical programming unit) in the physical erasing unit 410(0) data, the memory control circuit unit 404 (or the memory management circuit 502) will simultaneously read the error checking and correction code corresponding to the data, and use the error checking and correction circuit 512 to correct the read The data performs error checking and correction procedures, and then calculates an error bit count for the physical programming unit 410(0)-1 according to the number of error bits in the data stored in the physical programming unit 410(0)-1. However, the present invention is not used to limit the timing of calculating the error bit count. In an exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) can also write data into the physical programming unit 410(0)- After 1, the error checking and correcting program is executed by the error checking and correcting circuit 512, and then according to the number of error bits of the data stored in the physical programming unit 410(0)-1, the physical programming unit 410(0)- 1 Calculates the error bit count.

Afterwards, the memory control circuit unit 404 (or the memory management circuit 502) will judge whether the number of error bits of the read data read from the physical programming unit 410(0)-1 is greater than that of the physical erasing unit 410(0) Read the interference threshold. If the number of error bits of the read data read from the physical programming unit 410(0) is greater than the read disturbance threshold of the physical erasing unit 410(0), the memory control circuit unit 404 (or the memory management circuit 502 ) will copy the data stored in the physical erasing unit 410(0) to a physical erasing unit among the physical erasing units 410(0)˜410(N).

In detail, since the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read erase count corresponding to the physical erase unit 410 (0) to 8000, the memory control circuit unit 404 (or the memory management circuit 502) Adjust the read disturbance threshold corresponding to the physical erasing unit 410(0) to 100, assuming that the memory control circuit unit 404 (or the memory management circuit 502) reads data from the physical programming unit 410(0)-1 at this time , the memory control circuit unit 404 (or memory management circuit 502) will simultaneously read the error checking and correction code corresponding to the data, and use the error checking and correction circuit 512 to correct the read data according to the error checking and correction code The error checking and correction procedure is executed, and then the error bit count is calculated for the physical programming unit 410(0)-1 according to the number of error bits of the data stored in the physical programming unit 410(0)-1. Assuming that the value of the error bit count of the physical programming unit 410(0)-1 is 101 at this time, the memory control circuit unit 404 (or the memory management circuit 502) can, for example, execute the physical programming unit 410(0)-1 After the read operation, copy the data stored in the physical erasing unit 410(0) to, for example, the physical erasing unit 410(F) in the spare area 604, and perform an erasing operation on the physical erasing unit 410(0), The physical erase unit 410 ( 0 ) is then associated to the spare area 604 and the physical erase unit 410 (F) is associated to the data area 602 . However, it should be noted that the present invention is not intended to limit the manner of moving the data in the first physical erasing unit. In an exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ), for example, after performing the 101st read operation on the physical programming unit 410(0)-1, copy and store The data in 410(0)-1 is transferred to, for example, buffer memory 508, and after the erase operation is performed on the physical erasing unit 410(0), the data originally stored in the physical programming unit 410(0)-1 is reset from The buffer memory 508 is written back into the physical erase unit 410(0).

By means of the above method, when the number of erasing of the physical erasing unit 410 (0) increases, the memory control circuit unit 404 (or the memory management circuit 502) will dynamically change the read data corresponding to the physical erasing unit 410 (0) to Take the disturbance threshold value to increase, so as to avoid the wear and tear of the physical erasing unit 410 (0) to cause the number of error bits that are more than the read disturbance threshold value to be generated when the data is written, causing the physical erasing unit 410 (0) to be blocked. Problems with frequent wipe operations. Based on the second exemplary embodiment of the present invention, the wear of the physical erasing unit 410(0) can be effectively slowed down.

FIG. 13 is a flow chart of adjusting the read disturb threshold according to the erase count according to the second exemplary embodiment.

Referring to FIG. 13 , in step S1301 , the memory control circuit unit 404 (or the memory management circuit 502 ) performs an erase operation on the first physical erase unit. Afterwards, in step S1303, the memory control circuit unit 404 (or the memory management circuit 502) updates the erase count corresponding to the first physical erase unit. Finally, in step S1305, when the erase count of the first physical erase unit increases from the first count value to the second count value, the memory control circuit unit 404 (or the memory management circuit 502) sets the first physical erase unit The read disturb threshold value is adjusted from the third threshold value to a fourth threshold value, wherein the second count value is greater than the first count value, and the fourth threshold value is greater than the third threshold value.

FIG. 14 is a flow chart of performing read disturb prevention operations according to the second exemplary embodiment.

Referring to FIG. 14 , in step S1401 , the memory control circuit unit 404 (or the memory management circuit 502 ) reads a read data from the first physical programming unit of the first physical erasing unit. Next, in step S1403, the memory control circuit unit 404 (or the memory management circuit 502) judges whether the number of error bits of the read data read from the physical programming unit is greater than the read disturbance threshold of the first physical erasing unit value. If the number of erroneous bits of the read data read from the physical programming unit is not greater than the read disturbance threshold of the first physical erasing unit, then step S1401 is executed. If the number of error bits in the read data read from the physical programming unit is greater than the read disturbance threshold of the first physical erasing unit, in step S1405, the memory control circuit unit 404 (or the memory management circuit 502) The data stored in the first physical erasing unit is copied to the second physical erasing unit in the physical erasing unit.

Therefore, in the second exemplary embodiment of the present invention, it is assumed that when a physical erasing unit is erased for an increasing number of times, the memory control circuit unit 404 (or the memory management circuit 502) will dynamically erase the The read disturb threshold of the unit is increased to prevent the physical erase unit from being subjected to excessive erasing operations and causing more severe wear and tear.

Third Exemplary Embodiment

In the third exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) checks the temperature of the rewritable non-volatile memory module 406 through the temperature sensing circuit 514, and according to the rewritable non-volatile The temperature of the volatile memory module 406 adjusts the read disturb thresholds of the physical erase units 410( 0 )˜410(N).

For example, the third embodiment of the present invention adjusts the read disturb threshold by judging the “number of error bits” and the temperature of the rewritable non-volatile memory module 406 . Taking the physical erasing unit 410(0) and the physical programming unit 410(0)-1 as examples, the memory control circuit unit 404 (or the memory management circuit 502) can determine the physical program of the physical erasing unit 410(0) Whether the "error bit number" of the read data read in the BL unit 410(0)-1 is greater than the read disturb threshold value is used to determine whether to perform the read disturb prevention operation. Wherein, it is assumed that when the erasing times of the physical erasing unit 410(0) increase, the memory control circuit unit 404 (or the memory management circuit 502) will dynamically disturb the read corresponding to the physical erasing unit 410(0) The threshold value is increased to prevent the physical erasing unit 410( 0 ) from being subjected to excessive erasing operations and causing more severe wear and tear. However, it should be noted that at this time, when the temperature of the rewritable non-volatile memory module 406 rises, the memory control circuit unit 404 (or the memory management circuit 502) is writing data into the rewritable non-volatile memory module. 406 entities are also more prone to error bits when programming units. Therefore, if the memory control circuit unit 404 (or the memory management circuit 502) writes to the physical programming unit 410(0)-1 in the high temperature physical erasing unit 410(0) again, the memory control circuit unit 404 (or the memory management circuit 502) may check that too many error bits have been generated in the physical programming unit 410(0)-1, then the memory control circuit unit 404 (or the memory management circuit 502) will move the physical erase data in unit 410(0) and perform an erase operation on physically programmed unit 410(0). In this case, if the memory control circuit unit 404 (or the memory management circuit 502) repeatedly writes to one of the physical programming units in the high temperature and worn physical erasing unit 410(0), it may be caused by The number of error bits in the written data is greater than the error bit count threshold, causing the physical programming unit 410( 0 ) to be repeatedly erased, further increasing the wear and tear of the physical programming unit 410( 0 ).

Therefore, in the third exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) checks the temperature of the rewritable non-volatile memory module 406 through the temperature sensing circuit 514, and according to the rewritable The temperature of the non-volatile memory module 406 adjusts the read disturb threshold of the first physical erase unit. In particular, when the temperature of the rewritable non-volatile memory module 406 increases from the first temperature value to the second temperature value, the memory control circuit unit 404 (or the memory management circuit 502) will erase the read data of the first entity erase unit. The interference threshold is adjusted from the fifth threshold to the sixth threshold, wherein the second temperature value is greater than the first temperature value, and the sixth threshold is greater than the fifth threshold.

In detail, FIG. 15A , FIG. 15B and FIG. 15C are schematic diagrams of adjusting the read disturb threshold according to the temperature of the rewritable non-volatile memory module according to the third exemplary embodiment.

Please refer to FIG. 15A, FIG. 15B and FIG. 15C at the same time. Assume that in the state of FIG. 15A, assuming that the current temperature of the rewritable non-volatile memory module 406 is 60°C, it corresponds to the erasing of the physical erasing unit 410(0). The count is recorded as 7000 (ie, the first count value), and the read disturb threshold corresponding to the physical erase unit 410(0) is set to 90 (ie, the third threshold). Assume that after a period of time, the memory control circuit unit 404 (or the memory management circuit 502) erases the erase operation corresponding to the physical erase unit 410 (0) due to performing 1000 erase operations on the physical erase unit 410 When the count increases to 8000 (that is, the second count value), the memory control circuit unit 404 (or the memory management circuit 502) will, for example, adjust the read disturb threshold corresponding to the physical erasing unit 410 (0) from 90 to 100 (that is, the fourth threshold value), so that when the number of erasing of the physical erasing unit 410 (0) increases, the memory control circuit unit 404 (or the memory management circuit 502) will dynamically corresponding to the physical erasing unit 410 (0) read disturb threshold increased.

Assuming that the temperature of the rewritable non-volatile memory module 406 rises from 60°C to 80°C at this time, as shown in FIG. Adjusted from 100 to 105 (ie, the fifth threshold).

Afterwards, assuming that the temperature of the rewritable non-volatile memory module 406 rises from 80° C. (ie, the first temperature value) to 100° C. (ie, the second temperature value), as shown in FIG. 15C , the memory control circuit unit 404 (or the memory management circuit 502 ), for example, can further adjust the read disturb threshold from 105 to 110 (ie, the sixth threshold).

Assume that when the memory control circuit unit 404 (or the memory management circuit 502) reads data from the physical programming unit 410(0)-1 at this time, the memory control circuit unit 404 (or the memory management circuit 502) will simultaneously read the data corresponding to The error checking and correcting code, and the error checking and correcting circuit 512 executes the error checking and correcting program on the read data according to the error checking and correcting code, and then according to the stored data in the physical programming unit 410(0)-1 The number of erroneous bits of the data of , calculates the erroneous bit count for the physical programming unit 410 ( 0 )- 1 . Assuming that the value of the error bit count of the physical programming unit 410(0)-1 is 111 at this time, the memory control circuit unit 404 (or the memory management circuit 502) can, for example, execute the physical programming unit 410(0)-1 After the read operation, copy the data stored in the physical erasing unit 410 (0) to, for example, the buffer memory 508, and perform an erasing operation on the physical erasing unit 410 (0), and then rewritable non-volatile After the temperature of the memory module 406 drops to a certain temperature value, the data originally stored in the physical programming unit 410(0)-1 is written back from the buffer memory 508 to the physical erasing unit 410(0).

However, it should be noted that the present invention is not used to limit the above-mentioned manner of moving the data in the first physical erase unit, and the present invention is not used to limit the above-mentioned erase count, temperature of the rewritable non-volatile memory module 406 and The value of the read disturbance threshold value, the erasure count, the temperature of the rewritable non-volatile memory module 406 and the optimal correspondence between the read disturbance threshold value can be obtained through repeated experiments according to different types of memory storage devices. have to.

By means of the above method, when the temperature of the rewritable non-volatile memory module 406 rises, the physical erasing unit 410( 0 ) is subjected to excessive erasing operations to cause more severe wear and tear.

FIG. 16 is a flow chart of adjusting the read disturb threshold according to the temperature according to the third exemplary embodiment.

In step S1601, the memory control circuit unit 404 (or the memory management circuit 502) will check the temperature of the rewritable non-volatile memory module 406, so as to adjust the first physical erase according to the temperature of the rewritable non-volatile memory module. The read disturb threshold for the cell.

Next, in step S1603, when the temperature of the rewritable non-volatile memory module 406 increases from the first temperature value to the second temperature value, the memory control circuit unit 404 (or the memory management circuit 502) will erase the first entity The read disturbance threshold value of the dividing unit is adjusted from the fifth threshold value to the sixth threshold value, wherein the second temperature value is greater than the first temperature value, and the sixth threshold value is greater than the fifth threshold value.

Therefore, in the third exemplary embodiment of the present invention, it is assumed that when the temperature of the rewritable non-volatile memory module 406 rises, the memory control circuit unit 404 (or the memory management circuit 502) will dynamically change the The read disturb threshold of the erasing unit 410 ( 0 ) is increased to prevent the physical erasing unit 410 ( 0 ) from being subjected to excessive erasing operations and causing more severe wear and tear.

It is worth mentioning that, in the third exemplary embodiment, the read disturb threshold corresponding to each physical erasing unit is dynamically adjusted according to the temperature of the rewritable non-volatile memory module 406, but the present invention is not limited to this. In another exemplary embodiment, the memory controller 404 (or the memory management circuit 502) can also consider the temperature of the rewritable non-volatile memory module 406 and the erase count of each physical erase unit to set the read Interference threshold. That is to say, the memory control circuit unit 404 (or the memory management circuit 502 ) in the above-mentioned first and second exemplary embodiments can be more as described in the third exemplary embodiment according to the temperature of the rewritable non-volatile memory module 406 to dynamically adjust the read disturb threshold corresponding to each physical erasing unit.

To sum up, since the rewritable non-volatile memory module has the phenomenon that the physical erasing unit will wear out and read interference, the present invention proposes to dynamically adjust the read interference threshold according to the erasing times of the physical erasing unit, In order to effectively reduce the probability of wear of the physical erasing unit or the probability of read interference.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (21)

1. a kind of storage management method, it is characterised in that for a rewritable non-volatile memory Module, wherein the rewritable non-volatile memory module have multiple entity erased cells, those realities Each entity erased cell among body erased cell has multiple entity program units, the memory Management method includes：

A reading interference threshold value is set for those each entity erased cells；

According to a status information of the rewritable non-volatile memory module, one first instance of adjustment is smeared Except the reading interference threshold value of unit；And

According to the reading interference threshold value of the first instance erased cell, perform one and prevent reading interference behaviour Make.

2. storage management method according to claim 1, it is characterised in that can be made carbon copies according to this The status information of formula non-volatile memory module, reading for adjusting the first instance erased cell is done The step of disturbing threshold value includes：

The one of those each entity erased cells are recorded to erase counting；And

When the counting of erasing of the first instance erased cell is counted from the increase of one first count value for one second During value, the reading interference threshold value of the first instance erased cell is adjusted to one from one first threshold value Second threshold value,

Wherein second count value is more than first count value, and second threshold value is less than first threshold Value.

3. storage management method according to claim 2, it is characterised in that according to first reality The reading interference threshold value of body erased cell, performing the step of prevention reading interference is operated includes：

Judge to should the reading times of a first instance programmed cell of first instance erased cell be The no reading interference threshold value more than the first instance erased cell；And

If to should first instance programmed cell the reading times be more than the first instance erased cell Reading interference threshold value when, will be stored in the data duplication of the first instance erased cell to those entities A second instance erased cell among erased cell.

4. storage management method according to claim 1, it is characterised in that can be made carbon copies according to this The status information of formula non-volatile memory module, reading for adjusting the first instance erased cell is done The step of disturbing threshold value includes：

The one of those each entity erased cells are recorded to erase counting；And

When the counting of erasing of the first instance erased cell is counted from the increase of one first count value for one second During value, the reading interference threshold value of the first instance erased cell is adjusted to one from one the 3rd threshold value 4th threshold value,

Wherein second count value is more than first count value, and the 4th threshold value is more than the 3rd threshold value.

5. storage management method according to claim 4, it is characterised in that according to first reality The reading interference threshold value of body erased cell, performing the step of prevention reading interference is operated includes：

Data are read from a first instance programmed cell of the first instance erased cell；

Judge whether is the wrong bit number of the reading data that is read from the first instance programmed cell More than the reading interference threshold value of the first instance erased cell；

If the wrong bit number of the reading data read from the first instance programmed cell is more than During the reading interference threshold value of the first instance erased cell, the first instance erased cell will be stored in Data duplication to those entity erased cells among a second instance erased cell.

6. storage management method according to claim 1, it is characterised in that can be made carbon copies according to this The status information of formula non-volatile memory module, reading for adjusting the first instance erased cell is done The step of disturbing threshold value includes：

Check a temperature of the rewritable non-volatile memory module；And

The first instance erased cell is adjusted according to the temperature of the rewritable non-volatile memory module The reading interference threshold value.

7. storage management method according to claim 6, it is characterised in that can be made carbon copies according to this The temperature of formula non-volatile memory module adjusts the reading interference threshold of the first instance erased cell The step of value, includes：

When the rewritable non-volatile memory module the temperature from the increase of one first temperature value be one the During two temperature values, the reading interference threshold value of the first instance erased cell is adjusted from one the 5th threshold value Whole is one the 6th threshold value,

Wherein the second temperature value is more than first temperature value, and the 6th threshold value is more than the 5th threshold value.

8. a kind of memorizer control circuit unit, it is characterised in that for controlling a duplicative non-volatile Property memory module, the memorizer control circuit unit includes：

One HPI, is electrically connected to a host computer system；

One memory interface, is electrically connected to the rewritable non-volatile memory module, wherein The rewritable non-volatile memory module has multiple entity erased cells, those entity erased cells Among each entity erased cell there are multiple entity program units；And

One memory management circuitry, is electrically connected to the HPI and the memory interface,

The memory management circuitry for those each entity erased cells to set a reading interference threshold Value,

The memory management circuitry is also used to the state according to the rewritable non-volatile memory module Information, adjusts the reading interference threshold value of a first instance erased cell,

The memory management circuitry is also used to the reading interference threshold according to the first instance erased cell Value, performs one and prevents reading interference operation.

9. memorizer control circuit unit according to claim 8, it is characterised in that can according to this The status information of manifolding formula non-volatile memory module, adjusts the reading of the first instance erased cell In the running for taking interference threshold value,

The memory management circuitry is also erased counting to record the one of those each entity erased cells,

When the counting of erasing of the first instance erased cell is counted from the increase of one first count value for one second During value, the memory management circuitry is also to by the reading interference threshold value of the first instance erased cell One second threshold value is adjusted to from one first threshold value,

Wherein second count value is more than first count value, and second threshold value is less than first threshold Value.

10. memorizer control circuit unit according to claim 9, it is characterised in that according to this The reading interference threshold value of first instance erased cell, in the running for performing prevention reading interference operation,

The memory management circuitry also to judge to should first instance erased cell a first instance journey Whether one reading times of sequence unit are more than the reading interference threshold value of the first instance erased cell,

If to should first instance programmed cell the reading times be more than the first instance erased cell Reading interference threshold value when, the memory management circuitry is also erased list will be stored in the first instance A second instance erased cell among the data duplication to those entity erased cells of member.

11. memorizer control circuit unit according to claim 8, it is characterised in that according to this The status information of rewritable non-volatile memory module, adjusts being somebody's turn to do for the first instance erased cell In the running of reading interference threshold value,

The memory management circuitry is also erased counting to record the one of those each entity erased cells,

When the counting of erasing of the first instance erased cell is counted from the increase of one first count value for one second During value, the memory management circuitry is also to by the reading interference threshold value of the first instance erased cell One the 4th threshold value is adjusted to from one the 3rd threshold value,

Wherein second count value is more than first count value, and the 4th threshold value is more than the 3rd threshold value.

12. memorizer control circuit unit according to claim 11, it is characterised in that according to this The reading interference threshold value of first instance erased cell, in the running for performing prevention reading interference operation,

The memory management circuitry is also used to the first instance sequencing list from the first instance erased cell Member reads data,

The reading of the memory management circuitry also to judge to be read from the first instance programmed cell Whether the wrong bit number of data is more than the reading interference threshold value of the first instance erased cell,

If the wrong bit number of the reading data read from the first instance programmed cell is more than During the reading interference threshold value of the first instance erased cell, the memory management circuitry will be also that will deposit Store up the second instance among the data duplication to those entity erased cells of the first instance erased cell Erased cell.

13. memorizer control circuit unit according to claim 8, it is characterised in that according to this The status information of rewritable non-volatile memory module, adjusts being somebody's turn to do for the first instance erased cell In the running of reading interference threshold value,

A temperature of the memory management circuitry also to check the rewritable non-volatile memory module Degree,

The memory management circuitry is also used to the temperature according to the rewritable non-volatile memory module Adjust the reading interference threshold value of the first instance erased cell.

14. memorizer control circuit unit according to claim 13, it is characterised in that according to this The reading that the temperature of rewritable non-volatile memory module adjusts the first instance erased cell is done In the running for disturbing threshold value,

When the rewritable non-volatile memory module the temperature from the increase of one first temperature value be one the During two temperature values, the memory management circuitry is also to by the reading interference of the first instance erased cell Threshold value is adjusted to one the 6th threshold value from one the 5th threshold value,

Wherein the second temperature value is more than first temperature value, and the 6th threshold value is more than the 5th threshold value.

15. a kind of memory storage apparatus, it is characterised in that including：

One connecting interface unit, is electrically connected to a host computer system；

One rewritable non-volatile memory module, with multiple entity erased cells, those entities are smeared Except each entity erased cell among unit has multiple entity program units；And

One memorizer control circuit unit, is electrically connected to the connecting interface unit and the duplicative is non-waves Hair property memory module,

Wherein the memorizer control circuit unit is dry to be read for those each entity erased cells setting one Disturb threshold value,

The memorizer control circuit unit is also used to according to the one of the rewritable non-volatile memory module Status information, adjusts the reading interference threshold value of a first instance erased cell,

The memorizer control circuit unit is also used to the reading interference door according to the first instance erased cell Threshold value, performs one and prevents reading interference operation.

16. memory storage apparatus according to claim 15, it is characterised in that can be answered according to this The status information of formula non-volatile memory module is write, the reading of the first instance erased cell is adjusted In the running for disturbing threshold value,

The memorizer control circuit unit is also erased meter to record the one of those each entity erased cells Number,

When the counting of erasing of the first instance erased cell is counted from the increase of one first count value for one second During value, the memorizer control circuit unit is also to by the reading interference of first instance erased cell door Threshold value is adjusted to one second threshold value from one first threshold value,

Wherein second count value is more than first count value, and second threshold value is less than first threshold Value.

17. memory storage apparatus according to claim 16, it is characterised in that according to this first The reading interference threshold value of entity erased cell, in the running for performing prevention reading interference operation,

The memorizer control circuit unit also to judge to should first instance erased cell it is one first real Whether one reading times of body programmed cell are more than the reading interference threshold of the first instance erased cell Value,

If to should first instance programmed cell the reading times be more than the first instance erased cell Reading interference threshold value when, the memorizer control circuit unit is also smeared will be stored in the first instance Except the second instance erased cell among the data duplication to those entity erased cells of unit.

18. memory storage apparatus according to claim 15, it is characterised in that can be answered according to this The status information of formula non-volatile memory module is write, the reading of the first instance erased cell is adjusted In the running for disturbing threshold value,

The memorizer control circuit unit is also erased meter to record the one of those each entity erased cells Number,

When the counting of erasing of the first instance erased cell is counted from the increase of one first count value for one second During value, the memorizer control circuit unit is also to by the reading interference of first instance erased cell door Threshold value is adjusted to one the 4th threshold value from one the 3rd threshold value,

Wherein second count value is more than first count value, and the 4th threshold value is more than the 3rd threshold value.

19. memory storage apparatus according to claim 18, it is characterised in that according to this first The reading interference threshold value of entity erased cell, in the running for performing prevention reading interference operation,

The memorizer control circuit unit is also used to the first instance program from the first instance erased cell Change unit and read data,

The memorizer control circuit unit is also to judge from being somebody's turn to do that the first instance programmed cell is read Whether the wrong bit number for reading data is more than the reading interference threshold of the first instance erased cell Value,

If the wrong bit number of the reading data read from the first instance programmed cell is more than During the reading interference threshold value of the first instance erased cell, the memorizer control circuit unit is also used to One second will be stored among the data duplication to those entity erased cells of the first instance erased cell Entity erased cell.

20. memory storage apparatus according to claim 15, it is characterised in that can be answered according to this The status information of formula non-volatile memory module is write, the reading of the first instance erased cell is adjusted In the running for disturbing threshold value,

The memorizer control circuit unit is also to check the one of the rewritable non-volatile memory module Temperature,

The memorizer control circuit unit is also used to being somebody's turn to do according to the rewritable non-volatile memory module Temperature adjusts the reading interference threshold value of the first instance erased cell.

21. memory storage apparatus according to claim 20, it is characterised in that can be answered according to this The temperature for writing formula non-volatile memory module adjusts the reading interference door of the first instance erased cell In the running of threshold value,

When the rewritable non-volatile memory module the temperature from the increase of one first temperature value be one the During two temperature values, the memorizer control circuit unit is also to by the reading of the first instance erased cell Interference threshold value is adjusted to one the 6th threshold value from one the 5th threshold value,

Wherein the second temperature value is more than first temperature value, and the 6th threshold value is more than the 5th threshold value.