CN107196644A - A kind of analogue buffer - Google Patents
A kind of analogue buffer Download PDFInfo
- Publication number
- CN107196644A CN107196644A CN201710314915.3A CN201710314915A CN107196644A CN 107196644 A CN107196644 A CN 107196644A CN 201710314915 A CN201710314915 A CN 201710314915A CN 107196644 A CN107196644 A CN 107196644A
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- CN
- China
- Prior art keywords
- transistor
- electrode connects
- source electrode
- resistance
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Amplifiers (AREA)
Abstract
The invention provides a kind of analogue buffer, belong to semiconductor integrated circuit technical field.The circuit includes：The first transistor, second transistor, third transistor, the 4th transistor, first resistor and second resistance；The grid connection input signal of the first transistor, drain electrode connects power supply, and source electrode connects one end of first resistor and the grid of second transistor；The other end ground connection of first resistor；The grid connection input signal of third transistor, grounded drain, source electrode connects one end of second resistance and the grid of the 4th transistor, another termination power of second resistance；The grounded drain of second transistor, source electrode connects output signal；The drain electrode of 4th transistor connects power supply, and source electrode connects output signal.The analogue buffer of the present invention, has two paths to be controlled the relation of input and output voltage.Realize output voltage following completely to input voltage, simple in construction, fast response time.
Description
Technical field
The invention belongs to semiconductor integrated circuit technical field, and in particular to a kind of analogue buffer.
Background technology
Analogue buffer circuit is voltage follower, is to realize the electron-like member that output voltage follows input voltage to change
Part.That is the voltage amplification factor of voltage follower is close to 1.In circuit, simulated cache device typically make buffer stage or every
From level.Because the output impedance of voltage amplifier is typically higher, generally at several kilohms to tens ohm.If rear class is defeated
Enter impedance comparison small, then signal just has suitable partition losses in the output resistance of prime.At this moment be accomplished by voltage with
Enter row buffering with device, play a part of forming a connecting link.
Traditional analogue buffer circuit, is connected with operational amplifier with negative feedback mode, component unit gain amplifier,
For driving load, so that input signal is not affected by a load.But the analogue buffer being made up of amplifier, it is complicated,
Considerably increase the cost of system.
The content of the invention
To solve the existing technical problem that analogue buffer is complicated, cost is high, the invention provides a kind of letter of structure
Single analogue buffer.
The analogue buffer of the present invention includes：The first transistor Q1, second transistor Q2, third transistor Q3, the 4th crystalline substance
Body pipe Q4, first resistor R1 and second resistance R2；The first transistor Q1 grid connection input signal Uin, drain and connect power supply, source
Pole connects first resistor R1 one end and second transistor Q2 grid；First resistor R1 other end ground connection；Third transistor Q3
Grid connection input signal Uin, grounded drain, source electrode connects second resistance R2 one end and the 4th transistor Q4 grid, second
Resistance R2 another termination power；Second transistor Q2 grounded drain, source electrode connects output signal Uout；4th transistor Q4's
Drain electrode connects power supply, and source electrode connects output signal Uout。
The analogue buffer of the present invention, has two paths to be controlled the relation of input and output voltage.It passes through crystalline substance
Input voltage is reduced a threshold voltage V by integral tube Q1TH, then pass through one threshold voltage V of second transistor Q2 risesTH
Output.Meanwhile, it raises a threshold voltage V by third transistor Q3TH, then pass through the 4th transistor Q4 one threshold value of reduction
Voltage VTHOutput.
Using the lifting of threshold voltage, buffer of the invention realizes output voltage following completely to input voltage,
It is simple in construction, fast response time.
Brief description of the drawings
Fig. 1 is the analogue buffer electrical block diagram that first embodiment of the invention is provided.
Embodiment
To make the object, technical solutions and advantages of the present invention of greater clarity, with reference to embodiment and join
According to accompanying drawing, the present invention is described in more detail.It should be understood that these descriptions are merely illustrative, and it is not intended to limit this hair
Bright scope.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring this
The concept of invention.
Traditional analogue buffer circuit, uses operational amplifier to be connected with negative feedback mode.Due to operational amplifier
The analogue buffer of composition is complicated, so as to cause higher cost.
The present invention uses another Research idea, constitutes analogue buffer using transistor and resistance, reaches and reduce
System cost.
As shown in figure 1, the analogue buffer provided for the present invention, including：The first transistor Q1, second transistor Q2,
Three transistor Q3, the 4th transistor Q4, first resistor R1 and second resistance R2；Input signal Uin, drain electrode connects power supply, and source electrode connects the
One resistance R1 one end and second transistor Q2 grid；First resistor R1 other end ground connection；Third transistor Q3 grid
Connect input signal Uin, grounded drain, source electrode connects second resistance R2 one end and the 4th transistor Q4 grid, second resistance R2
Another termination power；Second transistor Q2 grounded drain, source electrode connects output signal Uout；4th transistor Q4 drain electrode connects
Power supply, source electrode connects output signal Uout。
The analogue buffer of the present invention, has two paths to be controlled the relation of input and output voltage.It passes through crystalline substance
Input voltage is reduced a threshold voltage V by integral tube Q1TH, then pass through one threshold voltage V of second transistor Q2 risesTH
Output.Meanwhile, it raises a threshold voltage V by third transistor Q3TH, then pass through the 4th transistor Q4 one threshold value of reduction
Voltage VTHOutput.
Using the lifting of threshold voltage, buffer of the invention realizes output voltage following completely to input voltage,
It is simple in construction, fast response time.
It should be appreciated that the above-mentioned embodiment of the present invention is used only for exemplary illustration or explains the present invention's
Principle, without being construed as limiting the invention.Therefore, that is done without departing from the spirit and scope of the present invention is any
Modification, equivalent substitution, improvement etc., should be included in the scope of the protection.In addition, appended claims purport of the present invention
Covering the whole changes fallen into scope and border or this scope and the equivalents on border and repairing
Change example.
Claims (1)
1. a kind of analogue buffer, it is characterised in that including：The first transistor Q1, second transistor Q2, third transistor Q3,
4th transistor Q4, first resistor R1 and second resistance R2；
The first transistor Q1 grid connection input signal Uin, drain and connect power supply, source electrode connects first resistor R1 one end and second
Transistor Q2 grid；First resistor R1 other end ground connection；Third transistor Q3 grid connection input signal Uin, drain electrode connects
Ground, source electrode connects second resistance R2 one end and the 4th transistor Q4 grid, second resistance R2 another termination power；Second is brilliant
Body pipe Q2 grounded drain, source electrode connects output signal Uout；4th transistor Q4 drain electrode connects power supply, and source electrode connects output signal
Uout。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710314915.3A CN107196644A (en) | 2017-05-07 | 2017-05-07 | A kind of analogue buffer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710314915.3A CN107196644A (en) | 2017-05-07 | 2017-05-07 | A kind of analogue buffer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107196644A true CN107196644A (en) | 2017-09-22 |
Family
ID=59873127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710314915.3A Withdrawn CN107196644A (en) | 2017-05-07 | 2017-05-07 | A kind of analogue buffer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107196644A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6278326B1 (en) * | 1998-12-18 | 2001-08-21 | Texas Instruments Tucson Corporation | Current mirror circuit |
| CN1524340A (en) * | 2001-05-25 | 2004-08-25 | �����ɷ� | High bandwidth low voltage gain cell and voltage follower with enhanced mutual conductance |
| CN204244532U (en) * | 2014-12-05 | 2015-04-01 | 何志财 | A kind of LDO circuit for LED driver |
-
2017
- 2017-05-07 CN CN201710314915.3A patent/CN107196644A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6278326B1 (en) * | 1998-12-18 | 2001-08-21 | Texas Instruments Tucson Corporation | Current mirror circuit |
| CN1524340A (en) * | 2001-05-25 | 2004-08-25 | �����ɷ� | High bandwidth low voltage gain cell and voltage follower with enhanced mutual conductance |
| CN204244532U (en) * | 2014-12-05 | 2015-04-01 | 何志财 | A kind of LDO circuit for LED driver |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20170922 |