CN107180859A - Semiconductor structure element, especially power transistor - Google Patents

Abstract

A semiconductor component (1), in particular a power transistor, is described, having a substrate; an active semiconductor region having at least one source region (8) and at least one drain region (10); a cover substrate The source pad (2) of the first part of the bottom and the drain pad (4) of the second part of the covering substrate, wherein, between the source pad (2) or the drain pad (4) and at least one source region (8 ) or at least one drain region (10) is arranged with a substantially horizontally extending, structured metallization plane (30), wherein the source pad (2) and the drain pad (4) extend substantially vertically The metallizations (51, 52) are connected to the metallization plane (30), wherein the metallization plane (30) is connected to the source region (8) and to the drain by means of substantially vertically extending metallizations (53, 54) Area (10) is connected. The metallization plane (30) can cover at least 50%, at least 70% or at least 90% of the area of the active semiconductor region in order to achieve a low overall resistance.

Description

Semiconductor structural components, especially power transistors

technical field

The invention relates to a semiconductor structural element, preferably a power transistor, especially a gallium nitride power transistor.

Background technique

An important parameter for judging the performance of semiconductor structural elements is the total resistance in the on-state. For transistors or MOSFETs (Metal-Oxid-Halbleiter-Feldeffekttransistoren, metal-oxide-semiconductor field-effect transistor), the resistor is conventionally referred to as R _DSon . A portion of the resistor is constructed through the metallization of the source and drain. It is desirable here to achieve the lowest possible resistance.

It is known from the prior art to construct semiconductor components, in particular power transistors, in multiple layers. It is customary here to form an active semiconductor region in the substrate and to arrange vertically thereon horizontally extending pads for the source and drain. A plurality of source and drain regions, which are in the form of thin strips, are often present in a semiconductor component. Pads for source and drain regularly cover multiple source and drain regions. In order to enable a current to flow, for example from the drain region to the drain pad, a vertically extending metallization is introduced as a connection between the active semiconductor region and the pad. Via such a vertical connection, current can thus flow out of the drain region or into the source region and into the drain pad or out of the source pad. In this case, the pad is in particular a planar, substantially resistive contact (ohmic contact), via which the semiconductor component can be wired to the outside.

Since the source pad and the drain pad cannot respectively cover the entire active semiconductor region owing to the structure, it is necessary that a part of the current is conducted laterally through the semiconductor structural element in order to reach the corresponding pad. Lateral current transfer continues until a location covered by the corresponding source or drain pad is reached. There, current flows through the vertical connection between the active semiconductor region and the corresponding bonding pad. In this case, the lateral current transfer can take place within the active semiconductor region or in ohmic contacts where the source and drain regions conventionally coincide with the respective source or drain region.

The problem with this configuration is that for the lateral current transport a relatively high resistance results, which is detrimental to the overall resistance of the semiconductor component.

Contents of the invention

According to the present invention, there is provided a semiconductor structural element, especially a power transistor, the semiconductor structural element has a substrate, an active semiconductor region, a source pad and a drain pad, the active semiconductor region has at least one source region and at least one drain region, the source pad covers a first part of the substrate and the drain pad covers a second part of the substrate, wherein substantially Horizontally extending, structured metallization plane, wherein the source pad is connected to at least one first part of the metallization plane by means of at least one first metallization extending substantially vertically and the drain pad is connected by means of at least one first metallization extending substantially vertically At least one second metallization is connected to at least one second part of the metallization plane, wherein at least one first part of the metallization plane is connected to at least one source region by means of a substantially vertically extending third metallization, wherein , at least one second part of the metallization plane is connected to at least one drain region by means of a substantially vertically extending fourth metallization. A “substantially vertical” connection is understood here in particular to be a connection which forms an angle of greater than 45°, preferably greater than 75°, with respect to the horizontal. Particularly preferably, the connection runs exactly vertically. The concept "substantially horizontal" should be understood similarly.

Advantages of the invention

The semiconductor component according to the invention has the advantage that a small and uniform overall resistance is achieved. At the same time, semiconductor structural elements with high electrical conductivity greater than 50A can be manufactured. In this case, a metallized plane is not to be understood as a geometric plane, but as a spatial body, which consists of an electrically conductive material, for example, metal. This is in particular a metal layer which is thin compared to the entire semiconductor component, which is structured two-dimensionally and can be characterized by specifying the positions or regions at which, from a direction perpendicular to the plane Observe the presence of material. In particular, the metallized plane has an approximately uniform thickness, ie is substantially two-dimensional.

The metallization planes are insulated by two dielectric interlayers, so that an electrical connection between the individual planes exists only at the vertical metallizations. A particular advantage of the invention is that there are no regions of the source and drain regions in which the current has no possibility of detouring to the metal layer above the region but has to flow over a long distance . Thus, an increase in resistance due to this effect is effectively avoided.

In a preferred embodiment, the metal plane has a structure such that at least 50% of the area of the active semiconductor region, preferably 70% of the area of the active semiconductor region and particularly preferably 90% of the area of the active semiconductor region is made of metal flat cover. The larger the fraction of the area covered by the metallization plane, the larger the average cross-section for lateral current transport. This improves the mentioned resistance reduction.

Preferably, at least one source region and at least one drain region may be implemented as strips parallel to each other. This results in a simple structured layout, which can be added to an already existing process without major changes.

In this case, the metallization level can have strips which have at least one, at least three times or at least five times the width of the strips of the source and drain regions. This measure also ensures that a sufficiently large cross section is available for lateral current transmission. The orientation of the strips of the metallization plane can form an angle of 30° to 150°, in particular 80° to 100° and in special cases 90° with respect to the orientation of the source and drain pads. The current can then be distributed particularly efficiently in the semiconductor component.

In an embodiment of the invention, the metallization plane has trapezoidal strips. In this case, the narrow end of the trapezoid can be located at the point at which the connection between the trapezoid, which is part of the metallization plane, and the contact pad can be achieved by means of the first or second vertical connection. This embodiment is advantageous in that a reduced overall electrical resistance results due to the larger metal volume of the buried region of the metallization plane.

In an alternative embodiment it is advantageously provided that the metallization plane has a grid-like or mesh-like structure. The period may be at least approximately twice the distance between source and drain regions and for example be in the range between 10 μm and 1 mm. One of the pads may annularly surround the other pad. In other words, the source pad completely surrounds the drain pad, or vice versa. This embodiment is advantageous in that the source and drain pads are arranged concentrically. In the described geometry, source and drain potentials can be interchanged without loss of functionality.

In a refinement of the invention, the semiconductor component comprises a metallization in the intermediate layer, which is of the same type as the metallization plane and which likewise fulfills the current distribution function, but which is arranged on the metallization plane below or above. It is thus also possible to optimize the current distribution independently of one another for the source region/source pad and for the drain region/drain pad, since the paths of the source and drain currents can also intersect as seen in plan view.

It can likewise be possible for the metallization plane to have at least two regions at different potentials, which regions are structured such that they engage one another in a tooth-like or peak-like manner. As a result, the overall electrical resistance can be reduced by the compact design of the additional metallization level.

Advantageous refinements of the invention are specified in the dependent claims and described in the description.

Description of drawings

Embodiments of the invention are further explained with reference to the drawings and the following description. The accompanying drawings show:

1 is a schematic top view and cross-section of a semiconductor structural element according to the prior art;

Fig. 2 is a schematic top view of a first embodiment of the present invention;

Fig. 3 is a schematic top view of a second embodiment of the present invention;

Fig. 4 is a schematic top view of a third embodiment of the present invention;

Fig. 5 is a schematic top view of a fourth embodiment of the present invention;

Fig. 6 is a schematic top view of a fifth embodiment of the present invention;

FIG. 7 is an enlarged detail of the embodiment shown in FIG. 6 .

detailed description

FIG. 1 shows a semiconductor component, as is known from the prior art. A schematic plan view of the semiconductor component 100 is shown in the upper region of the figure. A source pad 102 and a drain pad 104 can be seen, which respectively extend horizontally from right to left and form the uppermost layer of the semiconductor structural element 100 . In this case, the semiconductor component 100 can be externally contacted and thus connected into an electrical circuit. In addition, a source region 106 and a drain region 108 running perpendicular to the direction of extension of the bonding pads 102 , 104 , respectively, can be seen. The source region 106 and the drain region 108 are part of the active semiconductor region and an ohmic contact is provided in each case on the surface of the source region 106 and the drain region 108 . Also marked is gate region 110 , which is not discussed further as a subject here.

The source region 106 is connected to the source pad 102 by a first vertical connection 112 . The drain region 108 is connected to the drain pad 104 through the second vertical connection 114 similarly to the source region 106 .

The example shown is a layout for producing gallium nitride power transistors (GaN transistors). FIG. 1 shows a plan view of the mask plane in the upper region. This represents the lateral dimensions of different metals and dielectrics. The source region 106 defines the region where current enters the semiconductor. Electric current is understood in this case to be a flow of electrons. The area includes an ohmic contact connected to the source pad 102 through the first vertical connection 112 . The drain region 108 defines the region where current—ie, again electron flow—leaves the semiconductor. Said area also includes an ohmic contact, which is connected to the drain pad 104 via the second vertical connection 114 .

The gate region 110 represents a metallic or semiconductor gate electrode, which is used to control the transistor. The gate electrode is no longer considered within the scope of the present invention. In this case, the first vertical connection 112 and the second vertical connection 114 are metal vias which are embedded in a layer of insulating material.

The transistor can be connected to an external device by means of a source pad 102 and a drain pad 104 and a gate pad not shown.

The source and drain regions 106, 108 are arranged alternately at the same pitch, eg 5 μm to 30 μm, in thin, eg 0.2 μm to 10 μm wide strips, eg 0.1 mm to 10 mm long and often occupying the entire chip length, so that the through Current through the semiconductor travels the same distance at every location on the wafer.

In the prior art example shown, the orientation of the contact pads, ie source pad 102 and drain pad 104 , at 90° relative to source region 106 and drain region 108 has been chosen. In order to provide a sufficient area for connecting external devices, the contact pads have a size of about (0.1mm-10mm)×(0.1mm-10mm).

The problem is that the current to be entered or to be extracted sometimes has to flow through a long path between the active semiconductor region and the corresponding pad 102 , 104 . For example, the electrons flowing through the channel between the source region 106 and the drain region 108 in the central region of FIG. 104 leaves the structural element. Resistance to these currents can significantly increase the overall resistance of component 100 . In addition, this effect also leads to an inhomogeneity of the electrical resistance of the component 100 .

A cross section of the semiconductor component 100 can be seen in the lower region of FIG. 1 . Again the source region 106 , the drain region 108 , the gate region 110 and the first vertical connection 112 can be seen. The connecting portion connects the drain region 108 with the drain pad 104 .

FIG. 2 shows a schematic plan view of a first embodiment of the invention. The statements that apply to the elements of the semiconductor structure described in FIG. 1 can likewise apply to the elements of the embodiment described in FIG. 2 , unless otherwise stated. In particular the mentioned dimensions of the pads, of the source and drain regions etc. and the structure of the vertical connections can be used.

Similar to FIG. 1 , source regions 8 and drain regions 10 can be seen, which are embodied as parallel strips and are arranged in a common plane. The gate region 12 adjacent to the source region 8 can likewise be seen. The source pad 2 is marked in the left part of the drawing, and the drain pad 4 is visible in the right part of the drawing. The two pads 2 , 4 are arranged rotated by 90° compared to the corresponding pads in FIG. 1 and run from top to bottom instead of right to left in the drawing. The pads 2 , 4 therefore run parallel to the source region 8 and to the drain region 10 . Furthermore, the bonding pads 2 , 4 are enlarged in area and cover a large part of the area of the semiconductor component 1 . Basically, the dimensions of the pads 2 , 4 correspond to those known from the prior art.

Metallization plane 30 is provided running at right angles to source region 8 and gate region 10 . The metallization plane is formed from a plurality of parallel strips 32 , 34 in the illustrated case, which cover the largest part of the substrate surface. Each strip 32 , 34 is electrically non-conductively connected to each other strip 32 , 34 within the metallization plane 30 . Each strip 32 , 34 is assigned either to the source region 8 or to the drain region 10 and is electrically conductively connected thereto. Thus, the strip 32 is connected to the source region 8 by means of the third vertical connection 53 and the strip 34 is connected to the drain region 10 by means of the fourth vertical connection 54 . Metallization plane 30 is thus at least partially connected both to source region 8 and to drain region 10 and also to source pad 2 and drain pad 4 . Respectively separate sections, in the case shown namely one each of the strips 32, 34, are connected both to the source region 8 and to the source pad 2, whereas the other sections are connected to both the drain region 10 and the source pad 2. Connect to drain pad 4. Thus, strip 32 may be referred to as a source segment or source strip of metallization plane 30 , and strip 34 may similarly be referred to as a drain segment or drain strip of metallization plane 30 .

The length of the source bar 32 and the drain bar 34 extends over the width (0.1mm-10mm) of the chip. The width of the source and drain bars can vary along the chip length between about 5 μm to 1 mm. The distance between the source and drain bars may be, for example, approximately 5 μm to 30 μm. However, smaller pitches in the range of 1 μm are also possible. Two adjacent strips 32 , 34 are made to have different potentials (source and drain) by arranging the vertical connections 51 , 52 , 53 and 54 . Here, the expressions "length" and "width" of the chip are arbitrarily selected and can be interchanged with each other. "Length" and "width" may be referred to as "first side" and "second side".

In the region where the source strip 32 overlaps the source region 8 a third vertical connection 53 is arranged in order to enable current to flow between the source region 8 and the source region 32 . Similar to this, a fourth vertical connection 54 is arranged between the drain bar 34 and the drain region 10 .

In a similar manner, the electrical connection between the metallization plane 30 and the source pad 2 and the drain pad 4 is achieved. Here, too, the vertical connections 51 , 52 are placed using corresponding overlapping regions. Therefore, the first vertical connection part 51 is arranged in a region where the source pad 2 and the source bar 32 overlap each other. The second vertical connection portion 52 is arranged in the region where the drain pad 4 overlaps the drain bar 34 .

The vertical connections 51 , 52 , 53 and 54 can be simple metallizations surrounded by a thin insulating layer. As in the exemplary embodiment shown, the vertical connections can each have a square cross-section (alternatively they can also be circular) and can be distributed equidistantly over the respective surface. Depending on the geometry of the overlapping surfaces, a linear arrangement as in the case of the first and second vertical connections 51 , 52 or a two-dimensional arrangement as in the case of the third and fourth vertical connections 53 , 54 can be provided. Grille arrangement.

Some strips 32 of metallization level 30 are connected to source pads 2 by means of first vertical connections 51 . The other strip 34 of the metallization level is connected to the drain pad 4 by means of a second vertical connection 52 .

FIG. 3 shows a schematic top view of a second embodiment of the invention. The structure of the semiconductor component 1 substantially corresponds to the structure of the semiconductor component shown in FIG. 2 . Correspondingly, the individual elements are provided with the same reference numerals as in FIG. 2 . The main difference lies in the structuring of the metallization plane 30 . The source bars 32 and the drain bars 34 are not embodied as rectangles, as in FIG. 2 , but as trapezoids. In other words, the strips 32, 34 do not have a constant width, but are oriented such that on the side they are connected to the source pad 2 by means of a first vertical connection 51 or to the drain pad 2 by means of a second vertical connection 52 4 The side of the connection is narrowed.

In this case, the lengths of the mutually parallel sides of the trapezoid have a ratio of approximately 2 to 1. Other ratios in the range between 10:1 and 1:1 are likewise possible, ie for example 1:1, 5:1 or 10:1. That is, for example, the long side of the source bar 32 is the side arranged below the drain pad 4 . Said side is about twice as long as the side parallel to it, which delimits the bar opposite and is arranged below the source pad 2 . This configuration results in a particularly low electrical resistance through the metallization level 30 in the region where the metallization level 30 is connected to the active semiconductor region, in other words to the source region 8 or the drain region 10 . This is advantageous since in conventional semiconductor components there is a relatively high electrical resistance in this region.

In the opposite areas where the strips 32, 34 are connected to the pads 2, 4, although there is a slightly higher resistance due to the reduced strip width relative to the rectangular strips as in FIG. The design of the trapezoidal bars 32, 34 is reduced relative to the rectangular bars.

FIG. 4 shows a schematic top view of a third exemplary embodiment of the invention. The illustrated exemplary embodiment corresponds substantially to the exemplary embodiment in FIG. 3 . The same reference numerals again designate elements of the same name. However, source pad 2 and drain pad 4 and source bar 32 and drain bar 34 are rotated by 90° relative to the embodiment shown in FIG. 3 . Therefore, the source bar 32 and the drain bar 34 run parallel to the source region 8 and the drain region 10 , whereas the pads 2 , 4 run at right angles to the source region 8 and the drain region 10 . The source region 8 and the drain region 10 are respectively equidistantly connected to the source bar 32 or the drain bar 34 over the entire length by means of third and fourth vertical connections 53 , 54 .

FIG. 5 shows a schematic top view of a fourth exemplary embodiment of the invention. The drain pad 4 can be seen, which is arranged centrally and completely surrounded by the source pad 2 . The metallization plane 30 occupies most of the area of the semiconductor component 1 in the exemplary embodiment shown and has only some gaps 6 below the drain pad 4, in which gaps between the drain pad 4 and the active semiconductor region In particular, no material belonging to the metallization plane 30 is present between the source regions 8 . Here, the source pad 2 is completely outside the active semiconductor region, ie does not cover the active semiconductor region. Alternatively, the active semiconductor region can also continue below the source pad 2 .

The drain region 10 is connected to the drain pad 4 by means of the second vertical connection portion 52 and the fourth vertical connection portion 54 . In the illustrated exemplary embodiment, the second vertical connection 52 and the fourth vertical connection 54 are arranged directly one above the other. The second vertical connection portion 52 has a larger cross section than the fourth vertical connection portion 54 . This is not important for functionality, but can offer production-technical advantages, since the third and fourth vertical connections 53 , 54 are thus designed of the same type as the first and second vertical connections 51 , 52 .

A first vertical connection 51 connecting the metallization plane 30 to the source pad 2 is arranged around the semiconductor component 1 . The first vertical connecting parts are arranged equidistantly in two parallel rows in the illustrated embodiment, but can also be arranged in other patterns.

FIG. 6 shows a schematic plan view of a fifth exemplary embodiment of the invention. The drain pad 4 is again arranged centrally and surrounded by the source pad 2 . Thus, in contrast to the embodiment shown in FIG. 5 , the source pad 2 again covers a part of the active semiconductor region. The metallization plane is divided into two parts, a source part 36 and a drain part 38 . The source part 36 roughly has a "double T structure": in the upper and lower part of the figure, the source part extends to the edge of the semiconductor structure element 1, at the right edge and at the left edge, the source part is retracted by the edge of the semiconductor structure element 1 approximately a quarter of the width, so that the source portion 36 covers approximately half the width of the semiconductor component 1 . In the right and left regions in the drawing, to which the source portion 36 does not extend, the drain portion 38 is arranged.

In the boundary region between the source portion 36 and the drain portion 38, the source and drain portions "engage" with each other. In other words, both the source part 36 and the drain part 36 have a peak-like structure, wherein the peaks of one part of the metallization plane are shaped correspondingly to the peaks of the other part of the metallization plane and engage with the latter. Here, however, in any case a small horizontal distance is observed so that there is no electrical contact between the source part 36 and the drain part 38 . Instead of a peak-shaped design, for example a saw-tooth-shaped design is also conceivable. Obviously, as in all illustrated embodiments, all metallizations in contact with source pad 2 are electrically insulated from drain pad 4 .

The two drain regions 10.1 and 10.2 in the middle of the drawing are connected to the drain pad 4 by means of the second vertical connection portion 52 (see FIG. 7 ) and the fourth vertical connection portion 54 (see FIG. 7 ). However, the other drain region 10 is also connected via a fourth vertical connection 54 (see FIG. 7 ) to the metallization level here in the form of the drain section 38 , as in the other exemplary embodiments.

FIG. 7 shows an enlarged detail of the semiconductor component 1 according to FIG. 6 . The meshing of the source part 36 and the drain part 38 of the metallization plane and the delimitation of the source pad 2 and the drain pad 4 can be seen particularly well here.

All described structures can be repeated any number of times over the entire semiconductor structural element and are thus considered as a unified unit. It is likewise possible to interchange the geometric positions of the element with source functionality and the element with drain functionality, respectively, without deviating from the inventive concept. Thus, only the current is reversed. It is also possible that in a unit cell there are more individual elements than shown, for example more parallel source and drain regions. For the sake of clarity, only a relatively small number of structures are shown in each case in the figures.

Claims (10)

1. a kind of semiconductor structure element (1), especially a kind of power transistor, the semiconductor structure element has substrate, active Semiconductor region, source pad (2) and solder skip disk (4), the active semi-conductor area have at least one source region (8) and at least one drain region (10), the source pad (2) covers the Part I and the solder skip disk (4) of the substrate and covers the Part II of the substrate, and it is special Levy and be,

I. in the source pad (2) or the solder skip disk (4) and at least one described source region (8) or at least one described drain region (10) substantial horizontal extension, structuring metallized plane (30) is disposed between, wherein

Ii. the source pad (2) by substantially vertical extension at least one first metallization (51) and the metallization Plane (30) at least one Part I connection, also, the solder skip disk (4) by substantially vertical extension at least one Second metallization (52) is connected with least one Part II of the metallized plane (30), wherein

Iii. at least one described Part I of the metallized plane (30) by substantially vertical extension the 3rd metal Change portion (53) is connected with least one described source region (8), wherein, described at least one second of the metallized plane (30) Divide and be connected by the 4th metallization (54) of substantially vertical extension with least one described drain region (10).

2. semiconductor structure element (1) according to claim 1, wherein, the metallized plane (30) has following knot Structure：So that at least the 50% of the area in the active semi-conductor area, at least the 70% of the area in preferably described active semi-conductor area And at least the 90% of the area in the particularly preferred active semi-conductor area is covered by the metallized plane (30).

3. semiconductor structure element (1) according to claim 1 or 2, wherein, at least one described source region (8) and described At least one drain region (10) is embodied as the bar of orientation parallel to each other, and the bar has the bar of the source region and drain region (8,10) extremely Few one times of width.

4. the semiconductor structure element (1) according to any one of the claims, wherein, the metallized plane (30) Bar (32,34) with trapezoidal configuration.

5. the semiconductor structure element (1) according to claim 3 or 4, wherein, the metallized plane (30) it is described The orientation of bar (32,34) forms 30 ° to 150 °, especially 90 ° of angle relative to the orientation of the source pad and solder skip disk (2,4) Degree.

6. the semiconductor structure element (1) according to any one of the claims, wherein, the metallized plane (30) With lattice-shaped or netted structure.

7. the semiconductor structure element (1) according to any one of the claims, wherein, or the source pad (2) Circlewise or box-shaped surround the solder skip disk (4), or the solder skip disk (4) circlewise or box-shaped surround the source pad (2)。

8. the semiconductor structure element (1) according to any one of the claims, wherein, the semiconductor structure element (1) there is another metallization in the intermediate layer, another metallization is configured to identical with the metallized plane (30) Type, wherein, another metallization meets CURRENT DISTRIBUTION function and is arranged in the lower section of the metallized plane (30) Or top.

9. the semiconductor structure element (1) according to any one of the claims, wherein, the metallized plane (30) With at least two regions (36,38) in common plane on different potentials, the such structure at least two regions Change so that at least two region dentation or peak be engaged with each other pointedly.

10. a kind of control device for vehicle, it includes at least one half according to any one of the claims Conductor structural element (1).