CN107180838B - Array substrate and manufacturing method thereof - Google Patents

Abstract

An array substrate, comprising: a substrate; a first metal layer located on the substrate; a gate insulating layer located on the first metal layer; an active layer located on the gate insulating layer; a second metal layer, located on the active layer and connected to the active layer; an insulating protective layer, located on the second metal layer, and a first via hole and a second via hole are opened on the insulating protective layer, so The insulating protective layer forms a stepped structure between the first via hole and the second via hole; the transparent electrode layer is located on the insulating protective layer and covers the stepped structure. A stepped structure is formed between the first via hole and the second via hole on the insulating protection layer, realizing the gradation of the transparent electrode layer from the opening of the first via hole to the opening of the second via hole Climbing, avoiding the climbing fracture caused by the excessive height difference caused by one-time climbing.

Description

A kind of array substrate and its manufacturing method

technical field

The invention relates to an array substrate and a manufacturing method thereof for improving transparent electrode climbing and disconnection in the field of liquid crystal display.

Background technique

With the development of display technology, consumers have higher and higher requirements for display screen quality, such as color saturation, resolution, response speed, and overall aesthetics of the appearance. In order to meet market demand, panel manufacturers are also actively developing new materials. , new processes and new technologies. Among them, the metal material used in thin-film transistor array panels has also been upgraded from aluminum to copper. The advantage of copper is its low impedance, which is suitable for high-end display panels with narrow borders, high PPI (pixels per inch) and high refresh rates.

However, because the chemical properties of copper itself are different from that of aluminum, problems such as excessive taper and chamfering are prone to occur during copper etching, which makes the transparent conductive film (ITO) prone to breakage when climbing. , especially at the vias where the jumper is connected. Traditional via design usually has two structures, as shown in Figures 1 to 4, including a first metal layer 1, a gate insulating layer 7, an active layer 5, and a second metal layer 2 sequentially arranged on a substrate 6. , an insulating protective layer 8 and a transparent electrode layer 9 , the first metal layer 1 partially covers the substrate 6 ; the active layer 5 partially covers the gate insulating layer 7 , and the second metal layer 2 covers the active layer 5 . A first via hole 3 and a second via hole 4 are respectively opened on the insulating protection layer 7 at the central positions of the first metal layer 1 and the second metal layer 2, and the gate insulating layer 7, the active layer 5 and the The shape formed by the second metal layer 2 basically forms the shape of the insulating protection layer 8 .

In Figure 1 and Figure 2, the first metal layer 1 and the second metal layer 2 have no overlap in the vertical direction; in Figure 3 and Figure 4, the first metal layer 1 and the second metal layer 2 partially overlap in the vertical direction . Due to the existence of the deep hole 3 and the shallow hole 4, the chamfering of the second metal layer 2 after etching makes the transparent electrode layer 9 on the insulating protective layer 8 located between the opening of the deep hole 3 and the opening of the shallow hole 4. Fracture, so that the direct connection of the two metal layers is abnormal.

Especially in the via hole design shown in FIG. 3 , the first metal layer 1 and the second metal layer 2 partially overlap in the vertical direction, so there is a large gap between the surface of the gate insulating layer 7 and the surface of the second metal layer 2 . On this basis, the surface of the insulating protective layer 8 will also form a larger height difference (that is, the position of the deep hole hole and the shallow hole hole), thereby causing the gap between the deep hole hole and the shallow hole hole. If the height difference between them is too large, the transparent electrode layer is likely to break during the climbing process from the deep hole opening to the shallow hole opening, and the direct connection between the two metal layers will be abnormal.

Contents of the invention

In order to improve the defect that the transparent electrode layer is prone to fracture during the climbing process, a substrate and a manufacturing method thereof for improving the disconnection caused by the climbing of the transparent electrode layer are invented.

An array substrate, comprising:

Substrate;

a first metal layer located on the substrate;

a gate insulating layer located on the first metal layer;

an active layer located on the gate insulating layer;

a second metal layer located on the active layer and connected to the active layer;

an insulating protective layer, located on the second metal layer, a first via hole and a second via hole are opened on the insulating protective layer, and the first via hole penetrates the insulating protective layer and the gate insulating layer to expose the first metal layer, the second via hole penetrates the insulating protection layer to expose the second metal layer, and the insulating protection layer is between the first via hole and the second A stepped structure is formed between the vias;

a transparent electrode layer, located on the insulating protection layer and covering the stepped structure, the transparent electrode layer is respectively connected to the first metal layer and the second via hole through the first via hole and the second via hole The two metal layers are connected.

The array substrate, wherein the second metal layer partially covers the active layer, and the part of the active layer not covered by the second metal layer is an uncovered area, and the uncovered area is located in the direction toward the first metal layer , the uncovered region occupies one-third of the total area of the source layer.

In the array substrate, the first via hole is a deep hole, and the second via hole is a shallow hole.

The array substrate, wherein, when the first metal layer and the second metal layer have no overlapping portion in the vertical direction, the height of the opening of the deep hole is equal to the height of the opening of the shallow hole, and the height of the step is equal to the height of the shallow hole. The bottom of the hole is on the same plane. .

The array substrate, wherein, when the first metal layer and the second metal layer partially overlap in the vertical direction, when the height of the deep hole is smaller than the height of the shallow hole, the step is located between the deep hole and the shallow hole. One-half of the vertical distance from the orifice.

A method for manufacturing an array substrate, comprising the following steps:

Step 1. Coating a layer of metal layer on the substrate, coating photoresist on the metal layer, exposing the part of the metal layer coated with photoresist, and removing the photoresist on the metal layer at the exposed position , leaving the metal layer and a part of the unremoved photoresist on the metal layer;

Step 2, etching the metal layer formed in step 1 and the unremoved photoresist on the metal layer, the part of the metal layer not covered by the photoresist is etched away, leaving the metal layer covering the part of the photoresist;

Step 3, peeling off the metal layer formed in step 2, removing the photoresist remaining on the metal layer, and forming the first metal layer;

Step 4, coating a gate insulating layer on the substrate and the first metal layer formed on the substrate;

Step 5, forming an active layer covering the gate insulating layer on the gate insulating layer;

Step 6, covering the active layer with a metal layer;

Step 7. Expose the structure formed in step 6 to form an active layer partially covering the gate insulating layer and a second metal layer partially covering the active layer. The active layer not covering the second metal layer is Uncovered area;

Step 8: Cover the insulating protective layer on the second metal layer, open a first via hole and a second via hole on the insulating protective layer, and the first via hole penetrates through the insulating protective layer and the gate insulating layer to expose The first metal layer is exposed, the second via hole penetrates the insulating protection layer to expose the second metal layer, and the insulating protection layer forms a ladder-like structure based on the shape of the uncovered area.

In the manufacturing method of the array substrate, in Step 7: before exposure, the position where the second metal layer needs to be formed is covered with a Cr film, and the position where the uncovered area needs to be formed is covered with a semi-permeable film.

In the manufacturing method of the array substrate, the uncovered area occupies one-third of the area of the source layer.

In the manufacturing method of the array substrate, when the second metal layer has no overlapping area with the first metal layer in the vertical direction, the opening heights of the first via hole and the second via hole are the same.

In the manufacturing method of the array substrate, when the second metal layer partially overlaps the first metal layer in the vertical direction, the height of the first via hole is smaller than the height of the second via hole.

The present invention has the following advantages: a stepped structure is formed between the first via hole and the second via hole on the insulating protection layer, and the transparent electrode layer is formed from the opening of the first via hole to the second via hole. The graded climbing of the orifice avoids the climbing fracture caused by the excessive height difference caused by one-time climbing.

The uncovered area is formed on the active layer, so that the insulating protection layer forms a step on the basis of the difference in height between the surface of the uncovered area and the surface of the second metal layer, so that the cost of the formed step is low and the processing is simple.

Description of drawings

Hereinafter, the present invention will be described in more detail based on the embodiments with reference to the accompanying drawings. in:

Figure 1 is a top view of a conventional via design structure.

FIG. 2 is a cross-sectional view of a conventional via design structure.

FIG. 3 is a top view of another structure of a conventional via hole design.

FIG. 4 is a cross-sectional view of another structure of a conventional via design.

5 is a top view of the array substrate structure of the first embodiment of the present invention;

6 is a cross-sectional view of the array substrate structure of the first embodiment of the present invention;

7 is a top view of the array substrate structure of the second embodiment of the present invention;

8 is a cross-sectional view of an array substrate structure according to a second embodiment of the present invention;

9 is a schematic diagram of a manufacturing method of an array substrate according to a first embodiment of the present invention;

10 is a schematic diagram of a manufacturing method of an array substrate according to a second embodiment of the present invention;

In the figures, the same parts are given the same reference numerals. The drawings are not to scale.

Detailed ways

The present invention will be further described below in conjunction with accompanying drawing.

As shown in FIG. 6 and FIG. 8, an array substrate includes: a substrate 6; a first metal layer 1 located on the substrate 6; a gate insulating layer 7 located on the first metal layer 1; an active layer 5, located on the gate insulating layer 7; the second metal layer 2, located on the active layer 5 and connected to the active layer 5; an insulating protection layer 8, located on the second metal layer 2 On the insulating protective layer 8, a first via hole 3 and a second via hole 4 are opened, and the first via hole 3 penetrates the insulating protective layer 8 and the gate insulating layer 7 to expose the The first metal layer 1, the second via hole 4 penetrates the insulating protection layer 8 to expose the second metal layer 2, and the insulating protection layer 8 is between the first via hole 3 and the first via hole 3. A stepped structure is formed between the two via holes 4; a transparent electrode layer 9 is located on the insulating protection layer 8 and covers the stepped structure, and the transparent electrode layer 9 passes through the first via hole 3 and the second via hole 3 Two via holes 4 communicate with the first metal layer 1 and the second metal layer 2 respectively. The second metal layer 2 partially covers the active layer 5, and the part of the active layer 5 not covered by the second metal layer 2 is an uncovered area 13, and the uncovered area 13 is located in a direction toward the first metal layer 1, The uncovered region 13 occupies one-third of the total area of the source layer 5 . The first via hole 3 is a deep hole, and the second via hole 4 is a shallow hole.

As shown in FIG. 5 and FIG. 6, wherein, the first metal layer 1 and the second metal layer 2 have no overlapping portion in the vertical direction, and the surface of the gate insulating layer 7 and the surface of the second metal layer 2 form a height difference, The insulating protection layer 8 covering the gate insulating layer 7 and the second metal layer 2 also forms a height difference, that is, the surface of the insulating protection layer 8 at the position of the first metal layer 1 and the surface of the insulating protection layer 8 at the gate The surface at the position of the insulating layer 7 forms a relatively large height difference; the surface of the insulating protection layer 8 at the position of the second metal layer 2 and the surface of the insulating protection layer 8 at the position of the gate insulating layer 7 form a relatively large height difference. , the height of the deep hole orifice is equal to the height of the shallow hole orifice, and the insulating protective layer 8 forms a step 14 between the deep hole and the shallow hole position, and the height of the step 14 is on the same plane as the bottom of the shallow hole, realizing The gradual climbing of the transparent electrode layer 9 from the opening of the first via hole 3 to the insulating protection layer 8 located on the surface of the gate insulating layer 7 to the step 14 and then to the opening of the second via hole 2 avoids one-time climbing The climbing fracture caused by the excessive height difference caused by the time.

As shown in Figures 7 and 8, when the first metal layer 1 and the second metal layer 2 partially overlap in the vertical direction, the height of the deep holes is smaller than the height of the shallow holes, and the first metal layer 1 and the second metal layer The metal layer 2 partially overlaps in the vertical direction, so there is a large height difference between the surface of the gate insulating layer 7 and the surface of the second metal layer 2, and on this basis, the surface of the insulating protection layer 8 will also form a large height difference (that is, the position of the deep hole orifice and the shallow hole orifice), which causes the height difference between the deep hole orifice and the shallow hole orifice to be too large, causing the transparent electrode layer 9 to move from the deep hole to the shallow hole. Fractures are prone to occur during the climbing process of the hole, which makes the direct connection of the two metal layers abnormal, and a step 14 is formed between the deep hole and the shallow hole in the insulating protection layer 8, and the step 14 is located between the deep hole and the shallow hole. One-half of the vertical distance of the orifice realizes the graded climbing of the transparent electrode layer 9 from the opening of the first via hole 3 to the opening of the second via hole 4, avoiding the height difference caused by one-time climbing Climbing breaks caused by oversize.

As shown in Figures 9 and 10, a method for manufacturing an array substrate includes the following steps:

Step 1. Coating a layer of metal layer on the substrate, coating photoresist on the metal layer, exposing the part of the metal layer coated with photoresist, and removing the photoresist on the metal layer at the exposed position , leaving the metal layer and a part of the unremoved photoresist on the metal layer;

Step 2, etching the metal layer formed in step 1 and the unremoved photoresist on the metal layer, the part of the metal layer not covered by the photoresist is etched away, leaving the metal layer covering the part of the photoresist;

Step 3, peeling off the metal layer formed in step 2 to remove the photoresist remaining on the metal layer to form the first metal layer 1;

Step 4, coating the gate insulating layer 7 on the substrate 6 and the first metal layer 1 formed on the substrate 6;

Step 5, forming an active layer covering the gate insulating layer 7 on the gate insulating layer 7;

Step 6, covering the active layer with a metal layer;

Step 7: Exposing the structure formed in step 6 to form an active layer 5 partially covering the gate insulating layer 7, and a second metal layer 2 partially covering the active layer 5 without covering the second metal layer 2 The active layer is the uncovered area 13;

Step 8: Cover the second metal layer 2 with an insulating protective layer 8, and open a first via hole 3 and a second via hole 4 on the insulating protective layer 8, and the first via hole 3 runs through the insulating protective layer 8 and the insulating protective layer 8. The gate insulating layer 7 exposes the first metal layer 1, the second via hole 4 penetrates the insulating protection layer 8 to expose the second metal layer 2, and the insulating protection layer 8 is On the basis of the shape of the uncovered area 13, a stepped structure 14 is formed. The uncovered region 14 is formed on the active layer 5, so that the insulating protection layer 8 forms a step 14 on the basis of the height difference between the surface of the uncovered region 13 and the surface of the second metal layer 2, and the cost of the step 14 formed in this way is low. Processing is simple.

Wherein, in step seven: before exposure, the position where the second metal layer 2 needs to be formed is covered with the Cr film 12 , and the position where the uncovered region 13 needs to be formed is covered with the semi-permeable film 11 .

The uncovered region 13 occupies one-third of the area of the source layer.

As shown in FIG. 9 , when the second metal layer 2 has no overlapping area with the first metal layer 1 in the vertical direction, the opening heights of the first via hole 3 and the second via hole 4 are the same. As shown in FIG. 10 , when the second metal layer 2 partially overlaps the first metal layer 1 in the vertical direction, the height of the opening of the first via hole 3 is smaller than the height of the opening of the second via hole 4 .

While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for parts thereof without departing from the scope of the invention. In particular, as long as there is no structural conflict, the technical features mentioned in the various embodiments can be combined in any manner. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims (9)

1. An array substrate, comprising: a substrate; a first metal layer on the substrate; a gate insulating layer on the first metal layer; an active layer on the gate insulating layer; a second metal layer on and connected to the active layer; the insulating protection layer is positioned on the second metal layer, a first via hole and a second via hole are formed in the insulating protection layer, the first via hole penetrates through the insulating protection layer and the grid electrode insulating layer to expose the first metal layer, the second via hole penetrates through the insulating protection layer to expose the second metal layer, and a stepped structure is formed between the first via hole and the second via hole by the insulating protection layer; the transparent electrode layer is positioned on the insulating protection layer and covers the stepped structure, and the transparent electrode layer is respectively communicated with the first metal layer and the second metal layer through the first via hole and the second via hole; the second metal layer is partially covered with an active layer, the part of the active layer, which is not covered with the second metal layer, is an uncovered area, the uncovered area is positioned in the direction towards the first metal layer, and the uncovered area occupies one third of the total area of the active layer.

2. The array substrate of claim 1, wherein the first via is a deep hole and the second via is a shallow hole.

3. The array substrate of claim 2, wherein the first metal layer and the second metal layer have no overlapping portion in the vertical direction, the deep hole aperture has a height equal to that of the shallow hole aperture, and the step height is coplanar with the bottom of the shallow hole.

4. The array substrate of claim 2, wherein when the first metal layer and the second metal layer partially overlap in a vertical direction, the deep hole opening height is less than the shallow hole opening height, and the step is located at a half of a vertical distance between the deep hole opening and the shallow hole opening.

5. A manufacturing method of an array substrate is characterized by comprising the following steps: step one, coating a metal layer on a substrate, coating photoresist on the metal layer, carrying out exposure treatment on the part of the metal layer coated with the photoresist, removing the photoresist on the metal layer at the exposure position, and leaving the photoresist on the metal layer and the part of the metal layer which is not removed; etching the metal layer formed in the step one and the photoresist on the metal layer which is not removed, etching and removing the part of the metal layer which is not covered by the photoresist, and leaving the part of the metal layer which is covered by the photoresist; step three, carrying out stripping treatment on the metal layer formed in the step two, and removing the photoresist remained on the metal layer to form a first metal layer; step four, coating a grid insulation layer on the substrate and the first metal layer formed on the substrate; fifthly, forming an active layer covering the grid insulation layer on the grid insulation layer; sixthly, covering a metal layer on the active layer; step seven, carrying out exposure treatment on the structure formed in the step six, and forming an active layer partially covering the gate insulating layer and a second metal layer partially covering the active layer, wherein the active layer which is not covered by the second metal layer is an uncovered area; step eight, covering an insulating protection layer on the second metal layer, and forming a first via hole and a second via hole on the insulating protection layer, wherein the first via hole penetrates through the insulating protection layer and the gate insulating layer to expose the first metal layer, the second via hole penetrates through the insulating protection layer to expose the second metal layer, and the insulating protection layer forms a step-shaped structure on the basis of the shape of the uncovered area.

6. The method for manufacturing the array substrate according to claim 5, wherein in the seventh step: before exposure, the position where the second metal layer is to be formed is blocked by a Cr film, and the position where the second metal layer is to be formed is blocked by a semi-permeable film.

7. The method of claim 5, wherein the uncovered area occupies one third of the active layer area.

8. The method for manufacturing the array substrate according to claim 5, wherein the first via hole and the second via hole have the same height when the second metal layer has no overlapping area with the first metal layer in the vertical direction.

9. The method for manufacturing the array substrate according to claim 5, wherein when the second metal layer is partially overlapped with the first metal layer in the vertical direction, the height of the first via hole is smaller than that of the second via hole.