CN107180130B - Parasitic parameter extraction method - Google Patents
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Abstract
The invention relates to a parasitic parameter extraction method, which is characterized by comprising the following steps of: dividing the specified resistance model boundary into a plurality of boundary elements; taking the port and the model boundary element in the resistance model as ports, and calculating a boundary conductance matrix of the port and/or the model boundary element in the resistance model; converting the boundary conductance matrix into a Markov transfer matrix, and extracting parasitic resistance in the integrated circuit design under the same process by using a Markov transfer matrix library. The Markov transfer matrix library model established by the invention is a basic conductor or port, can cover all possible situations in a circuit, can completely control errors in the calculation process, ensures the precision and the reliability, and can achieve very high efficiency.
Description
The invention has the application number of 201510015007.5, the application date of 2015, 1 month and 13 days, the application type of the invention and the application name of the invention is divisional application of a parasitic resistance extraction method based on a Markov transfer matrix library.
Technical Field
The invention relates to the field of parasitic parameter extraction, in particular to a parasitic parameter extraction method.
Background
The extraction of parasitic parameters of interconnection lines is a very important link in the design of the current integrated circuit. An integrated circuit designer obtains parasitic parameters such as resistance, capacitance and the like on an interconnection line in an integrated circuit through parasitic parameter extraction tool software, and then obtains time delay and power consumption of the integrated circuit to judge whether the design meets requirements in the aspects of function, frequency and power consumption or not and whether the original design needs to be changed and optimized. In fact, in the current integrated circuit design, multiple designs or design optimizations are required, and parasitic parameter extraction and delay power consumption analysis can reach the initial standard to start tape-out, i.e. chip production.
The 22 nm and even more advanced chip process flow brings huge challenges to the extraction of parasitic parameters of interconnection lines, and makes it more difficult for integrated circuit designers to design faster and lower power consumption chips. The source of this challenge is EDA software for parasitic parameter extraction: various effects on a silicon wafer in a 22 nanometer process flow, higher clock frequency, larger circuit layout and a three-dimensional integrated circuit cause the parasitic parameter extraction software to have huge troubles in accuracy, reliability and running time. Integrated circuit designers have to deal with the above problems by increasing the redundancy of their designs to ensure the reliability of their designs, but this reduces the clock frequency of the chips being designed and increases the power consumption of the chips.
Regarding extracting parasitic resistance parameters, conventional parasitic resistance extraction methods are classified into two categories:
1. subdividing the network lines by using a numerical method, and directly solving a stable and constant current field on the network lines;
2. and generating a model and a resistor library under the model according to the process flow, dividing network cables in the circuit design, and extracting the specific circuit design by using the resistor library.
In the conventional method 1, a solution-stable constant current field is required for each designed network cable, and the calculation amount is huge, especially when the network cable is large. For today's real integrated circuit designs, extraction cannot be performed in practical time with this method.
In the conventional method 2, a model and a resistor library are generated and constructed under each process flow, and then resistors in the real design are extracted by using the resistor library. The ports in the resistor bank are either the ports in the real extraction or the entire interface of the divided part of the net wire. The potential of the port must be uniform, and the potential at the interface of the divided portions of the mesh wire is not necessarily uniform, which causes an error. The invention can divide the port into a plurality of boundary elements, allows the potentials of different boundary elements on the same port to be different, and reduces the error caused by the nonuniform interface potential.
The examiner proposes in the first examination opinion notice: the structured random walk capacitance extraction algorithm considering the suspended dummy published in "compound denier reports (nature science edition)" by Sunzu et al, No. 1 discloses a structured random walk capacitance extraction algorithm considering the suspended dummy, and specifically provides a parasitic capacitance extraction algorithm based on random walk, which divides a dummy region into a plurality of sub-regions by using a region decomposition technology, establishes a macro model for standard sub-regions with the same structure, calculates a Markov transfer matrix, and realizes 'walk' in the dummy region by using a transfer probability to extract parasitic capacitance. Although the parasitic capacitance and the parasitic resistance belong to parasitic parameters, the article does not disclose the specific content of how to generate the markov transfer matrix from the resistance model, and therefore the parasitic capacitance extraction method cannot solve the technical problem of extracting the parasitic resistance.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a parasitic resistance extraction method based on a Markov transfer matrix (Markov transfer matrix) library, so as to improve the accuracy and reliability under a new process and meet higher requirements of the current integrated circuit design.
A parasitic resistance extraction method based on a Markov transfer matrix library comprises the following steps:
constructing a resistance model by using the model template and the process parameter file;
generating a markov transfer matrix from the resistance model;
storing the Markov transfer matrix of each resistance model in the same process to a Markov transfer matrix library; and
the parasitic resistance in the integrated circuit design under the process is extracted by using a Markov transfer matrix library.
Among the sufficient requirements that the markov transition matrix satisfies are:
all elements are non-negative; and the sum of the elements in each row is 1; the diagonal element is 0.
Wherein the step of generating the Markov transfer matrix by the resistance model comprises:
dividing the specified resistance model boundary into a plurality of boundary elements;
taking the port and the model boundary element in the resistance model as ports, and calculating a boundary conductance matrix of the port and/or the model boundary element in the resistance model; and
the transition boundary conductance matrix is a markov transition matrix.
The model boundary element is a boundary element of a boundary adjacent to other models in the conductor.
The resistance model comprises a metal layer two-port model, a metal layer one-port model, a metal layer three-port model, a metal layer communication hole model, a metal layer one-port communication hole model and a through hole model.
Wherein the step of converting the boundary conductance matrix to a markov transfer matrix comprises: using formulas
The transition boundary conductance matrix is a markov transition matrix, where M is the markov transition matrix,
is a boundary conductance matrix, I is an identity matrix with the same dimension as the boundary conductance matrix,
is to the matrix
Taking the diagonal operation to carry out the diagonal operation,
the inverse of the boundary conductance matrix after the diagonal operation is taken.
The method for extracting parasitic resistance in the integrated circuit design under the process by utilizing the Markov transfer matrix library comprises the following steps:
reading in a Markov transfer matrix library of a corresponding process;
reading in and translating all or part of network cables in the integrated circuit layout and dividing each read-in internet cable into a plurality of sub-network cables;
reading in a Markov transfer matrix of a process corresponding to each sub-net line; and
calculating conductance between ports from Markov transfer matrices
Taking the inverse of the conductance between the ports as the parasitic resistance of the net wire.
Wherein the step of calculating the conductance between the ports from the markov transfer matrix to thereby obtain the reciprocal of the conductance between the ports as the parasitic resistance of the network cable comprises:
setting the potential of the first port to be 0V, the potential of the second port to be 1V, and the other ports to be natural surfaces;
obtaining the probability of jumping from the initial boundary element adjacent to the first port to the adjacent boundary element by the Markov transfer matrix corresponding to the body block connected with the first port;
randomly selecting a target boundary element to be jumped according to the probability of jumping to the adjacent boundary element;
starting jumping by taking the starting boundary element as an origin and continuously jumping by taking the target boundary element as a next origin according to the corresponding jumping probability until jumping to the first port or the second port is stopped;
repeating the jumping step with the starting boundary element as the origin for multiple times;
counting the number of times n1 with the first port as a terminal point, and counting the number of times n2 with the second port as a terminal point;
obtaining the conductance between the first port and the originating boundary element according to the boundary conductance matrix corresponding to the originating boundary element
Calculating the conductance between the first port and the second port, i.e. the current of the first port
Taking the reciprocal of the conductance between the first port and the second port as the resistance between the first port and the second port
The step of reading and translating all or part of the network cables in the integrated circuit layout and dividing each read-in internet cable into a plurality of sub-network cables comprises the following steps:
and converting the integrated circuit layout into a data format with the interior indexed according to the spatial region.
The step of reading and translating all or part of the network cables in the integrated circuit layout and dividing each read-in internet cable into a plurality of sub-network cables comprises the following steps:
and obtaining a circuit board diagram on the actual silicon chip by the integrated circuit design layout and the process parameter file under the corresponding process.
The steps of reading and translating the integrated circuit layout comprise: and converting the integrated circuit layout into a data format with the interior indexed according to the spatial region.
Technical effects of the invention
The method for extracting the parasitic resistance parameters by utilizing the Markov transfer matrix library and applying the random walk method is strictly based on the variant form of the Maxwell equation, can completely control the error in the calculation process, and ensures the precision and the reliability. In the invention, a Markov transfer matrix library is only established once in one process flow, and most of calculation processes are carried out during the establishment of the library, but not during the calculation and the extraction of parasitic parameters by using a random walk method, so that the high efficiency can be achieved. The Markov transfer matrix library of the invention is different from the parasitic parameter library in the model matching method, and the model of the invention is a basic conductor or port and can cover all possible situations in the circuit; the model matching method must consider the coupling relationship between a plurality of conductors, the combination of the models is complex, and all possible circuit layout situations cannot be covered by practically acceptable number of models.
Drawings
FIG. 1 is a flow diagram of a method of parasitic resistance extraction based on a Markov transfer matrix library;
FIG. 2 is a schematic diagram of a two-port model of a metal layer;
FIG. 3 is a schematic diagram of a metal layer-port model;
FIG. 4 is a schematic diagram of a metal layer three-port model;
FIG. 5 is a schematic view of a metal layer via model;
FIG. 6 is a schematic view of a metal layer port via model;
FIG. 7 is a schematic diagram of a via model;
FIG. 8 is a partial top view of an integrated circuit;
FIG. 9 is a top view of a feature block on a first metal layer;
FIG. 10 is a top view of a feature block on a second metal layer; and
fig. 11 is a top view of a shape block on a via layer.
List of reference numerals
1: the shape block 12: the shape block 23: shaped block 3
4: the shape block 45: the shape block 56: shaped block 6
7: the shape block 78: the shape block 89: shaped block 9
10: body block 1011: body block 1112: shaped block 12
13: body block 1314: body block 1415: shaped block 15
16: body block 1617: first port 18: second port
19: third port 20: first metal layer 21: originating boundary element
30: second metal layer 40: via layer
Detailed Description
The following detailed description is made with reference to the accompanying drawings.
FIG. 1 is a flow chart of a method for parasitic resistance extraction based on a Markov transfer matrix library. A method for extracting parasitic resistance based on markov transfer matrix library is shown in fig. 1, and includes the following steps:
constructing a resistance model by using the model template and the process parameter file;
generating a markov transfer matrix from the resistance model;
storing the Markov transfer matrix of each resistance model in the same process to a Markov transfer matrix library; and
the parasitic resistance in the integrated circuit design under the process is extracted by using a Markov transfer matrix library.
Specifically, the data of the process characteristic dimension of the integrated circuit model template and the process parameter file are read or input into a computer scanning program to be constructed into the resistance model. Calculating a boundary conductance matrix of the resistance models and converting the boundary conductance matrix into a Markov transfer matrix, wherein each resistance model corresponds to one Markov transfer matrix; storing the Markov transfer matrix of each resistance model in the same process to a Markov transfer matrix library; extracting parasitic resistance in the integrated circuit layout by using a Markov transfer matrix library according to a certain method step.
In the present invention, the process parameter file is generally provided by an integrated circuit manufacturer, and is a file describing the geometric and physical characteristics of conductors and media in a certain integrated circuit process. Each integrated circuit process corresponds to a process parameter file. The integrated circuit process refers to the fineness of the integrated circuit. The higher the precision, the more advanced the production process, such as 28 nm process, 22 nm process. The nanometer in the process refers to the distance between the circuits in the IC, and the higher the density of the IC circuit design, which means that the IC with the same area can have a circuit design with higher density and more complex functions.
Among the sufficient requirements that the markov transition matrix satisfies are:
all elements are non-negative and the sum of the elements in each row is 1 and the diagonal elements are 0.
In general, the markov transition matrix needs to satisfy the following conditions: all elements of the matrix are non-negative and the sum of the row elements equals 1, the elements being represented by probabilities and, under certain conditions, being shifted from each other. In the present invention, the Markov transition matrix must also satisfy the condition that the diagonal elements of the matrix are 0.
Wherein the step of generating the Markov transition matrix by the circuit model comprises:
dividing the specified model boundary into a plurality of boundary elements;
taking the port and the model boundary element in the model as ports, and calculating a boundary conductance matrix of the port and/or the model boundary element in the model; and
the transition boundary conductance matrix is a markov transition matrix.
One resistance model is a conductor whose surface is considered to be the boundary element or natural surface of the port. A model boundary element is a boundary element inside a conductor that is adjacent to the boundary of other models. At any time, there is no current on the natural surface that is perpendicular to the surface, i.e., no normal current. In numerical calculations, a natural surface without normal current is called a neman boundary element or a natural boundary element, which is a boundary element between a conductor and a medium. The invention divides the appointed model boundary into a plurality of boundary elements, allows the potentials of the boundary elements of the same port to be different, and reduces the error caused by the non-uniform interface potential.
The circuit model comprises a metal layer two-port model, a metal layer one-port model, a metal layer three-port model, a metal layer communication hole model, a metal layer one-port communication hole model and a through hole model. The resistance model is a cuboid, and the cross section of the resistance model is trapezoidal under many current processes, so the resistance model is not a strict cuboid. One port of the resistance model is divided into 4 port boundary elements, but the port is divided into more boundary elements according to the requirement of visual precision in implementation.
Fig. 2 shows a metal layer two-port model, which is considered as a boundary element of a port at both ends of a cuboid. Fig. 3 shows a metal layer-port model, which is considered as a boundary element of a port at one end of a rectangular parallelepiped. Fig. 4 shows a metal layer three-port model, which is viewed as a boundary element of a port at both ends of a rectangular parallelepiped, and another perpendicular to the surface of the substrate. Fig. 5 shows a metal layer via hole model, which is regarded as a boundary element of a port at both ends of a rectangular parallelepiped, and a surface parallel to the substrate, i.e., a surface of a metal layer connection via hole. Fig. 6 shows a metal layer-port via model, which is regarded as a boundary element of a port at one end of a rectangular parallelepiped, and a surface parallel to the substrate, i.e., a surface of a metal layer connection via. Fig. 7 shows a via model, which is viewed as a boundary element of a port parallel to the surface of the substrate at both upper and lower ends of a rectangular parallelepiped.
Each model has several resistance models in different metal layers or via layers and with different geometric parameters. The geometrical parameters include the length, width and height of the cuboid, and since the height of the cuboid is determined by the process, the heights of different cuboids are a common parameter. All the resistance models of different types, in different metal layers or through hole layers and with different geometric parameters under the same process flow form a set, namely the conductance parameters.
According to the method, the ports and the model boundary elements in the resistance model are used as the ports, the boundary conductance matrix of the ports and/or the model boundary elements in the resistance model is calculated, and the model boundary elements do not include Newman boundary elements.
Specifically, voltages or normal currents on the boundary elements and the natural boundary are set, voltages on the boundary elements i which are regarded as the ports are set to be 1V, voltages on other boundary elements are set to be 0V, and normal currents on the natural surface of the model are set to be 0; the conductance parameter in the model is determined by the process flow, and the constant current field in the space is solved by using numerical methods such as finite element, boundary element, finite difference and the like, so as to obtain the normal current on each boundary element, for example, the normal current I on the boundary element jjI.e. the conductance. Conductance is the inverse of the boundary element resistance.
In the present invention, the boundary conductance matrix is used
Meaning, specifically defined, that the dimension of the matrix is equal to the number of boundary elements considered as ports, and then the boundary conductance matrix
Element of ith row and jth column
Numerically equal to the conductance of the boundary element j. Thus, the boundary conductance matrix consists of the conductance of each boundary element.
Using formulas
The transition boundary conductance matrix is a markov transition matrix, where M is the markov transition matrix,
is a boundary conductance matrix, I is an identity matrix with the same dimension as the boundary conductance matrix,
is to the matrix
Taking the diagonal operation to carry out the diagonal operation,
the inverse of the boundary conductance matrix after the diagonal operation is taken. The resulting markov transfer matrix M fully satisfies the sufficient requirements of the markov transfer matrix defined by the present invention: all elements are non-negative and the sum of the elements in each row is 1 and the diagonal elements are 0.
And after the Markov transfer matrix corresponding to the resistance model is obtained, storing the Markov transfer matrix under the same process into a Markov transfer matrix library of the process.
Parasitic resistances are extracted using a markov transfer matrix library. The step of extracting parasitic resistance in the integrated circuit design under the process by utilizing the Markov transfer matrix library comprises the following steps:
reading in a Markov transfer matrix library of a corresponding process;
reading in and translating all or part of network cables in the integrated circuit layout and dividing each read-in internet cable into a plurality of sub-network cables;
reading in a Markov transfer matrix of a process corresponding to each sub-net line; and
calculating conductance between ports from Markov transfer matrices
Taking the inverse of the conductance between the ports as the parasitic resistance of the net wire.
Firstly, reading in a Markov transfer matrix library under a corresponding process. Then, the integrated circuit layout in a standard format, such as LEF/DEF format, GDSII format, etc., is read or input into a computer, and all or part of the network cables in the integrated circuit layout are translated and converted into a data structure format with internal indexes according to spatial regions so as to extract parasitic parameters more effectively.
The steps of reading in and translating all or part of network cables in the integrated circuit layout and dividing each read-in internet cable into a plurality of sub-network cables comprise:
and obtaining a circuit board diagram on the actual silicon chip by the integrated circuit design layout and the process parameter file under the corresponding process.
Under a relatively new integrated circuit process, due to physical effects during the production of numerous silicon chips, the final layout on the silicon chip may be different from the designer's layout, such as the width, thickness and shape of the conductive lines. Therefore, after the circuit board diagram of the designer is read in, the effect on the silicon wafer needs to be considered according to the process characteristics, and the circuit board diagram on the actual silicon wafer is obtained by the integrated circuit design layout and the process parameter file under the corresponding process. Reading and translating all or part of network cables in the circuit layout on the actual silicon chip into a data structure format with the interior indexed according to the space region. Dividing each read-in internet line into a plurality of sub-network lines, and extracting the Markov transfer matrix of the corresponding process for each sub-network line by a plurality of computer cores or a plurality of computers in parallel so as to reduce the total time for extracting the parasitic resistance. The sub-nets of all the integrated circuit layouts are connected directly or indirectly through their boundaries, so that their corresponding markov transition matrices can be linked together. The probability of a boundary element on any sub-net-line transitioning to the remaining boundary element or port can be calculated by the corresponding markov transition matrix. And counting the jumping times from the initial boundary element to the port pair, namely the first port and the second port in the probability to obtain the normal current of the first port, namely the conductance between the first port and the second port, wherein the reciprocal of the conductance is the resistance between the first port and the first port.
In particular, the parasitic resistance is extracted separately for each port pair of each net wire in the integrated circuit. The circuit designer may also specify that only one or a portion of the nets in the circuit are to be extracted, and that the port pairs of the nets need not be a combination of all the port pairs. The problem is therefore to simplify the multiple iterations of the resistance extraction algorithm between a pair of ports paired to one network line.
The mesh wire of the resistor to be extracted is divided into a plurality of shape blocks, each shape block is a cuboid-like body and is only arranged in one metal layer or through hole layer. In addition, the segmented feature blocks correspond to well-defined resistance models when generating a Markov transfer matrix library under the process. For example, a block having two opposing faces connecting other blocks or ports on the same layer corresponds to the two-port model of the metal layer shown in fig. 2, a block having one face connecting other blocks or ports on the same layer corresponds to the one-port model of the metal layer shown in fig. 3, a block having three faces connecting its blocks or ports on the same layer corresponds to the three-port model of the metal layer shown in fig. 4, a block having two faces connecting other blocks or ports on the same layer and connecting a through hole corresponds to the through hole model of the metal layer shown in fig. 5, a block having one face connecting its blocks or ports on the same layer and connecting a through hole corresponds to the one-port through hole model of the metal layer shown in fig. 6, and a block in the through hole layer corresponds to the through hole model shown in fig. 7. The common boundaries between the shape blocks and the port faces correspond to the boundaries of the resistance model, dividing the boundaries and ports between the shape blocks into boundary elements. Two boundary elements that are divided are said to be "adjacent" if they belong to a common shape.
Extracting the parasitic resistance between two ports of the network cable, i.e. the first port and the second port, needs to be converted into calculating the conductance between the two ports, i.e. the inverse of the resistance. Setting the potential of the first port to 0, the potential of the second port to 1 volt, and all other ports to be considered as natural surfaces, the conductance between the first port and the second port is numerically equal to the current through the first port or the second port.
The shape block connected with the first port is a shape block 1, and the shape block 1 is connected with one or more other shape blocks. The physique 1 has boundary elements on the first port, and has boundary elements adjacent to the boundary elements on the first port, the adjacent boundary elements being connected to other physiques and not on the first port. Starting from a boundary element that is not on the first port but is adjacent to the first port, the probability of jumping from that boundary element to its adjacent boundary element is obtained by the Markov transition matrix corresponding to the shape block 1 or its connected shape block. And randomly selecting the boundary elements of the jumped targets according to the probability of the jumped targets. And if the target boundary element jumped to in the previous step is on the first port or the second port, stopping the jump and recording the final port of the jump. Otherwise, the boundary element jumped in the previous step is taken as a starting point, the probability of jumping to the adjacent boundary element is obtained by the Markov transfer matrix corresponding to the body block where the boundary element is located, and the target boundary element jumped is randomly selected on the probability. This step is repeated until a jump is made to the first port or the second port.
Repeating the jumping for multiple times from the boundary element adjacent to the first port for multiple times, and counting the number n of the final jumping to the first port1And the number of jumps to the second port n2The total number of times of starting the jump is n1+n2。
Definition of a Markov transfer matrix and its relationship to a boundary conductance matrix
It can be seen that n is the value of n when the setting of the resistance port is satisfied1+n2When the size of the particles is large enough,
infinitely close to the potential of the originating boundary element adjacent to the first port.
Conductance between a first port and its adjacent boundary elements can be obtained from the boundary conductance matrix adjacent to the first port
The current through the first port is
I.e. the conductance between the first port and the second port.
The parasitic resistance between the first port and the second port is then extracted, i.e. the inverse of the conductance
Examples
Fig. 8 is a partial top view of an integrated circuit, fig. 9 is a top view of a shape block on a first metal layer, fig. 10 is a top view of a shape block on a second metal layer, and fig. 11 is a top view of a shape block on a via layer.
FIG. 8 is a partial top view of an integrated circuit, which includes 16 tile blocks, numbered 1-16, having first metal layer 20, second metal layer 30, via layer 40, first port 17, second port 18, third port 19, and nets. The body blocks 1-8, the first port 17 and the second port 18 are on the first metal layer 20, the body blocks 9-13 are on the second metal layer 30, and the body blocks 14-16 are on the via layer 40. Among the 16 shape blocks, as shown in fig. 9, 10 and 11, the shape blocks 1, 3, 4 and 8 on the first metal layer 20 and the shape blocks 12 on the second metal layer correspond to models belonging to metal layer two-end die model types; the model corresponding to the shape block 10 on the first metal layer 20 belongs to a metal layer end model type; the model corresponding to the shape block 2 on the first metal layer 20 belongs to a metal layer three-port model; the models corresponding to the shape blocks 5, 6 and 7 on the first metal layer 20 and the shape blocks 9, 11 and 13 on the second metal layer 30 belong to a metal layer one-port communication hole model class; the corresponding model of the shape blocks 14, 15, 16 on the via layer 40 belongs to the via model class.
Adjacent to the first port 17 is the body block 1 and the boundary element adjacent to the first port 17 is at the interface of the body block 1 and the body block 2, referred to as the originating boundary element 21. Starting from the originating boundary element 21, the probability of jumping from the originating boundary element 21 to its neighboring boundary elements, including the boundary element on the first port 17, the boundary element on the interface of the volume block 2 with the volume block 3 or the volume block 4, is derived from the corresponding markov transition matrices for the volume block 1 and the volume block 2. And continuously repeating the step of randomly jumping to the adjacent boundary element in the probability until jumping to the boundary element of the first port 17 or the second port 18, recording the terminal port of the jump, returning to the original boundary element 21, and starting the jump sequence of the next round.
The potential of the first port 17 is set to 0V, and the potential of the second port 18 is set to 1V. In case the jump sequence is sufficient, the potential of the originating border element 21 is derived or approximated by the number of times the termination to the first port 17 and the second port 18 takes place. The conductance between the originating boundary element 21 and the first port 17 is obtained from the boundary conductance matrix of the corresponding resistance model of the shape block 1, and then the normal current of the first port 17 at this time is obtained from the conductance between the originating boundary element 21 and the first port 17, and the normal current is equal to the conductance between the first port 17 and the second port 18 in value. The resistance between the first port 17 and the second port 18 is the inverse of the resulting conductance.
The invention divides the resistance model port into a plurality of boundary elements, allows the potentials of different boundary elements on the same resistance model port to be different, and reduces the error caused by the nonuniform interface potential; the invention can cover all possible situations in the circuit, can completely control errors in the calculation process, and ensures the precision and the reliability; the invention establishes the Markov transfer matrix library only once for a process, most of the calculation processes are carried out during the process of establishing the library, the extraction time is shortened during the extraction of the parasitic resistance, and the high efficiency can be achieved.
It should be noted that the above-mentioned embodiments are exemplary, and that those skilled in the art, having benefit of the present disclosure, may devise various arrangements that are within the scope of the present disclosure and that fall within the scope of the invention. It should be understood by those skilled in the art that the present specification and figures are illustrative only and are not limiting upon the claims. The scope of the invention is defined by the claims and their equivalents.
Claims (10)
1. A parasitic parameter extraction method is characterized by comprising the following steps:
dividing the specified resistance model boundary into a plurality of boundary elements;
taking the port and the model boundary element in the resistance model as ports, and calculating a boundary conductance matrix of the port and/or the model boundary element in the resistance model;
converting the boundary conductance matrix to a Markov transition matrix, an
The method comprises the steps of extracting parasitic resistance in an integrated circuit design under the same process by using a Markov transfer matrix library.
2. The parasitic parameter extraction method according to claim 1, further comprising the steps of:
reading in a Markov transfer matrix library of a corresponding process;
reading in and translating all or part of network cables in the integrated circuit layout and dividing each read-in internet cable into a plurality of sub-network cables;
reading in a Markov transfer matrix of a process corresponding to each sub-net line; and
the conductance between the ports is calculated by the Markov transfer matrix, and the reciprocal of the conductance between the ports is taken as the parasitic resistance of the network cable.
3. The parasitic parameter extraction method according to claim 1, comprising the steps of:
and storing the Markov transfer matrix of each resistance model under the same process into a Markov transfer matrix library.
4. Parasitic parameter extraction method according to one of the previous claims, characterized in that it further comprises the steps of:
setting the potential of the first port to be 0V, the potential of the second port to be 1V, and the other ports to be natural surfaces;
obtaining the probability of jumping from the initial boundary element adjacent to the first port to the adjacent boundary element by the Markov transfer matrix corresponding to the body block connected with the first port;
randomly selecting a target boundary element to be jumped according to the probability of jumping to the adjacent boundary element;
starting jumping by taking the starting boundary element as an origin and continuously jumping by taking the target boundary element as a next origin according to the corresponding jumping probability until jumping to the first port or the second port is stopped;
repeating the jumping step with the starting boundary element as the origin for multiple times;
counting the number n of times with the first port as the terminal point1Counting the number of times n of the second port as the end point2；
Obtaining the conductance between the first port and the originating boundary element according to the boundary conductance matrix corresponding to the originating boundary element
Calculating the conductance between the first port and the second port, i.e. the current of the first port
Taking the reciprocal of the conductance between the first port and the second port as the resistance between the first port and the second port
5. The parasitic parameter extraction process of claim 1 wherein said step of converting the boundary conductance matrix to a markov transition matrix comprises:
using formulas
The transition boundary conductance matrix is a markov transition matrix, where M is the markov transition matrix,
is a boundary conductance matrix, I is an identity matrix with the same dimension as the boundary conductance matrix,
is to the matrix
Taking the diagonal operation to carry out the diagonal operation,
the inverse of the boundary conductance matrix after the diagonal operation is taken.
6. The parasitic parameter extraction method according to claim 1, further comprising the steps of:
translating all or part of network cables in the integrated circuit board diagram and converting the network cables into a data structure format which is internally indexed according to a space region;
and obtaining a circuit board diagram on the actual silicon chip by the integrated circuit design layout and the process parameter file under the corresponding process.
7. The parasitic parameter extraction process of claim 1 wherein said resistance model is generated by reading in or inputting a process feature size construct of a model template and a process parameter file,
each of the resistance models corresponds to a markov transfer matrix.
8. The parasitic parameter extraction method of claim 1 wherein said resistance model comprises a metal layer two-port model, a metal layer one-port model, a metal layer three-port model, a metal layer via model, a metal layer one-port via model, and a via model,
and the ports in the resistance model and the model boundary elements are used as ports for calculating a boundary conductance matrix.
9. The parasitic parameter extraction process of claim 8 wherein said model boundary elements are boundary elements of boundaries within the conductor adjacent to other models, said model boundary elements not including Newman boundary elements.
10. The parasitic parameter extraction process of claim 1 wherein said markov transfer matrix satisfies sufficient requirements to:
all elements are non-negative; and the sum of the elements in each row is 1; the diagonal element is 0.
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