CN107170678A - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN107170678A CN107170678A CN201610128530.3A CN201610128530A CN107170678A CN 107170678 A CN107170678 A CN 107170678A CN 201610128530 A CN201610128530 A CN 201610128530A CN 107170678 A CN107170678 A CN 107170678A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02389—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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Abstract
A kind of forming method of semiconductor devices, including：Substrate is provided, substrate has central area and fringe region；Sequentially form metal material layer, sacrificial material layer and barrier material layer from down to up in substrate；Etching metal material layer, sacrificial material layer and barrier material layer are until expose substrate surface, in central area and fringe region formation metal level, sacrifice layer and barrier layer；Form the first interlayer dielectric layer of covering barrier layer and substrate；The first interlayer dielectric layer is planarized until exposing the top surface on central area and fringe region barrier layer；Etching removes the first interlayer dielectric layer of barrier layer and segment thickness, and the top surface of the first interlayer dielectric layer is flushed with the lower surface of sacrifice layer；Remove after sacrifice layer, form the second interlayer dielectric layer of covering metal level and the first interlayer dielectric layer.Methods described improves the fringe region of semiconductor devices and the caliper uniformity of central area, and reduction process costs.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of forming method of semiconductor devices.
Background technology
With the development of ic manufacturing technology, in integrated circuit the precision of various devices will
Ask and increasingly improve, and the fringe region of wafer and the caliper uniformity of central area are for the essence of subsequent technique
Effects of Density is most important.
Prior art is in power device, and such as radio frequency circuit device is, it is necessary to form metallic traces layer, generally
The thickness of metallic traces layer is more than 2 μm.Form the base of the semiconductor devices with metallic traces layer
This step, with reference to Fig. 1 and Fig. 2, including：Semiconductor substrate 100 is provided, the Semiconductor substrate 100 has
There are central area (I regions) and fringe region (II region)；Insulation is formed on a semiconductor substrate 100
Layer 110；Metallic traces layer 120 is made on insulating barrier 110；Form covering metallic traces layer 120 and partly lead
The interlayer dielectric layer 130 of body substrate 100；Planarize the interlayer dielectric layer 130.
However, semiconductor devices central area (I regions) and the fringe region (II of prior art formation
Region) caliper uniformity it is poor, and process costs are higher.
The content of the invention
The problem of present invention is solved is to provide a kind of forming method of semiconductor devices, to cause semiconductor device
The central area of part and the caliper uniformity of fringe region are improved, while reducing process costs.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：There is provided
Substrate, the substrate has central area and fringe region；Sequentially form from down to up on the substrate
Metal material layer, sacrificial material layer and barrier material layer；Etch the metal material layer, sacrificial material layer
With barrier material layer until expose substrate surface, the central area and fringe region formation metal level,
Sacrifice layer and barrier layer；Form the first interlayer dielectric layer of the covering barrier layer and substrate；Planarization institute
The first interlayer dielectric layer is stated until exposing the top surface on central area and fringe region barrier layer；Etching
The first interlayer dielectric layer of the barrier layer and segment thickness is removed, and makes first interlayer dielectric layer
Top surface is flushed with the lower surface of the sacrifice layer；Remove after the sacrifice layer, form covering described
Second interlayer dielectric layer of metal level and the first interlayer dielectric layer.
Optionally, the material on the barrier layer is silicon nitride.
Optionally, the thickness on the barrier layer is 5nm~5000nm.
Optionally, the technique for forming the barrier material layer is plasma activated chemical vapour deposition technique, Asia
Sub-atmospheric CVD technique or low-pressure chemical vapor deposition process.
Optionally, the material of the sacrifice layer is indefinite form carbon.
Optionally, the thickness of the sacrifice layer is 5nm~5000nm.
Optionally, the technique for forming the sacrificial material layer is plasma activated chemical vapour deposition technique, Asia
Sub-atmospheric CVD technique or low-pressure chemical vapor deposition process.
Optionally, the technique for planarizing first interlayer dielectric layer is chemical mechanical milling tech.
Optionally, the technique that etching removes the first interlayer dielectric layer of the barrier layer and segment thickness is each
Anisotropy dry carving technology.
Optionally, during the first interlayer dielectric layer that etching removes the barrier layer and segment thickness,
The ratio of etch rate to barrier layer and the etch rate to the first interlayer dielectric layer is 1：30~30：1.
Optionally, the technique of the removal sacrifice layer is：The sacrifice layer is removed using oxygen plasma.
Compared with prior art, technical scheme has advantages below：
Due to the sacrificial material layer and barrier material that are sequentially formed from down to up on the metal material layer
Layer, etches after the metal material layer, sacrificial material layer and barrier material layer, forms metal level, position
Sacrifice layer in the top surface of metal level and the barrier layer positioned at sacrifice layer top surface.In planarization institute
During stating the first interlayer dielectric layer, generally to the planarization rate of central area with to fringe region
Planarization rate has certain difference；Fringe region is put down when the planarization rate to central area is more than
During smoothization speed, in the critical moment for the barrier layer top surface for exposing central area, fringe region is also
It is not removed in the presence of the first interlayer dielectric layer higher than barrier layer top surface, due to the presence on barrier layer,
The barrier layer can stop at the planarization process to central area at the top on the barrier layer of central area
Surface, and edge region continues to planarize the first interlayer dielectric layer until exposing the stop of fringe region
The top surface of layer, final edge region and central area will be above the first of barrier layer top surface
Interlayer dielectric layer is removed so that the central area of semiconductor devices and the thickness of fringe region are homogeneous；When right
When the planarization rate of central area is less than the planarization rate to fringe region, fringe region is being exposed
Barrier layer top surface critical moment, central area also exist higher than barrier layer top surface first
Interlayer dielectric layer is not removed, and due to the presence on barrier layer, the barrier layer can be by fringe region
Planarization process stop edge region barrier layer top surface, and central area continue it is flat
Change the first interlayer dielectric layer until the top surface on the barrier layer of central area is exposed, finally in marginal zone
The first interlayer dielectric layer that domain and central area will be above barrier layer top surface is removed so that semiconductor
The central area of device and the thickness of fringe region are homogeneous；Then etching removes the barrier layer and part thickness
First interlayer dielectric layer of degree, and make the top surface and the sacrifice layer of first interlayer dielectric layer
Lower surface is flushed, in the process, and the lower surface of sacrifice layer can weigh the first layer for needing to remove
Between dielectric layer thickness, and as remove barrier layer stop-layer, the sacrifice layer is removed afterwards so that
The top surface of first interlayer dielectric layer is flushed；Formed after the second interlayer dielectric layer, the second interlayer dielectric layer
Top surface flush；The thickness of the final central area for causing semiconductor devices and fringe region is homogeneous.
Further, since the presence on barrier layer, can stop at planarization process the top surface on barrier layer,
So as to realize that the top surface on barrier layer and the top surface of the first interlayer dielectric layer are flushed.In the process,
Avoid and rely primarily on grinding and remove in the first interlayer dielectric layer thicker thickness to reach barrier layer and the
The purpose that the top surface of one interlayer dielectric layer is flushed, because the cost of flatening process compares other steps
Cost it is larger, and the present invention removes thicker thickness in the first interlayer dielectric layer without grinding, significantly
Reduce process costs.
Brief description of the drawings
Fig. 1 to Fig. 2 is the structural representation of prior art semiconductor devices forming process；
Fig. 3 to Fig. 9 is the structural representation of semiconductor devices forming process in one embodiment of the invention.
Embodiment
As described in background, the semiconductor device edge region and central area of prior art formation
Caliper uniformity is poor.
Research is found, with reference to Fig. 1 and Fig. 2, because the thickness of metallic traces layer 120 is more than 2 μm, is formed
After metallic traces layer 120, the difference in height on the surface of semiconductor devices is larger, typically at least needs 3 μm of deposition
Metallic traces layer 120, insulating barrier 110 and Semiconductor substrate can be just completely covered in interlayer dielectric layer 130 above
100 so that deposited after interlayer dielectric layer 130, the difference in height of semiconductor device surface is larger, therefore needs
Interlayer dielectric layer 130 is planarized using flatening process；Planarizing the process of the interlayer dielectric layer 130
In, the interlayer dielectric layer 130 on metallic traces layer 120 and on Semiconductor substrate 100 can be ground simultaneously
To, it is necessary to increase the thickness ground to interlayer dielectric layer 130 to can reach that semiconductor device surface is flat
Purpose.Because the more other steps of the cost of flatening process are (such as conventional depositing operation：It is plasmarized
Learn gas-phase deposition etc.) cost it is larger, cause process costs to dramatically increase.
Simultaneously as to central area and inconsistent to the grinding rate of fringe region so that planarization institute
State after interlayer dielectric layer 130, the caliper uniformity of central area and fringe region is poor.
On this basis, the present invention provides a kind of forming method of semiconductor devices, including：Substrate is provided,
The substrate has central area and fringe region；Sequentially form metal material from down to up on the substrate
The bed of material, sacrificial material layer and barrier material layer；Etch the metal material layer, sacrificial material layer and stop
Material layer is until expose substrate surface, in the central area and fringe region formation metal level, sacrifice
Layer and barrier layer；Form the first interlayer dielectric layer of the covering barrier layer and substrate；Planarize described
One interlayer dielectric layer is until expose the top surface on central area and fringe region barrier layer；Etching is removed
The barrier layer and the first interlayer dielectric layer of segment thickness, and make the top of first interlayer dielectric layer
Surface is flushed with the lower surface of the sacrifice layer；Remove after the sacrifice layer, form the covering metal
Second interlayer dielectric layer of layer and the first interlayer dielectric layer.Methods described causes the center of semiconductor devices
The caliper uniformity of domain and fringe region is improved, while reducing process costs.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 3 to Fig. 9 is the structural representation of semiconductor devices forming process in one embodiment of the invention.
With reference to Fig. 3 there is provided substrate, the substrate has central area (III region) and fringe region (IV
Region).
The substrate includes Semiconductor substrate 200 and the insulating barrier 210 in Semiconductor substrate 200.
The Semiconductor substrate 200 can be monocrystalline silicon, polysilicon or non-crystalline silicon；Semiconductor substrate 200
Can also be the semi-conducting materials such as silicon, germanium, SiGe, GaAs；The Semiconductor substrate 200 may be used also
To be other semi-conducting materials, no longer illustrate one by one here.In the present embodiment, the Semiconductor substrate 200
Material be silicon.
There can also be semiconductor structure in the Semiconductor substrate 200, the semiconductor structure is PMOS
Transistor, nmos pass transistor, CMOS transistor, capacitor, resistor or inductor.
The fringe region (IV region) is located at the periphery in central area (III region).
The insulating barrier 210 is used for insulator-semiconductor substrate 200 and the metal level being subsequently formed.It is described exhausted
The material of edge layer 210 is silica, silicon oxynitride or silicon oxide carbide.Form the work of the insulating barrier 210
Skill is depositing operation.
With continued reference to Fig. 3, sequentially form metal material layer 220 from down to up on the substrate, sacrifice material
The bed of material 230 and barrier material layer 240.
The material of the metal material layer 220 can be aluminium or aluminium copper.The metal material layer 220
Thickness be 2 μm~10 μm, such as 2 μm, 5um or 10 μm.Form the work of the metal material layer 220
Skill is physical gas-phase deposition or electroplating technology.The metal material layer 220 is to be subsequently formed metal
Layer provides raw material.
In the present embodiment, it can also include：The first titanium layer is formed between substrate and metal material layer 220
(not shown) and the first titanium nitride layer (not shown) on the first titanium layer (not shown), in metal
The second titanium layer and the second nitrogen on the second titanium layer are formed between material layer 220 and sacrificial material layer 230
Change titanium layer.
First titanium layer is act as：Prevent metal material layer 220 from diffusing in Semiconductor substrate 200；First
Titanium nitride layer is act as：Isolate the first titanium layer and metal material layer 220, prevent from forming metal material layer
During 220, the titanium layer of metal material layer 220 and first formation alloy.
Second titanium layer is nonessential layer；Second titanium nitride layer is act as：In patterned metal material layer 220
During, it is necessary to form patterned photoresist layer on metal material layer 220, the second titanium nitride layer is made
For the bottom anti-reflective between patterned photoresist layer on metal material layer 220 and metal material layer 220
Layer.
The material of the sacrificial material layer 230 can be indefinite form carbon.Form the sacrificial material layer 230
Technique be depositing operation, such as plasma activated chemical vapour deposition technique, sub-atmospheric pressure chemical vapor deposition
Technique or low-pressure chemical vapor deposition process.The sacrificial material layer 230 provides to be subsequently formed sacrifice layer
Raw material.
In the present embodiment, the material of the sacrificial material layer 230 is indefinite form carbon.Sacrificial material layer 230
It is advantageous in that using indefinite form carbon：Formation process is simple, and cost is relatively low, when subsequently removing sacrifice layer
It is relatively easy to.
The material of the barrier material layer 240 can be silicon nitride.
The technique for forming the barrier material layer 240 is depositing operation, such as plasma activated chemical vapour deposition
Technique, sub-atmospheric pressure chemical vapor deposition method or low-pressure chemical vapor deposition process.The barrier material
Layer 240 provides raw material to be subsequently formed barrier layer.
With reference to Fig. 4, the metal material layer 220, sacrificial material layer 230 and barrier material layer 240 are etched
Until substrate surface is exposed, in the central area and fringe region formation metal level 221, sacrifice layer
231 and barrier layer 241.
The technique for etching the metal material layer 220, sacrificial material layer 230 and barrier material layer 240 is each
Anisotropy dry carving technology, specifically：Patterned mask is formed on the surface of the barrier material layer 240
Layer (not shown), the patterned mask layer defines metal level 221 to be formed, sacrifice layer 231
With the position on barrier layer 241；Then using the patterned mask layer as mask, using anisotropic dry
Carving technology etches the metal material layer 220, sacrificial material layer 230 and barrier material layer 240 until exposure
Go out the surface of insulating barrier 210, so as to form metal level 221, the sacrifice positioned at the top surface of metal level 221
Layer 231 and the barrier layer 241 positioned at the top surface of sacrifice layer 231.
The thickness on the barrier layer 241 is 5nm~5000nm, such as 5nm, 100nm, 1000nm, 3000nm
Or 5000nm.The thickness on the barrier layer 241 selects the meaning of this scope to be：If the barrier layer 241
Thickness be less than 5nm, cause deposit barrier layer 241 during to the controllable of the thickness of barrier layer 241
Property be deteriorated, the difference in thickness on the barrier layer 241 of different zones is larger, the inter-level dielectric of subsequent planarization first
The surface on barrier layer 241 can be stopped at after layer, causes the flatness of different zones semiconductor device surface to become
Difference；If the thickness on the barrier layer 241 is more than 5000nm, technique is caused to waste.
The thickness of the sacrifice layer 231 is 5nm~5000nm, such as 5nm, 100nm, 1000nm, 3000nm
Or 5000nm.The thickness of the sacrifice layer 231 selects the meaning of this scope to be：If the sacrifice layer 231
Thickness be less than 5nm, for sacrifice layer 231 thickness adjustable scope reduce, in subsequent etching
During the first interlayer dielectric layer for removing the barrier layer 241 and segment thickness, when to barrier layer 241
Etch rate when being less than to the etch rate of the first interlayer dielectric layer, it is impossible to effectively pass through to adjust and sacrifice
The thickness of layer 231 matches to be finally reached to meet with etching technics：Exposed removing barrier layer 241
Go out the critical moment of the top surface of sacrifice layer 231, the top surface of the first interlayer dielectric layer is higher than sacrifice layer
231 lower surface is flushed with the lower surface of sacrifice layer 231, it is therefore desirable to relied primarily on to etching work
Skill parameters, which are adjusted, can be only achieved requirements above, add the difficulty of technique；If the sacrifice layer
231 thickness is more than 5000nm, causes technique to waste.
Because the thickness of the metal material layer 220 is 2 μm~10 μm so that the thickness of metal level 221
Also it is 2 μm~10 μm.
With reference to Fig. 5, the first interlayer dielectric layer 250 of the covering barrier layer 241 and substrate is formed.
The material of first interlayer dielectric layer 250 is silica, silicon oxynitride or silicon oxide carbide.Shape
Into the first interlayer dielectric layer 250 technique be depositing operation, such as plasma activated chemical vapour deposition technique,
Sub-atmospheric pressure chemical vapor deposition method or low-pressure chemical vapor deposition process.
Formed after the first interlayer dielectric layer 250, the covering barrier layer 241 of the first interlayer dielectric layer 250, sacrifice
Layer 231, metal level 221 and substrate, the top surface of the first interlayer dielectric layer 250 be it is rough,
Therefore need to planarize the top surface of the first interlayer dielectric layer 250 in subsequent planarization technique.
With reference to Fig. 6, first interlayer dielectric layer 250 is planarized until exposing central area and marginal zone
The surface on domain barrier layer 241.
The technique for planarizing first interlayer dielectric layer 250 can be chemical mechanical milling tech.
During the first interlayer dielectric layer 250 is planarized, the planarization rate generally to central area
It is inconsistent with planarization rate to fringe region；When the planarization rate to central area is more than to edge
During the planarization rate in region, in the critical moment for the top surface of barrier layer 241 for exposing central area,
Fringe region is not removed also in the presence of the first interlayer dielectric layer 250 higher than the top surface of barrier layer 241,
Due to the presence on barrier layer 241, the barrier layer 241 can stop the planarization process to central area
Only central area barrier layer 241 top surface, and edge region continue planarize the first interlayer
Dielectric layer 250 is until expose the top surface on the barrier layer 241 of fringe region, final edge region
The first interlayer dielectric layer 250 that the top surface of barrier layer 241 is will be above with central area is removed so that
The central area of semiconductor devices and the thickness of fringe region are homogeneous；When to the planarization rate of central area
During less than to the planarization rate of fringe region, the top surface of barrier layer 241 of fringe region is being exposed
Critical moment, central area also exist higher than the top surface of barrier layer 241 the first interlayer dielectric layer 250
It is not removed, due to the presence on barrier layer 241, the barrier layer 241 can be by fringe region
Planarization process stops the top surface on the barrier layer 241 of edge region, and continues flat in central area
First interlayer dielectric layer of smoothization 250 is until expose the top surface on the barrier layer 241 of central area, most
Whole edge region and central area will be above the first interlayer dielectric layer 250 of the top surface of barrier layer 241
Remove so that the central area of semiconductor devices and the thickness of fringe region are homogeneous.
Further, since the presence on barrier layer 241, can stop at planarization process on the top on barrier layer 241
Portion surface, thus realize barrier layer 241 top surface and the first interlayer dielectric layer 250 top surface it is neat
It is flat.In the process, it is to avoid rely primarily on grinding and remove thickness thicker in first interlayer dielectric layer 250
To reach purpose that the top surface of the interlayer dielectric layer 250 of barrier layer 241 and first is flushed, due to flat
The cost of chemical industry skill is larger compared to the cost of other steps, and the present invention removes the first interlayer without grinding and is situated between
Thicker thickness, significantly reduces process costs in matter layer 250.
With reference to Fig. 7, etching removes the first interlayer dielectric layer 250 of the barrier layer 241 and segment thickness,
And the top surface of first interlayer dielectric layer 250 is flushed with the lower surface of the sacrifice layer 231.
Specifically, etching removes the first interlayer dielectric layer 250 of the barrier layer 241 and segment thickness
Technique is anisotropy dry carving technology.
During the first interlayer dielectric layer 250 that etching removes the barrier layer 241 and segment thickness,
The ratio of etch rate to barrier layer 241 and the etch rate to the first interlayer dielectric layer 250 is 1：
30~30：1.
It should be noted that removing the first interlayer dielectric layer of the barrier layer 241 and segment thickness in etching
It is fast much smaller than the etching to the first interlayer dielectric layer 250 to the etch rate of sacrifice layer 231 during 250
Rate, and much smaller than the etch rate to barrier layer 241.In the present embodiment, the barrier layer is removed in etching
241 and segment thickness the first interlayer dielectric layer 250 during, it is relative to the etch rate of sacrifice layer 231
In the etch rate to the first interlayer dielectric layer 250 etching selection ratio be 1/10~1/1000, such as 1/10,
1/50th, 1/100 or 1/1000, to the etch rate of sacrifice layer 231 relative to the etch rate to barrier layer 241
Etching selection ratio be 1/10~1/1000, such as 1/10,1/50,1/100 or 1/1000.
It is another it should be noted that, remove the first inter-level dielectric of the barrier layer 241 and segment thickness in etching
During layer 250, the etch rate on barrier layer 241 can be more than to the first interlayer dielectric layer 250
Etch rate, on this condition, remove barrier layer 241 expose the top surface of sacrifice layer 231
Critical moment, the top surface of the first interlayer dielectric layer 250 is higher than the top surface of sacrifice layer 231；So
Afterwards continue etching of first layer between dielectric layer 250 until the first interlayer dielectric layer 250 top surface with it is described
The lower surface of sacrifice layer 231 is flushed, during dielectric layer 250 between continuing etching of first layer, by
The etch rate to the first interlayer dielectric layer 250 is much smaller than in the etch rate to sacrifice layer 231, will not
Sacrifice layer 231 is etched into removal, the time of control etching enables to the top of the first interlayer dielectric layer 250
Portion surface is flushed with the lower surface of the sacrifice layer 231.
During the first interlayer dielectric layer 250 that etching removes the barrier layer 241 and segment thickness,
Etch rate to the first interlayer dielectric layer 250 can be equal to the etch rate on barrier layer 241, herein
Under the conditions of, expose the critical moment of the top surface of sacrifice layer 231, first layer on removal barrier layer 241
Between the top surface of dielectric layer 250 flushed with the top surface of sacrifice layer 231；Then proceed to etching first
Interlayer dielectric layer 250 is until the bottom of the top surface and the sacrifice layer 231 of the first interlayer dielectric layer 250
Portion surface is flushed.
During the first interlayer dielectric layer 250 that etching removes the barrier layer 241 and segment thickness,
Etch rate to the first interlayer dielectric layer 250 can be less than to the etch rate on barrier layer 241, herein
Under the conditions of, it is necessary to so that：Remove barrier layer 241 expose the top surface of sacrifice layer 231 it is critical when
Carve, lower surface or and sacrifice layer of the top surface higher than sacrifice layer 231 of the first interlayer dielectric layer 250
231 lower surface is flushed；If in the process, the top surface of the first interlayer dielectric layer 250 is higher than sacrificial
The lower surface of domestic animal layer 231, then dielectric layer 250 is until the first interlayer dielectric layer between continuing etching of first layer
250 top surface is flushed with the lower surface of the sacrifice layer 231.
If not forming sacrifice layer 231, the first layer of the barrier layer 241 and segment thickness is removed in etching
Between during dielectric layer 250, when to the etch rate of the interlayer dielectric layer 250 of barrier layer 241 and first
When inconsistent, cause to remove shape after the first interlayer dielectric layer 250 of the barrier layer 241 and segment thickness
Into semiconductor devices uneven surface.
It is described in the first interlayer dielectric layer 250 that etching removes the barrier layer 241 and segment thickness
Sacrifice layer 231 is act as：(1) lower surface of sacrifice layer 231 can weigh need to remove first
The thickness of interlayer dielectric layer 250；(2) as the stop-layer for removing barrier layer 241；(3) gone in etching
Except the barrier layer 241 and segment thickness the first interlayer dielectric layer 250 during, when to barrier layer
When 241 etch rate is less than the etch rate to the first interlayer dielectric layer 250, it can be sacrificed by adjusting
The thickness and etching technics of layer 231, which match, to be reached：Sacrifice layer 231 is exposed removing barrier layer 241
The critical moment of top surface, the top surface of the first interlayer dielectric layer 250 is higher than the bottom of sacrifice layer 231
Portion surface is flushed with the lower surface of sacrifice layer 231.
As can be seen here, the first interlayer dielectric layer 250 of the barrier layer 241 and segment thickness is removed in etching
During, when inconsistent to the etch rate of the interlayer dielectric layer 250 of barrier layer 241 and first,
It can realize：After the first interlayer dielectric layer 250 for removing the barrier layer 241 and segment thickness so that
The top surface of first interlayer dielectric layer 250 is flushed with the lower surface of the sacrifice layer 231.
With reference to Fig. 8, the sacrifice layer 231 (referring to Fig. 7) is removed.
The technique for removing the sacrifice layer 231 is：The sacrifice layer 231 is removed using oxygen plasma.
Remove after sacrifice layer 231, the surface of the semiconductor devices of formation is flat, and semiconductor devices is in
The thickness of heart district domain and fringe region is homogeneous.
Then, with reference to Fig. 9, the second of the covering interlayer dielectric layer 250 of metal level 221 and first is formed
Interlayer dielectric layer 260.
The material of second interlayer dielectric layer 260 is silica, silicon oxynitride or silicon oxide carbide.Formed
The technique of second interlayer dielectric layer 260 be depositing operation, such as plasma activated chemical vapour deposition technique,
Sub-atmospheric pressure chemical vapor deposition method or low-pressure chemical vapor deposition process.
It is equal in the thickness of central area and fringe region due to removing semiconductor devices after the sacrifice layer 231
One so that formed after the second interlayer dielectric layer 260, the fringe region of semiconductor devices and the thickness of central area
Degree is homogeneous.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (11)
1. a kind of forming method of semiconductor devices, it is characterised in that including：
Substrate is provided, the substrate has central area and fringe region；
Sequentially form metal material layer, sacrificial material layer and barrier material layer from down to up on the substrate；
The metal material layer, sacrificial material layer and barrier material layer are etched until exposing substrate surface,
The central area and fringe region formation metal level, sacrifice layer and barrier layer；
Form the first interlayer dielectric layer of the covering barrier layer and substrate；
First interlayer dielectric layer is planarized until exposing the top on central area and fringe region barrier layer
Surface；
Etching removes the first interlayer dielectric layer of the barrier layer and segment thickness, and first interlayer is situated between
The top surface of matter layer is flushed with the lower surface of the sacrifice layer；
Remove after the sacrifice layer, the second interlayer for forming the covering metal level and the first interlayer dielectric layer is situated between
Matter layer.
2. the forming method of semiconductor devices according to claim 1, it is characterised in that the barrier layer
Material be silicon nitride.
3. the forming method of semiconductor devices according to claim 1, it is characterised in that the barrier layer
Thickness be 5nm~5000nm.
4. the forming method of semiconductor devices according to claim 1, it is characterised in that form the resistance
The technique of obstructing material layer is plasma activated chemical vapour deposition technique, sub-atmospheric pressure chemical vapor deposition work
Skill or low-pressure chemical vapor deposition process.
5. the forming method of semiconductor devices according to claim 1, it is characterised in that the sacrifice layer
Material be indefinite form carbon.
6. the forming method of semiconductor devices according to claim 1, it is characterised in that the sacrifice layer
Thickness be 5nm~5000nm.
7. the forming method of semiconductor devices according to claim 1, it is characterised in that formed described sacrificial
The technique of domestic animal material layer is plasma activated chemical vapour deposition technique, sub-atmospheric pressure chemical vapor deposition work
Skill or low-pressure chemical vapor deposition process.
8. the forming method of semiconductor devices according to claim 1, it is characterised in that planarization is described
The technique of first interlayer dielectric layer is chemical mechanical milling tech.
9. the forming method of semiconductor devices according to claim 1, it is characterised in that etching removes institute
The technique for stating the first interlayer dielectric layer of barrier layer and segment thickness is anisotropy dry carving technology.
10. the forming method of semiconductor devices according to claim 1, it is characterised in that removed in etching
During first interlayer dielectric layer of the barrier layer and segment thickness, to the etch rate on barrier layer
Ratio with the etch rate to the first interlayer dielectric layer is 1：30~30：1.
11. the forming method of semiconductor devices according to claim 1, it is characterised in that remove described sacrificial
Domestic animal layer technique be：The sacrifice layer is removed using oxygen plasma.
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