CN107168678A - A kind of improved floating dual MAC and floating point multiplication addition computational methods - Google Patents

Abstract

Embodiments of the present invention provide an improved floating-point multiply-accumulator and a floating-point multiply-accumulate calculation method. The floating-point multiplier includes at least two floating-point multipliers and a multi-input adder. The floating-point multiplier is composed of a sign bit XOR circuit, a mantissa multiplier and an exponent adder. The floating-point multiplier receives a normalization The floating-point number is multiplied and outputted as a non-normalized floating-point number, and the adder receives the non-normalized floating-point number and accumulates the input non-normalized floating-point number and outputs a normalized floating-point number. By setting the floating-point part of the multiplier to only include the sign bit XOR circuit, the mantissa multiplier and the exponent adder do not include the normalization module, the normalized floating-point number is received and multiplied, and the non-normalized floating-point number is output by the adder Perform addition operations and output normalized floating-point numbers, optimize the floating-point multiply-adder from the hardware circuit, improve the operational efficiency of the floating-point multiply-adder, and reduce the area and power consumption of the hardware circuit.

Description

An Improved Floating Point Multiply Adder and Floating Point Multiply Add Calculation Method

technical field

The embodiment of the present invention relates to the technical field of computer hardware structure and circuit design, and in particular to an improved floating-point multiply-accumulator and a floating-point multiply-accumulate calculation method.

Background technique

In recent years, various machine learning algorithms such as deep convolutional neural networks have been widely used in many fields, and these machine learning algorithms have become more computing-intensive and storage-intensive with the update of technology, correspondingly required computing resources and storage Resources are also increasing. In order to solve this problem, the development of special hardware has become one of the solutions recognized by academia and industry. Academia and industry have proposed many hardware acceleration platforms with different architectures. However, there is no method for optimizing the design of the hardware circuit to improve the operation efficiency. Therefore, it is an urgent technical problem to be solved in the industry to provide a method for optimizing the hardware circuit to improve the operation efficiency of the floating-point multiply-adder.

Contents of the invention

In order to solve the problems existing in the prior art, an embodiment of the present invention provides an improved floating-point multiply-accumulator and a floating-point multiply-accumulate calculation method.

On the one hand, the embodiment of the present invention provides an improved floating-point multiply-adder, comprising at least two floating-point part multipliers and a multi-input adder, the floating-point part multiplier is composed of sign bit XOR circuit, mantissa multiplication Composed of a multiplier and an exponent adder, the floating-point multiplier receives a normalized floating-point number and performs multiplication calculation to output a non-normalized floating-point number, and the adder receives the non-normalized floating-point number and converts the input non-normalized floating-point number The normalized floating-point numbers are accumulated and output as normalized floating-point numbers. The non-normalized floating-point numbers are composed of sign bits, non-normalized mantissas and exponent parts. The normalized floating-point numbers are composed of sign bits, normalized Mantissa and exponent parts.

On the other hand, an embodiment of the present invention provides a floating point multiplication and addition calculation method, including:

Receives at least four normalized floating point inputs;

performing a multiplication operation on the normalized floating-point number to obtain a non-normalized floating-point number;

The non-normalized floating-point numbers are added to obtain the normalized floating-point numbers.

The improved floating-point multiply-accumulator and the floating-point multiply-accumulate calculation method provided by the embodiment of the present invention, by setting at least two floating-point partial multipliers and a multi-input adder, the floating-point partial multiplier only includes a sign bit XOR circuit, The mantissa multiplier and the exponent adder do not include the normalization module. After receiving the normalized floating-point number and performing the multiplication operation, the non-normalized floating-point number is output. The adder performs the addition operation and outputs the normalized floating-point number. From the aspect of hardware circuit The floating-point multiply-accumulator is optimized and the operation efficiency of the floating-point multiply-accumulator is improved, and the area and power consumption of the hardware circuit are reduced.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a floating-point multiply-accumulator provided by an embodiment of the present invention;

2 is a schematic structural diagram of a floating-point part multiplier in a floating-point multiply-accumulator provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a sixteen-input floating-point multiply-accumulator provided by an embodiment of the present invention;

4 is a schematic structural diagram of an eight-input adder in a sixteen-input floating-point multiply-adder provided by an embodiment of the present invention;

FIG. 5 is a schematic flowchart of a floating-point multiply-accumulate calculation method provided by an embodiment of the present invention.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Fig. 1 is a schematic structural diagram of a floating-point multiplier provided by an embodiment of the present invention, and Fig. 2 is a schematic structural diagram of a floating-point multiplier in a floating-point multiplier provided by an embodiment of the present invention, as shown in Fig. 1 and Fig. 2 , the floating-point multiplier-accumulator provided by the embodiment of the present invention includes at least two floating-point part multipliers 1 and a multi-input adder 2, and the floating-point part multiplier is composed of a sign bit XOR circuit 11, a mantissa multiplier 12 and Exponent adder 13 is made up of, and described floating-point part multiplier 1 receives normalized floating-point number and carries out multiplication calculation and obtains non-normalized floating-point number, and described adder 2 accumulates described non-normalized floating-point number and outputs normalization A normalized floating-point number, the non-normalized floating-point number is composed of a sign bit, a non-normalized mantissa and an exponent part, and the normalized floating-point number is composed of a sign bit, a normalized mantissa and an exponent part.

The operation of the convolutional neural network is composed of a large number of continuous multiplication and addition. The operation method in the prior art is to use multiple independent floating-point multipliers and a multi-input adder for operation: each multiplication calculation outputs a normalized The multi-input adder is also an addition tree composed of multiple adders, and each addition operation outputs a normalized floating-point number. The points are used as input for the next stage of addition. The normalized floating-point number mentioned here refers to a floating-point number conforming to the IEEE754 standard. The floating-point multiplier-adder that the embodiment of the present invention provides is made up of a plurality of floating-point part multipliers 1 and a multi-input adder 2. The so-called floating-point part multiplier refers to only a sign bit XOR circuit 11 and a mantissa multiplier 12. and exponent adder 13 constitute a multiplier that does not include a normalization module. When performing multiplication and addition operations, a floating-point part multiplier receives two normalized floating-point number inputs, and the sign bit of the two floating-point numbers is XORed by the sign bit XOR circuit 11 to obtain a new sign bit, and the sign bit is obtained by the mantissa The multiplier 12 multiplies the mantissa bits of the two floating-point numbers to obtain a new mantissa bit, and the exponent adder 13 adds the exponents on the exponent bits of the two floating-point numbers to obtain a new exponent bit. Since the mantissa multiplier 12 multiplies the mantissa bits of two floating-point numbers, the obtained new mantissa bits cannot guarantee to still meet the requirements of normalization, so the result obtained is a non-normalized mantissa. The normalized mantissa and new exponent bits form an unnormalized floating-point number. The non-normalized floating-point number obtained through the multiplication-adder operation of the floating-point part is directly used as the input of the multi-input adder, and the normalized floating-point number that meets the normalization requirement is obtained after the addition operation.

The floating-point multiplier-adder provided by this embodiment is optimized in terms of circuit structure. By setting at least two floating-point part multipliers 1 and one multi-input adder 2, the floating-point part multiplier 1 only includes a sign bit XOR circuit 11 , the mantissa multiplier 12 and the exponent adder 13 do not include a normalization module, receive the normalized floating-point number and enter the output non-normalized floating-point number after the multiplication operation is carried out by the adder and output the normalized floating-point number, from In terms of hardware circuit, the floating-point multiplier-accumulator is optimized and the operation efficiency of the floating-point multiplier-accumulator is improved, and the area and power consumption of the hardware circuit are reduced.

On the basis of the above embodiments, further, the adder includes: an exponent comparator, a mantissa shifter, a rounding module and a normalization module, so as to accumulate the input non-normalized floating-point numbers and output a normalized convert floating-point numbers.

Specifically, the non-normalized floating-point number output by the floating-point multiplier is used as the input of the multi-input adder, wherein the exponent part of the input non-normalized floating-point number first passes through the exponent comparator to compare the input non-normalized number according to the comparison result. The normalized mantissa is aligned by the mantissa shifter, and then accumulated by the fixed-point adder. After the accumulated result is passed through the rounding module, it is then normalized by the normalization module, and then the normalized floating-point number can be output.

The floating-point multiplier-adder provided by the embodiment of the present invention uses the floating-point part of the multiplier to perform multiplication calculation on the input normalized floating-point number, and inputs the obtained non-normalized floating-point number into the multi-input adder, and then passes through the multi-input adder. The exponent comparator, mantissa shifter, rounding module and normalization module accumulate the input non-normalized floating-point numbers and output normalized floating-point numbers, and reduce hardware costs by optimizing floating-point multiplication calculations at the circuit level. Therefore, the operation efficiency is improved, the extra normalization overhead is reduced, and the power consumption is reduced.

On the basis of the above embodiments, further, the rounding mechanism of the rounding module in the adder includes: truncated rounding, upward rounding, downward rounding or nearest rounding.

Specifically, truncation rounding, up rounding, down rounding and nearest rounding are four different data processing modes for rounding data. For the convenience of description, we use the decimal numbers 0.4, 0.5, 0.6, 1.5, 2.4 and 2.5 to illustrate the results of rounding for these four rounding methods.

Table 1 Example of data processing results with different rounding methods

Table 1 is an example of the results of data processing by different rounding methods. As shown in Table 1, the truncation rounding method is to completely round off the data after the decimal point and only keep the numbers before the decimal point. This rounding method is very important in circuit implementation. Being simple, it can effectively reduce the difficulty of circuit design, improve calculation efficiency and reduce circuit power consumption, but its calculation accuracy is relatively low, and it is suitable for calculation scenarios with low precision requirements. The three methods of rounding up, rounding down and nearest rounding are all rounding. The difference lies in the treatment of five. Rounding up is to calculate the carry of five to a larger number. 0.5 is rounded up Rounding up becomes 1, 1.5 is rounded up to 2, and so on, so I won’t go into details here; rounding down is to round off the five to smaller numbers, 0.5 becomes 0 after rounding down, 1.5 After being rounded down, it becomes 1, and so on, so I won’t go into details here; the nearest rounding becomes even rounding, which is to round five to the nearest even number, for example, 0.5 is between 0 and 1, where 0 is an even number, so 0.5 becomes 0 after the nearest rounding, 1.5 is between 1 and 2, and 2 is an even number, so 1.5 becomes 2 after the nearest rounding, similarly, 2.5 becomes 2 after the nearest rounding, and 3.5 passes through The nearest rounding becomes 4, and so on, which will not be repeated here. Due to the different processing methods for five, the data processed by the three rounding methods of rounding up, rounding down and nearest rounding also have their own characteristics in terms of errors: rounding up calculates the carry of five to a larger number, Therefore, the data will be shifted upwards as a whole; rounding down will round off five to a smaller number, so the data will be shifted downwards as a whole; and the most recently rounded data will round up the number whose integer part is an odd number , the number whose integer part is an even number is rounded down, thus reducing the data deviation caused by the rounding method as a whole and improving the accuracy of the data, but from the circuit design point of view, the circuit design of the nearest rounding is as complicated as The rounding method can be reasonably selected under different precision requirements.

The floating-point multiplier-adder provided in this embodiment includes multiple rounding mechanisms, which can reduce the difficulty of circuit design on the basis of meeting the requirements of different operations, and improve the efficiency and precision of operations.

On the basis of the above embodiment, further, the exponent comparator finds the largest exponent value in the input data, and the mantissa shifter performs a shift operation according to the largest exponent value to align the mantissa bits.

Specifically, the input normalized floating-point number is multiplied by the floating-point multiplier and the output non-normalized floating-point number is used as the input of the multi-input adder, wherein the exponent part of the input non-normalized floating-point number is first The maximum exponent value is obtained through the exponent comparator, and then the maximum exponent value is subtracted from each input exponent to obtain the offset. The decimal point of the mantissa value is shifted to the left according to the offset. The position of the decimal point on the circuit is fixed. Therefore, the mantissa part of each input is shifted to the right by the mantissa shifter according to the offset to complete the mantissa alignment requirement. Then the fixed-point adder is used for accumulation, and the result obtained by the accumulation is processed by the rounding module and then normalized by the normalization module, so that the normalized floating-point number can be output.

Here, the exponent comparator is used to obtain the largest exponent value in each input, and then the mantissa is aligned according to the difference between the largest exponent value and each exponent value, so that the exponent part of the result is determined to be the largest exponent value, and the mantissa is aligned and then added. The corresponding mantissa value is obtained, and the fixed-point adder can be directly used when adding the mantissa, which further improves the operation efficiency.

On the basis of the above embodiments, further, the adder further includes a systolic register for storing the results of the mantissa shifter and the exponent comparator, so as to increase the pipeline of the adder.

The operation of the convolutional neural network is composed of a large number of continuous multiplication and addition, so the operation efficiency of the floating-point multiply-adder is also affected by the operation frequency. In the floating-point multiplier-adder provided by the embodiment of the present invention, a pulse register is added in the multi-input adder to store the results of the mantissa shifter and the exponent comparator, and multiple normalized floating-point numbers input each time are passed through the floating-point Part of the multiplier-adder becomes a non-normalized floating-point number input multi-input adder after multiplication. After passing through the exponent comparator in the multi-input adder, the comparison result is stored in the pulse register, and then passed through the mantissa shifter. The shifted mantissa is stored in the corresponding pulse register, so that these data are stored in the pulse register, and the floating-point multiplier can receive the next batch of inputs to start a new round of operations, while the pulse register The data then continue to perform the next operation, enter the rounding module for rounding operation, and then enter the normalization module for normalization operation to output a normalized floating point number.

By adding a pulse register in the adder to store the results of the mantissa shifter and the exponent comparator, the frequency of operation can be effectively increased, thereby improving the overall operation efficiency.

On the basis of the above embodiments, further, the normalization module performs normalization processing on the calculation result at the end of the adder operation.

As mentioned above, the floating-point multiply-accumulator in the prior art uses continuous multiplication and addition to perform floating-point operations, and the result of each operation is a normalized floating-point number. The floating-point multiply-accumulator provided by the embodiment of the present invention removes the For all the normalization modules in the intermediate links, only the normalization module at the end of the adder is reserved, so that the multiplication and addition operations in the entire operation process are fixed-point operations, which greatly reduces the complexity of calculations and improves operation efficiency. Adding a normalization module at the end ensures that the output is a standard normalized floating-point number.

Fig. 3 is a schematic structural diagram of a sixteen-input floating-point multiplier-adder provided by an embodiment of the present invention, and Fig. 4 is a schematic structural diagram of an eight-input adder in a sixteen-input floating-point multiplier-accumulator provided by an embodiment of the present invention, as shown in Fig. 3 and Fig. 4, the multiplier-adder includes eight floating-point partial multiplier-adders 301 and one eight-input adder 302.

The floating-point part multiplier consists of a mantissa multiplier and an exponent adder, and includes an XOR circuit for the sign bit. The output of the floating-point part of the multiplier consists of the unnormalized mantissa, exponent, and sign bit, and is used as the input of the multiple-input adder. The eight-input adder includes: an exponent comparator 401, a mantissa shifter 402, a pulse register 403, a rounding module 404, a normalization module 405, and the like. During the implementation, the eight-input adder can choose the rounding method implemented internally according to the work needs.

When working, the output of the multiplier of the floating-point part of the upper stage is used as an input to the eight-input adder. The 8 exponents first pass through the exponent comparator to generate the value of the maximum exponent, and then subtract the maximum value of the exponent from each input exponent to obtain different offsets. Then, the mantissa part is shifted to the right according to the offset to complete the requirement of mantissa alignment. The aligned mantissas are then passed through the mantissa summation circuit to calculate the sum. Finally, the normalized final result is obtained through the normalization module.

The floating-point multiply-accumulator provided by the embodiment of the present invention has eight floating-point partial multiply-accumulators and an eight-input adder. floating-point numbers, and by adding the pulse register 403 to realize two-stage pipeline, which improves the operation frequency, reduces the overall circuit area, reduces power consumption, and improves operation efficiency.

Fig. 5 is a schematic flow chart of a floating-point multiplication and addition calculation method provided by an embodiment of the present invention. As shown in Fig. 5, the method includes:

Step 10, receiving at least four normalized floating-point number inputs;

Step 20, performing a multiplication operation on the normalized floating-point number to obtain a non-normalized floating-point number;

Step 30: Perform an addition operation on the non-normalized floating-point numbers to obtain a normalized floating-point number.

Specifically, first introduce the normalized floating-point number input, and then perform the multiplication operation on the received normalized floating-point number, but do not perform normalization processing during the multiplication operation, and directly use the non-normalized floating-point number to perform the addition operation , after the addition operation is completed, normalization processing is performed to obtain a standard normalized floating-point number. Since the normalization process is only performed at the end in the operation process, the step of normalizing the multiplication operation is saved, thereby improving the calculation efficiency.

On the basis of the above embodiments, further, the step of obtaining the non-normalized floating-point number is specifically:

Passing the sign bit of the normalized floating-point number through a signed XOR circuit to obtain the sign bit of the non-normalized floating-point number;

Passing the mantissa bits of the normalized floating-point number through a mantissa multiplier to obtain the unnormalized mantissa bits of the non-normalized floating-point number;

Passing the exponent of the normalized floating-point number through an exponent adder to obtain the exponent of the non-normalized floating-point number;

Output the unnormalized floating-point number composed of the sign bit, unnormalized mantissa bits and exponent bits.

Floating-point numbers are composed of three parts: sign bit, mantissa bit and exponent bit. Floating-point number multiplication operation is: perform XOR operation on the sign bit, the same sign is positive and the different sign is negative; multiply the mantissa bits; and then add the exponent bits . Therefore, after receiving the normalized floating-point number of input, the sign bit of said floating-point number is carried out to XOR operation by using an XOR circuit to obtain a new sign; Multiply to obtain a new mantissa; use the exponent adder to add the exponent bits of the normalized floating-point number to obtain a new exponent. After the mantissa is multiplied, the obtained mantissa may not meet the normalization requirements, so it is called a non-normalized mantissa. A floating-point number consisting of a new sign, mantissa, and exponent is called a non-normalized floating-point number. The obtained non-normalized floating-point number is used as the input of the multi-input adder, and the normalized floating-point number conforming to the standard is obtained after the addition operation.

The method provided by the embodiment of the present invention improves the efficiency of floating-point multiplication and addition calculation by simplifying the normalization step in the multiplication operation of the normalized floating-point number and outputting the normalized floating-point number after the addition operation.

On the basis of the above embodiments, further, the step of adding the non-normalized floating-point numbers to obtain the normalized floating-point numbers is specifically:

receiving all said denormalized floating point numbers;

Compare the exponents of each unnormalized floating-point number to obtain the largest exponent;

Making a difference between the largest exponent and the exponents of each non-normalized floating-point number to obtain the offset of each non-normalized floating-point number;

Aligning the mantissas of the non-normalized floating-point numbers according to the offset;

Perform signed summation of each unnormalized mantissa after the alignment to obtain a sum;

The sum and the exponent are passed through a rounding module and a normalization module to obtain a normalized floating point number for output.

After multiplication, the received normalized floating-point numbers become non-normalized floating-point numbers and continue to perform addition operations. When performing addition operations: first receive all non-normalized floating-point numbers; The exponent bits are compared to obtain the largest exponent; then the largest exponent is subtracted from each exponent, and the difference obtained by the subtraction is the offset of the mantissa of each non-normalized floating-point number; according to the offset, the The mantissa part of each non-normalized floating-point number is shifted and aligned; and then each aligned non-normalized mantissa is subjected to a signed addition operation to obtain a sum; the obtained sum may not meet the normalization requirements, so It is also necessary to go through the rounding module and the normalization module to make the result meet the normalization requirements, and obtain a normalized floating-point number for output.

The method provided by the embodiment of the present invention simplifies the normalization step in the multiplication operation of normalized floating-point numbers. In the addition operation, first calculates the offset by comparing the exponent bits to shift and align the mantissa bits, and then aligns the aligned Signed addition is performed on the mantissa bits, and then the obtained sum and exponent bits are passed through a rounding module and a normalization module to obtain a normalized floating-point number that meets the regulations, which improves the efficiency of floating-point multiplication and addition calculations.

The device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative efforts.

Through the above description of the implementations, those skilled in the art can clearly understand that each implementation can be implemented by means of software plus a necessary general hardware platform, and of course also by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, magnetic discs, optical discs, etc., including several instructions to make a computer device (which may be a personal computer, server, or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. An improved floating-point multiply-adder, comprising at least two floating-point part multipliers and a multi-input adder, is characterized in that, said floating-point part multiplier is composed of sign bit XOR circuit, mantissa multiplier and Composed of an exponential adder, the floating-point multiplier receives normalized floating-point numbers and performs multiplication calculations to obtain non-normalized floating-point numbers, and the adder accumulates the non-normalized floating-point numbers and outputs normalized floating-point numbers Point number, the non-normalized floating-point number is composed of a sign bit, a non-normalized mantissa and an exponent part, and the normalized floating-point number is composed of a sign bit, a normalized mantissa and an exponent part. 2. The multiply-adder according to claim 1, wherein the adder comprises: an exponent comparator, a mantissa shifter, a rounding module and a normalization module, so that the input non-normalized floating Points are accumulated and output as a normalized floating point number. 3. The multiply-adder according to claim 2, wherein the rounding mechanism of the rounding module in the adder comprises: truncated rounding, upward rounding, downward rounding or nearest rounding. 4. The multiply-adder according to claim 2, wherein the exponent comparator finds the maximum exponent value in the input data, and the mantissa shifter performs a shift operation according to the maximum exponent value Align the mantissa bits. 5 . The multiply-adder according to claim 2 , wherein the adder further comprises a systolic register for storing the results of the mantissa shifter and the exponent comparator, so as to increase the pipeline of the adder. 6. The multiplier-adder according to any one of claims 2 to 5, wherein the normalization module performs normalization processing on calculation results at the end of the operation of the adder. 7. The multiply-adder according to claim 6, wherein the multiply-adder comprises eight floating-point partial multiply-adders and one eight-input adder. 8. A floating point multiplication and addition calculation method, characterized in that, comprising: Receives at least four normalized floating point inputs; performing a multiplication operation on the normalized floating-point number to obtain a non-normalized floating-point number; The non-normalized floating-point numbers are added to obtain the normalized floating-point numbers. 9. method according to claim 8, is characterized in that, described normalized floating-point number is carried out multiplication operation, the step that obtains non-normalized floating-point number is specifically: Passing the sign bit of the normalized floating-point number through a signed XOR circuit to obtain the sign bit of the non-normalized floating-point number; Passing the mantissa bits of the normalized floating-point number through a mantissa multiplier to obtain the unnormalized mantissa bits of the non-normalized floating-point number; Passing the exponent of the normalized floating-point number through an exponent adder to obtain the exponent of the non-normalized floating-point number; Output the unnormalized floating-point number composed of the sign bit, unnormalized mantissa bits and exponent bits. 10. The method according to claim 8, wherein the step of adding the non-normalized floating-point number to obtain a normalized floating-point number is specifically: receiving all said denormalized floating point numbers; Compare the exponents of each unnormalized floating-point number to obtain the largest exponent; Making a difference between the largest exponent and the exponents of each non-normalized floating-point number to obtain the offset of each non-normalized floating-point number; Aligning the mantissas of the non-normalized floating-point numbers according to the offset; Perform signed summation of each unnormalized mantissa after the alignment to obtain a sum; Pass the sum and exponent through a normalization module to obtain a normalized floating point number for output.