CN107147286A - Current zero-crossing detection method, circuit and control method of switching power supply inductance - Google Patents

Abstract

The present invention provides a current zero-crossing detection method, circuit and control method of switching power supply inductance, including: obtaining the sampling current of the magnetization voltage and the sampling current of the demagnetization voltage based on the first and second current sampling modules; The voltage generation module generates the first detection voltage proportional to the product of the magnetization voltage and the duty cycle conduction time; based on the second detection voltage generation module, the first detection voltage is proportional to the product of the magnetization voltage and the duty cycle conduction time. A voltage and a second voltage proportional to the product of the demagnetization voltage and the cut-off time of the duty ratio; based on the dead zone pulse generation circuit, the current zero crossing point and the dead zone are detected. The invention indirectly samples the inductor current zero-crossing signal through the volt-second balance principle, avoids the processing of small signals, forms a control circuit, and solves the problem of current backflow; at the same time, the sampling resistor on the system is omitted; it not only improves the efficiency of the system, but also simplifies Improve the system solution of the power system and improve the competitiveness of the product.

Description

Current zero-crossing detection method, circuit and control method of switching power supply inductance

technical field

The invention relates to the field of semiconductor integrated circuits, in particular to a current zero-crossing detection method, circuit and control method for switching power supply inductance.

Background technique

With the rapid development of electronic technology, electronic products have more and more functions, more and more types, and more and more application fields, requiring more and more power consumption. At present, my country produces more than 100 million electronic products such as mobile phones, personal computers, servers, large-screen smart TVs, network communications, and high-power LED lighting every year, and the core components of these electronic products --- switching power supply, it is necessary to provide a larger power output. High power density, high conversion efficiency, high power factor and low standby power consumption are a basic trend in the development of switching power supplies; intelligentization, miniaturization and low cost, and gradual improvement of system integration are another trend in the development of switching power supplies , the traditional switching power supply control structure has been difficult to meet these requirements. This will inevitably force us to adopt new technologies to make switching power supply products as efficient as possible, with as few peripheral components as possible, and as low as possible in standby power consumption, in order to meet increasingly stringent international standards.

International power supply standards are becoming more and more strict on the average efficiency of power supply products and the energy efficiency level in standby power consumption. Compared with the V standard (87%, 0.1W), the American energy efficiency VI standard has increased to an average efficiency of 88%, and the higher standard of standby power consumption is 0.1W, which has caused a major impact on power supply manufacturers. Conform to the trend of green, environmental protection and energy saving.

During the working process of the switching power supply, if the current in the inductor is not completely released during the switching process, it belongs to the continuous current mode (CCM); if the current in the inductor is completely released and recharged after a period of time, it belongs to the discontinuous mode ( DCM); if the current in the inductor is fully discharged and then charged immediately, it is a critical mode. The optimal switching power supply chip design should be compatible with these three control modes, so that the load can vary in a wide range.

Figure 1 is a schematic diagram of the system structure of traditional AC/DC asynchronous control, and Figure 2 is a schematic diagram of the system structure of traditional DC/DC asynchronous control. The use of diode Diode as a switch in the two circuits can save the zero crossing The detection circuit reduces the design difficulty of the chip circuit. However, the use of the diode Diode greatly reduces the efficiency of the system, especially when the output voltage is relatively low, it can lose more than 10% of the efficiency, and it is difficult to meet the international energy efficiency standards.

In order to improve energy efficiency, synchronous control is generally used at present. As shown in Figure 3, the power tube Mp is used as a switch to replace the diode Diode in Figure 2. During the current demagnetization stage of the inductor L0, when the inductor current discharges to zero but the demagnetization time has not yet ended, the output voltage Vout will appear -power tube Mp-inductor L0-inverting current of input voltage VIN. The solution to the current inversion is usually to integrate a zero-crossing detection circuit inside the chip. When the inductor current is detected to be zero-crossing, the power tube Mp is controlled to turn off, thereby blocking the DC path of the inversion current. The traditional zero-crossing detection method is to determine the zero-crossing moment of the inductor current by detecting the relative change between the node voltage Vsw and the output voltage Vout, that is, in the demagnetization stage of the inductor current, when the node voltage Vsw is lower than the output voltage Vout, it is judged that the inductor current is too high. zero. However, the disadvantage of this method is that when the on-resistance R _{ON_P} of the power transistor Mp is designed to be small, it is difficult for the comparator to accurately determine the relative changes of Vsw and Vout. For example, when the on-resistance R _{ON_P} of the power transistor Mp is designed to be 20mΩ, when the inductor current changes within the range of ±50mA, the relative change value of the node voltage Vsw is 10mV, but the random mismatch voltage of the common comparator is It will reach more than 20mV, and due to the delay of judgment, there will still be a certain amount of backflow current, as shown in Figure 4.

Figure 5 shows a commonly used source-driven zero-crossing detection circuit. This method detects whether the current in the inductor L0 is too high by detecting the voltage V _SENSE across a small resistor Rs connected in series with the inductor L0. zero. Due to the large switching noise in the switching power supply circuit, the judgment of a small voltage difference is likely to cause misjudgment, and at the same time, there is a delay in judgment in the control circuit, which will also generate a certain amount of backflow current. Backflow current not only affects the efficiency of the system, but also causes certain safety hazards in the system.

Therefore, how to solve the problem of current backflow and improve the efficiency and safety of the switching power supply circuit has become one of the problems to be solved urgently by those skilled in the art.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a current zero-crossing detection method, circuit and control method for switching power supply inductors, which are used to solve the problems of low efficiency and Poor safety performance and other issues.

In order to achieve the above purpose and other related purposes, the present invention provides a current zero-crossing detection method for switching power supply inductors. The current zero-crossing detection method for switching power supply inductors at least includes:

Based on the principle of volt-second balance, the magnetization energy and demagnetization energy of the inductor current in one switching cycle are detected, and the magnetization energy is compared with the demagnetization energy. When the magnetization energy is equal to the demagnetization energy, the The current of the inductor crosses zero;

Wherein, the magnetization energy is the product of the magnetization voltage and the magnetization time, and the demagnetization energy is the product of the demagnetization voltage and the demagnetization time.

Preferably, the current zero-crossing detection method of the switching power supply inductor further includes:

During the on-time of the duty ratio, the first capacitor is charged with twice the sampling current of the line voltage, and the second capacitor is charged with the sampling current of the line voltage at the same time;

charging the second capacitor with the sampling current of the difference between the line voltage and the output voltage during the cut-off time of the duty cycle;

Comparing the voltage on the first capacitor with the voltage on the second capacitor, when the voltage on the first capacitor is equal to the voltage on the second capacitor, the current of the switching power supply inductor crosses zero; when the When the voltage on the first capacitor is lower than the voltage on the second capacitor, the inductor of the switching power supply enters a dead zone.

More preferably, when the inductor current is in a continuous mode, the cut-off time of the duty cycle is the demagnetization time.

More preferably, when the inductor current is in discontinuous mode, the cut-off time of the duty cycle is the sum of the demagnetization voltage and the dead time.

In order to achieve the above purpose and other related purposes, the present invention provides a current zero-crossing detection and control method of a switching power supply. The current zero-crossing detection and control method of a switching power supply at least includes:

Obtain the line voltage and output voltage of the synchronous switching power supply circuit, detect the zero-crossing point and the dead zone time of the inductor current in the synchronous switching power supply circuit based on the above method, and output the dead zone pulse signal;

The power switch tube in the synchronous switching power supply circuit is turned off under the control of the dead zone pulse signal, so as to avoid current backflow.

Preferably, the delay time of the power switch transistor is reduced by increasing the gate driving capability of the power switch transistor.

Preferably, by configuring circuit parameters, the dead-zone pulse signal occurs ahead of a set time, and the set time is not less than the delay time of the power switch tube.

In order to achieve the above purpose and other related purposes, the present invention provides a current zero-crossing detection circuit for switching power supply inductors. The current zero-crossing detection circuit for switching power supply inductors at least includes:

The first current sampling module is used to obtain the sampling current of the magnetization voltage, which is recorded as the first sampling current, and the magnetization voltage is the line voltage;

The second current sampling module is used to obtain the sampling current of the demagnetization voltage, which is recorded as the second sampling current, and the demagnetization voltage is the difference between the line voltage and the output voltage;

The first detection voltage generation module is connected to the output terminal of the first current sampling module, and receives a duty ratio conduction signal, and is used to generate a first detection voltage, and the first detection voltage is related to the magnetization voltage and the magnetization voltage and The product of the on-time of the duty cycle is proportional to;

The second detection voltage generation module is connected to the output terminals of the first current sampling module and the second current sampling module, and receives a duty cycle on signal and a duty cycle off signal, respectively generates the magnetizing A first voltage proportional to the product of the voltage and the on-time of the duty cycle and a second voltage proportional to the product of the demagnetization voltage and the off-time of the duty cycle, the first voltage and the second voltage superposition to generate a second detection voltage;

A dead zone pulse generation circuit, connected to the output terminals of the conduction voltage detection module and the cut-off voltage detection module, compares the first detection voltage and the second detection voltage to obtain the magnetization voltage and the difference between the product of the on-time of the duty cycle and the product of the demagnetization voltage and the off-time of the duty cycle, and output a dead zone pulse signal when the first detection voltage is less than the second detection voltage .

Preferably, the first current sampling module receives a line voltage sampling signal, and converts the line voltage sampling signal into a current signal through a first resistor.

More preferably, the first current sampling module includes: a first resistor, a first voltage follower, a first PMOS transistor, and a second PMOS transistor;

The first voltage follower receives a sampling signal of the line voltage;

One end of the first resistor is grounded, and the other end is connected to the first output end of the first voltage follower;

The drain terminal of the first PMOS transistor is connected to the second output terminal of the first voltage follower, the gate terminal is connected to the bias voltage, and the source terminal is connected to the drain terminal of the second PMOS transistor;

The source end of the second PMOS transistor is connected to a power supply, and the gate end is connected to the drain end of the first PMOS transistor as an output end of the first current sampling module.

Preferably, the second current sampling module receives the sampling signal of the line voltage and the sampling signal of the output voltage, and calculates the difference between the sampling signal of the line voltage and the sampling signal of the output voltage in the second The resistance is converted into a current signal.

More preferably, the second current sampling module includes: a second voltage follower, a third voltage follower, a second resistor, a third PMOS transistor, and a fourth PMOS transistor;

The second voltage follower receives a sampling signal of the line voltage;

The third voltage follower receives a sampling signal of the output voltage;

The second resistor is connected between the output terminal of the second voltage follower and the output terminal of the third voltage follower;

The drain terminal of the third PMOS transistor is connected to the output terminal of the third voltage follower, the gate terminal is connected to the bias voltage, and the source terminal is connected to the drain terminal of the fourth PMOS transistor;

The source terminal of the fourth PMOS transistor is connected to a power supply, and the gate terminal is connected to the drain terminal of the third PMOS transistor as an output terminal of the second current sampling module.

Preferably, the first detection voltage generation module uses the first sampling current to charge a first capacitor within the on-time of the duty ratio to obtain the first detection voltage.

More preferably, the first detection voltage generation module includes: a first capacitor, a first switch, a fifth PMOS transistor, and a sixth PMOS transistor;

The lower plate of the first capacitor is grounded, and the upper plate is connected to one end of the first switch;

The other end of the first switch is connected to the drain end of the fifth PMOS transistor, and the first switch is closed under the control of the duty cycle conduction signal;

The source end of the fifth PMOS transistor is connected to the drain end of the sixth PMOS transistor, and the gate end is connected to a bias voltage;

A source terminal of the sixth PMOS transistor is connected to a power supply, and a gate terminal is connected to an output terminal of the first current sampling module.

Preferably, the second detection voltage generation module uses the first sampling current to charge the second capacitor during the on-time of the duty ratio, and uses the second sampling current to charge the second capacitor during the off-time of the duty ratio. The second capacitor is charged, and the second detection voltage is obtained by superposition of two charging voltages.

More preferably, the second detection voltage generation module includes: a second capacitor, a second switch, a seventh PMOS transistor, an eighth PMOS transistor, a third switch, a ninth PMOS transistor, and a tenth PMOS transistor;

The lower plate of the second capacitor is grounded, and the upper plate is respectively connected to one end of the second switch and the third switch;

The other end of the second switch is connected to the drain end of the seventh PMOS transistor, and the second switch is closed under the control of the duty cycle conduction signal;

The source end of the seventh PMOS transistor is connected to the drain end of the eighth PMOS transistor, and the gate end is connected to a bias voltage;

The source terminal of the eighth PMOS transistor is connected to a power supply, and the gate terminal is connected to the output terminal of the first current sampling module;

The other end of the third switch is connected to the drain end of the ninth PMOS transistor, and the third switch is closed under the control of the duty ratio cut-off signal;

The source end of the ninth PMOS transistor is connected to the drain end of the tenth PMOS transistor, and the gate end is connected to the bias voltage;

A source terminal of the tenth PMOS transistor is connected to a power supply, and a gate terminal is connected to an output terminal of the second current sampling module.

Preferably, the dead zone pulse generating circuit includes a comparator, an AND gate and a flip-flop;

The first input terminal of the comparator is connected to the first detection voltage, and the second input terminal is connected to the second detection voltage;

The first input end of the AND gate is connected to the output end of the comparator, and the second input end is connected to the duty cycle cut-off signal;

The input end of the flip-flop is connected to a high level, and the clock end is connected to the output end of the AND gate.

Preferably, the output terminals of the first detection voltage generation module and the second detection voltage generation module are respectively connected to a reset transistor to reset the first detection voltage and the second detection voltage to zero.

As mentioned above, the current zero-crossing detection method, circuit and control method of the switching power supply inductor of the present invention have the following beneficial effects:

The current zero-crossing detection method, circuit and control method of the switching power supply inductance of the present invention indirectly sample the inductance current zero-crossing signal through the volt-second balance principle, avoiding the processing of small signals, forming a control circuit, and solving the problem of current backflow; Remove the sampling resistor on the system; it not only improves the efficiency of the system, but also simplifies the system solution of the power system and improves the competitiveness of the product.

Description of drawings

Fig. 1 is a schematic diagram of the system structure of AC/DC asynchronous control in the prior art.

Fig. 2 is a schematic structural diagram of a DC/DC asynchronous control system in the prior art.

Fig. 3 is a schematic structural diagram of a DC/DC synchronous control system in the prior art.

FIG. 4 is a schematic diagram of the timing sequence of the current pouring in the prior art.

FIG. 5 is a schematic structural diagram of a source-driven zero-crossing detection circuit in the prior art.

FIG. 6 is a schematic diagram of a current zero-crossing detection circuit for switching power supply inductors of the present invention.

FIG. 7 is a schematic diagram of the waveforms of the first detection voltage and the second detection voltage in the continuous mode of the present invention.

FIG. 8 is a schematic diagram of waveforms of the first detection voltage and the second detection voltage in the discontinuous mode of the present invention.

FIG. 9 is a simulation waveform diagram of node signals of the zero-crossing detection circuit of the present invention in discontinuous mode.

FIG. 10 is a simulation waveform diagram of node signals of the zero-crossing detection control system of the present invention in intermittent mode.

Component designation description

1 Current zero-crossing detection circuit of switching power supply inductor

11 The first current sampling module

111 First voltage follower

1111 First Amplifier

12 The second current sampling module

121 Second voltage follower

1211 Second Amplifier

122 Third voltage follower

1221 Third Amplifier

13 The first detection voltage generation module

14 The second detection voltage generation module

15 Dead zone pulse generating circuit

151 Comparators

152 First NOT gate

153 NAND gate

154 Second NOT gate

155 triggers

16 Third Inverter

S1～S6 steps

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 6 to Figure 10. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

As shown in FIG. 6 , the present invention provides a current zero-crossing detection circuit 1 of a switching power supply inductor, and the current zero-crossing detection circuit 1 of the switching power supply inductor at least includes:

The first current sampling module 11 , the second current sampling module 12 , the first detection voltage generation module 13 , the second detection voltage generation module 14 and the dead zone pulse generation circuit 15 .

As shown in FIG. 6 , the first current sampling module 11 is used to acquire a sampling current of a magnetization voltage, denoted as a first sampling current I _C1 , and the magnetization voltage is a line voltage V _IN .

Specifically, in this embodiment, the first current sampling module 11 includes: a first resistor R1, a first voltage follower 111, a first PMOS transistor _MP1 and a second _PMOS transistor MP2. The first voltage follower 111 includes a first amplifier 1111 and an NMOS transistor M _N0 , the non-inverting input terminal of the first amplifier 1111 receives the sampling signal V _INS of the line voltage V _IN , and the inverting input terminal is connected to the The source end and the output end of the NMOS transistor M _N0 are connected to the gate end of the NMOS transistor M _N0 ; one end of the first resistor R1 is grounded, and the other end is connected to the source end of the NMOS transistor M _N0 ; through the line voltage V The sampling signal V _INS of _IN controls the gate terminal of the NMOS transistor M _N0 to obtain the first sampling current I _C1 . The drain terminal of the first PMOS transistor M _P1 is connected to the drain terminal of the NMOS transistor M _N0 , the gate terminal is connected to the bias voltage V _B , and the source terminal is connected to the drain terminal of the second PMOS transistor _MP2 ; The source end of the _PMOS transistor MP2 is connected to the power supply, and the gate end is connected to the drain end of the first _PMOS transistor MP1 as the output end of the first current sampling module 11; the first sampling current I _C1 passes through the first Two PMOS tube M _P2 output. Any circuit structure capable of converting a line voltage sampling signal into a current signal is applicable to the first current sampling module 11 of the present invention, and is not limited to this embodiment.

As shown in FIG. 6 , the second current sampling module 12 is used to obtain the sampling current of the demagnetization voltage, denoted as the second sampling current I _C2 , and the demagnetization voltage is the difference between the line voltage V _IN and the output voltage V _O.

Specifically, in this embodiment, the second current sampling module 12 includes: a second voltage follower 121, a third voltage follower 122, a second resistor R2, a third PMOS transistor _MP3 , and a fourth PMOS transistor M _P4 . The second voltage follower 121 includes a second amplifier 1211, the non-inverting input terminal of the second amplifier 1211 receives the sampling signal V _INS of the line voltage V _IN , and the inverting input terminal is connected to the The output end is then connected to one end of the second resistor R2. The third voltage follower 122 includes a third amplifier 1221, the non-inverting input terminal of the third amplifier 1221 receives the sampling signal V _OS of the output voltage V _O , and the inverting input terminal is connected to the third amplifier 1221. The output end is then connected to the other end of the second resistor R2. The difference between the sampling signal V _INS of the line voltage V _IN and the sampling signal V _OS of the output voltage V _O is formed at both ends of the second resistor R2 and converted into the second sampling current I _C2 . The drain terminal of the third PMOS transistor _MP3 is connected to the output terminal of the third voltage follower 122, the gate terminal is connected to the bias voltage V _B , and the source terminal is connected to the drain terminal of the fourth PMOS transistor _MP4 ; The source end of the fourth PMOS transistor _MP4 is connected to the power supply, and the gate end is connected to the drain end of the third PMOS transistor _MP3 as the output end of the second current sampling module 12; the second sampling current I _C2 passes through the Describe the output of the fourth PMOS transistor _MP4 . Any circuit structure that can convert the difference between the line voltage sampling signal and the output voltage sampling signal into a current signal is applicable to the second current sampling module 12 of the present invention, and is not limited to this embodiment.

As shown in FIG. 6, the first detection voltage generation module 13 is connected to the output end of the first current sampling module 11, and receives a duty cycle turn-on signal T _ON for generating the first detection voltage V _S1 , The first detection voltage V _S1 is directly proportional to the product of the magnetization voltage and the on-time of the duty cycle.

Specifically, in this embodiment, the first detection voltage generation module 13 includes: a first capacitor C _S1 , a first switch S1 , a fifth PMOS transistor _MP5 , a sixth PMOS transistor _MP6 and a first reset transistor M _S1 . The lower plate of the first capacitor C _S1 is grounded, the upper plate is connected to one end of the first switch S1; the other end of the first switch S1 is connected to the drain end of the fifth _PMOS transistor MP5, the The first switch S1 is closed under the control of the duty ratio conduction signal T _ON ; the source terminal of the fifth _PMOS transistor MP5 is connected to the drain terminal of the sixth PMOS transistor _MP6 , and the gate terminal is connected to the bias voltage V _B ; the source terminal of the sixth PMOS transistor _MP6 is connected to the power supply, and the gate terminal is connected to the output terminal of the first current sampling module 11; the first reset transistor M _S1 is connected to the top of the first capacitor C _S1 plate, in this embodiment, the first reset transistor M _S1 is an NMOS transistor. Any circuit capable of realizing the product of the magnetizing voltage and the on-time of the duty ratio is suitable for the first detection voltage generating module 13 of the present invention, and is not limited to this embodiment.

As shown in FIG. 6, the second detection voltage generation module 14 is connected to the output terminals of the first current sampling module 11 and the second current sampling module 12, and receives the duty cycle turn-on signal T _ON and duty cycle. Duty ratio cut-off signal respectively generate a first voltage V1 proportional to the product of the magnetization voltage and the on-time of the duty ratio and a second voltage V2 proportional to the product of the demagnetization voltage and the off-time of the duty ratio, the The first voltage V1 and the second voltage V2 are superimposed to generate a second detection voltage V _S2 .

Specifically, in this embodiment, the second detection voltage generating module 14 includes: a second capacitor CS2, a second switch _S2 , a seventh PMOS transistor _MP7 , an eighth PMOS transistor _MP8 , a third switch S3, The ninth PMOS transistor _MP9 , the tenth PMOS transistor _MP10 and the second reset transistor M _S2 . The lower plate of the second capacitor CS2 is grounded, and the upper plate is respectively connected to one end of the second switch _S2 and the third switch S3; the other end of the second switch S2 is connected to the seventh PMOS transistor The drain end of _MP7 , the second switch S2 is closed under the control of the duty ratio conduction signal T _ON ; the source end of the seventh PMOS transistor _MP7 is connected to the drain end of the eighth PMOS transistor _MP8 The gate terminal is connected to the bias voltage V _B ; the source terminal of the eighth PMOS transistor _MP7 is connected to the power supply, and the gate terminal is connected to the output terminal of the first current sampling module 11; the other terminal of the third switch S3 connected to the drain end of the ninth PMOS transistor _MP9 , the third switch S3 receives the duty cycle cut-off signal The control of the ninth PMOS transistor _MP9 is connected to the drain terminal of the tenth PMOS transistor _MP10 , and the gate terminal is connected to the bias voltage _VB ; the source terminal of the tenth PMOS transistor _MP10 Connect the power supply and the gate end to the output end of the second current sampling module 12; the second reset transistor M _S2 is connected to the upper plate of the second capacitor _CS2 . In this embodiment, the second The reset transistor _MS2 is an NMOS transistor. The voltage on the second capacitor _{CS2 is the sum of the first voltage V1 and the second voltage V2, which is the second detection voltage V S2 .} Any circuit that can realize the sum of the product of the magnetization voltage and the on-time of the duty cycle and the product of the demagnetization voltage and the off-time of the duty cycle is applicable to the second detection voltage generating module of the present invention 14. It is not limited to this embodiment.

As shown in FIG. 6, the dead zone pulse generation circuit 15 is connected to the output terminals of the first detection voltage generation module 13 and the second detection voltage generation module 14, and the first detection voltage V _S1 and the The second detection voltage V _S2 is compared to obtain the difference between the product of the magnetization voltage and the on-time of the duty cycle and the product of the demagnetization voltage and the off-time of the duty cycle, when the When the first detection voltage V _S1 is lower than the second detection voltage V _S2 , a dead zone pulse signal T _D is output.

Specifically, in this embodiment, the dead zone pulse generating circuit 15 includes a comparator 151 , a first NOT gate 152 , a NAND gate 153 , a second NOT gate 154 and a flip-flop 155 . The non-inverting input terminal of the comparator 151 is connected to the first detection voltage V _S1 , and the inverting input terminal is connected to the second detection voltage V _S2 , so as to obtain the magnetization voltage and the on-time of the duty cycle The difference between the product of the demagnetization voltage and the product of the duty cycle cut-off time; the first sampling of charging the capacitor in the first detection voltage generation module 13 and the second detection voltage generation module 14 The multiple of the current I _C1 is not limited, and the charging current related to the first sampling current I _C1 in the first detection voltage generation module 13 is one I _C1 larger than that in the second detection voltage generation module 14, and is not limited to charging in this embodiment. The current is twice the setting of I _C1 and single I _C1 , the product (single) of the magnetization voltage and the conduction time of the duty ratio and the demagnetization voltage and The difference of the product (single times) of the duty cycle cut-off time is enough. The first NOT gate 152 is connected to the output terminal of the comparator 151 , and the output terminal of the first NOT gate 152 is equivalent to the inverting output terminal of the comparator 151 . The input ends of the NAND gate 153 are respectively connected to the duty ratio cut-off signal and the output terminal of the first NOT gate 152 . The second NOT gate 154 is connected to the output terminal of the NAND gate 153 , and the NAND gate 153 and the second NOT gate 154 form an AND gate. The input end of the flip-flop 155 is connected to a high level, and the clock end is connected to the output end of the second NOT gate 154. In this embodiment, the flip-flop 155 is a D flip-flop. The polarity relationship between each signal and the device is not limited, and different connection relationships can be realized by adding an inverter, which is not limited to this embodiment. Any circuit structure that can output the dead-zone pulse signal _TD when the first detection voltage V _S1 is lower than the second detection voltage V _S2 is applicable to the dead-zone pulse generation circuit 15 of the present invention, and is not based on this embodiment. example is limited.

The gate terminal of the first reset transistor _MS1 , the gate terminal of the second reset transistor _MS2 and the reset terminal of the flip-flop 155 receive a clock signal clk through the third inverter 16 .

The present invention also provides a current zero-crossing detection and control method for switching power supply inductors. In this embodiment, the current zero-crossing detection and control method for switching power supply inductors is based on the switching power supply inductor current zero-crossing detection circuit 1 and a A synchronous switching power supply circuit, the synchronous switching power supply circuit can be any AC/DC or DC/DC circuit structure in the prior art, which will not be described one by one here, the current zero-crossing detection control method of the switching power supply inductor It includes: detecting the magnetization energy and demagnetization energy of the inductor current in one switching cycle based on the principle of volt-second balance, comparing the magnetization energy with the demagnetization energy, and when the magnetization energy is equal to the demagnetization energy, The current of the inductor crosses zero; wherein, the magnetization energy is the product of the magnetization voltage and the magnetization time, and the demagnetization energy is the product of the demagnetization voltage and the demagnetization time. The volt-second balance principle can be expressed as:

V _IN *T _ON ＝(V _O -V _IN )*T _OFF

Among them, T _ON and T _OFF are the magnetization time and demagnetization time of the inductor current respectively.

Further, include the following steps:

Step S1: Based on the first current sampling module 11 receiving the sampling signal V _INS of the line voltage V _IN , in this embodiment, the sampling signal V _INS of the line voltage V _IN satisfies the following relationship:

In practical applications, the sampling signal V _INS of the line voltage V _IN and the line voltage V _IN may satisfy other proportional relationships, which are not limited to this embodiment.

Then the sampling signal V _INS of the line voltage V _IN is converted into a first sampling current I _C1 , and the first sampling current I _C1 satisfies the following relationship:

Step S2: Based on the second current sampling module 12 receiving the sampling signal V _INS of the line voltage V _IN and the sampling signal V _OS of the output voltage V _O , in this embodiment, the sampling signal of the output voltage V _O The sampling signal V _OS satisfies the following relationship:

In practical applications, the sampling signal V _OS of the output voltage V _O and the output voltage V _O may satisfy other proportional relationships, which are not limited to this embodiment.

Then the difference between the sampling signal V _INS of the line voltage V _IN and the sampling signal V _OS of the output voltage V _O is converted into a second sampling current I _C2 , and the second sampling current I _C2 satisfies the following relationship:

Step S3: When the duty cycle is turned on, the first switch S1 and the second switch S2 are closed, the third switch S3 is opened, and the first detection voltage generation module 13 uses the first sampling current I _C1 charges the first capacitor C _S1 during the on-time of the duty ratio to obtain the first detection voltage V _S1 ; based on the second detection voltage generating module 14, the first sampling current I _C1 is During the on-time of the duty ratio, the second capacitor _CS2 is charged to obtain the first voltage V1.

Specifically, in this embodiment, the fifth PMOS transistor _MP5 and the sixth _PMOS transistor _MP6 form a current mirror structure with the first PMOS transistor _MP1 and the second PMOS transistor MP2. In the example, the current output by the drain terminal of the fifth _PMOS transistor MP5 is twice the first sampling current I _C1 through the setting of device parameters; S1 is closed, and the first capacitor C _S1 is charged with twice the current of the first sampling current I _C1 , then the first detection voltage V _S1 satisfies the following relationship:

Among them, T _ON is the on-time of the duty cycle.

Specifically, in this embodiment, the seventh PMOS transistor _MP7 and the eighth _PMOS transistor _MP8 form a current mirror structure with the first PMOS transistor _MP1 and the second PMOS transistor MP2. In the example, the current output by the drain terminal of the seventh PMOS transistor _MP7 is a single time of the first sampling current I _C1 through the setting of device parameters; during the on-time of the duty cycle, the second switch S2 is closed, and the second capacitor _CS2 is charged with the first sampling current I _C1 to obtain the first voltage V1, then the first voltage V1 satisfies the following relationship:

Step S4: When the duty cycle is cut off, the first switch S1 and the second switch S2 are turned off, the third switch S3 is turned on, and the second detection voltage generation module 14 utilizes the second sampling current I _C2 charges the second capacitor _CS2 within the cut-off time of the duty cycle to obtain the second voltage V2.

Specifically, in this embodiment, the ninth PMOS transistor _MP9 and the tenth PMOS transistor _MP10 form a current mirror structure with the third PMOS transistor _MP3 and the fourth PMOS transistor _MP4 . In the example, the current output by the drain terminal of the ninth PMOS transistor _MP9 is a single time of the second sampling current I _C2 through the setting of device parameters; closed, the second capacitor _CS2 is charged with the second sampling current I _C2 to obtain the second voltage V2, and the second voltage V2 satisfies the following relationship:

in, is the duty cycle cut-off time.

The voltage on the second capacitor _{CS2 is the sum of the first voltage V1 and the second voltage V2, that is, the second detection voltage V S2 , and the second detection voltage V S2 satisfies the} following relationship :

Step S5: comparing the voltage on the first capacitor C _S1 with the voltage on the second capacitor C _S2 based on the dead zone pulse generating circuit 15, when the voltage (V _S1 ) on the first capacitor C _S1 is equal to When the voltage (V _S2 ) on the second capacitor _CS2 , the current of the switching power supply inductor crosses zero; when the voltage (V _S1 ) on the first capacitor _CS1 is smaller than the voltage on the second capacitor _CS2 voltage (V _S2 ), the switching power supply inductor enters the dead zone.

Specifically, the comparator 151 compares the first detected voltage V _S1 and the second detected voltage V _S2 , which in this embodiment is equivalent to obtaining the first detected voltage V _S1 and the second detected voltage V S1 . The difference between the two detection voltages V _S2 satisfies the following relationship:

Assuming that the values of the first resistor R1 and the second resistor R1 are equal, the values of the first capacitor _CS1 and the second capacitor _CS2 are equal, and a reasonable layout matching technique is adopted to make the relative error become is very small, combined with the volt-second balance formula, it can be deduced that the values of the first detection voltage V _S1 and the second detection voltage V _S2 at the end of demagnetization are just equal, therefore, the comparator 151 always outputs a high voltage level, the NAND gate 153 outputs a high level, the clock signal of the flip-flop 155 maintains a low level, the flip-flop 155 outputs a low level, and no dead zone pulse signal T _D is generated. When the difference between the two is less than zero (the first detection voltage V _S1 is less than the second detection voltage V _S2 ), the comparator 151 outputs a low level, and the NAND gate 153 outputs a low level, so The clock signal of the flip-flop 155 jumps to a high level, the flip-flop 155 is triggered and outputs a high-level pulse signal, and the dead zone pulse signal T _D is generated.

Step S6: When a switching cycle ends, the first detection voltage V _S1 , the second detection voltage V _S2 and the dead zone pulse signal T _D are reset, and the reset is only for a very short time at the beginning of the switching cycle within the segment for the next cycle of detection.

Step S7: Control the power switch tube in the synchronous switching power supply circuit with the dead zone pulse signal T _D , when the dead zone pulse signal T _D takes effect (high level), turn off the power switch tube to avoid Current backflow, thereby improving efficiency and safety performance.

As shown in Figure 7, when the inductor current is in continuous mode, the duty cycle cut-off time That is, the demagnetization time T _OFF . When it is detected that the first detection voltage V _S1 is equal to the second detection voltage V _S2 , the inductor current just crosses zero, and no dead zone pulse signal T _D is generated, and the synchronous switching power supply circuit operates at the original setting A certain duty cycle conduction signal T _ON and a duty cycle cut-off signal control the power switch tube.

As shown in Figure 8, when the inductor current is discontinuous mode, the duty cycle cut-off time is the sum of the demagnetization time T _OFF and the dead time T _D . When it is detected that the first detection voltage V _S1 is less than the second detection voltage V _S2 , the inductor current is completely released and kept at zero, generating the dead zone pulse signal T _D , the dead zone pulse signal T _D controls the power switch tube in the synchronous switching power supply circuit to be turned off, so as to avoid current backflow.

Suppose the input voltage VIN is set to 3.3V, the load is set to 100Ω, that is, the load current is 50mA, the inductor current IL, the first detection voltage V _S1 , the second detection voltage V _S2 and the dead zone pulse signal The simulation waveform of T _D is shown in Figure 9. In the magnetization stage of the inductor current, the rising slope of the first detection voltage V _S1 is 1.86V/us, the rising slope of the second detection voltage V _S2 is 0.92V/us, and the dead zone pulse signal T _D is low. level; during the demagnetization stage of the inductor current, the first detection voltage V _S1 remains unchanged, while the second detection voltage V _S2 continues to rise at a rate of 0.4V/us, when the second detection voltage V _S2 is close to At the moment of the first detection voltage V _S1 , the demagnetization of the inductor current IL just ends, and when the second detection voltage V _S2 exceeds the first detection voltage V _S1 , the comparator triggers the dead zone pulse signal T _D to become high Level, and then control the power switch to turn off, and the reverse flow path is blocked. When the next clock cycle comes, the first detection voltage V _S1 and the second detection voltage V _S2 are quickly pulled to the ground, the dead zone pulse signal T _D is reset to low level, and the zero-crossing detection circuit is Start a new round of sample comparison operation.

As shown in Figure 10, the simulation waveform diagram of the system node signal in the inductor current discontinuous mode, where PWM_P is the gate pulse signal of the power switch tube, when the inductor current starts to demagnetize, the signal PWM_P jumps from high level to low Level, when the demagnetization of the inductor is over, the dead zone pulse signal T _D is converted by the logic circuit and the gate drive circuit, and then the control signal PWM_P jumps to a high level, and then the power switch tube is turned off. Since the gate drive circuit of the power switch tube has an intrinsic delay function, there is a certain delay time between the triggering time of the rising edge of the logic signal T _D and the gate drive signal PWM_P, and the inductor current IL will appear a small amount during this time period. In order to improve this non-ideal effect, the methods that can be adopted are: (1) improve the drive capability of the power switch tube gate and reduce the delay time; or (2) when configuring the parameters of the zero-crossing detection circuit, try to make the dead The zone pulse signal T _D occurs in advance, and the advance time is not less than the delay time of the power switch tube.

In summary, the present invention provides a current zero-crossing detection method, circuit and control method for switching power supply inductors, including: obtaining the sampling current of the magnetization voltage based on the first current sampling module; obtaining the demagnetization voltage based on the second current sampling module The sampling current; based on the first detection voltage generation module, the first detection voltage is proportional to the product of the magnetization voltage and the duty ratio conduction time; based on the second detection voltage generation module, the magnetization voltage and the The first voltage proportional to the product of the on-time of the duty cycle and the second voltage proportional to the product of the demagnetization voltage and the off-time of the duty cycle, the sum of the first voltage and the second voltage is the second detection Voltage: comparing the first detection voltage and the second detection voltage based on the dead zone pulse generating circuit to detect the current zero crossing point and the dead zone. The current zero-crossing detection method, circuit and control method of the switching power supply inductance of the present invention indirectly sample the inductance current zero-crossing signal through the volt-second balance principle, avoiding the processing of small signals, forming a control circuit, and solving the problem of current backflow; Remove the sampling resistor on the system; it not only improves the efficiency of the system, but also simplifies the system solution of the power system and improves the competitiveness of the product. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (18)

1. A current zero-crossing detection method of a switching power supply inductor is characterized by at least comprising the following steps:

based on a volt-second balance principle, detecting magnetizing energy and demagnetizing energy of an inductor current in a switching period, comparing the magnetizing energy with the demagnetizing energy, and when the magnetizing energy is equal to the demagnetizing energy, the current of the inductor passes through zero;

the magnetizing energy is the product of magnetizing voltage and magnetizing time, and the demagnetizing energy is the product of demagnetizing voltage and demagnetizing time.

2. The method for detecting the zero crossing of the current of the switching power supply inductor according to claim 1, wherein: the current zero-crossing detection method of the switch power supply inductor further comprises the following steps:

within the duty ratio conduction time, charging the first capacitor by twice the sampling current of the line voltage, and simultaneously charging the second capacitor by the sampling current of the line voltage;

charging the second capacitor with a sampling current of the difference between the line voltage and the output voltage within the duty-cycle cut-off time;

comparing the voltage on the first capacitor with the voltage on the second capacitor, wherein when the voltage on the first capacitor is equal to the voltage on the second capacitor, the current of the switch power supply inductor crosses zero; when the voltage on the first capacitor is smaller than the voltage on the second capacitor, the switch power supply inductor enters a dead zone.

3. The method for detecting the zero crossing of the current of the switching power supply inductor according to claim 2, wherein: and when the inductive current is in a continuous mode, the duty ratio cut-off time is the demagnetization time.

4. The method for detecting the zero crossing of the current of the switching power supply inductor according to claim 2, wherein: and when the inductive current is in an intermittent mode, the duty ratio cut-off time is the sum of the demagnetization time and the dead time.

5. A current zero-crossing detection control method of a switching power supply is characterized by at least comprising the following steps:

acquiring line voltage and output voltage of a synchronous switching power supply circuit, detecting a zero crossing point and dead time of inductive current in the synchronous switching power supply circuit based on the method of any one of claims 1-4, and outputting a dead time pulse signal;

and a power switch tube in the synchronous switch power supply circuit is controlled to be switched off by the dead zone pulse signal so as to avoid current backflow.

6. The current zero-crossing detection control method of the switching power supply inductor according to claim 5, characterized in that: and reducing the delay time of the power switch tube by improving the grid driving capability of the power switch tube.

7. The current zero-crossing detection control method of the switching power supply inductor according to claim 5, characterized in that: and enabling the dead zone pulse signal to generate in advance set time by configuring circuit parameters, wherein the set time is not less than the delay time of the power switch tube.

8. A current zero-crossing detection circuit of a switching power supply inductor is characterized by at least comprising:

the first current sampling module is used for acquiring sampling current of magnetizing voltage, and recording the sampling current as first sampling current, wherein the magnetizing voltage is line voltage;

the second current sampling module is used for acquiring a sampling current of the demagnetization voltage, and recording the sampling current as a second sampling current, wherein the demagnetization voltage is a difference value between a line voltage and an output voltage;

the first detection voltage generation module is connected to the output end of the first current sampling module, receives a duty ratio conduction signal and is used for generating a first detection voltage, and the first detection voltage is in direct proportion to the product of the magnetizing voltage and the duty ratio conduction time;

a second detection voltage generation module, connected to the output ends of the first current sampling module and the second current sampling module, receiving a duty cycle on signal and a duty cycle off signal, and respectively generating a first voltage proportional to the product of the magnetizing voltage and the duty cycle on time and a second voltage proportional to the product of the demagnetizing voltage and the duty cycle off time, wherein the first voltage and the second voltage are superimposed to generate a second detection voltage;

the dead zone pulse generating circuit is connected with the output ends of the conduction voltage detection module and the cut-off voltage detection module, compares the first detection voltage with the second detection voltage to obtain the difference value between the product of the magnetizing voltage and the duty ratio conduction time and the product of the demagnetizing voltage and the duty ratio cut-off time, and outputs a dead zone pulse signal when the first detection voltage is smaller than the second detection voltage.

9. A current zero-crossing detection circuit of a switching power supply inductor according to claim 8, wherein: the first current sampling module receives a sampling signal of line voltage and converts the sampling signal of the line voltage into a current signal through a first resistor.

10. A current zero-crossing detection circuit of a switching power supply inductor according to claim 9, characterized in that: the first current sampling module includes: the first resistor, the first voltage follower, the first PMOS tube and the second PMOS tube;

the first voltage follower receives a sampling signal of the line voltage;

one end of the first resistor is grounded, and the other end of the first resistor is connected with a first output end of the first voltage follower;

the drain end of the first PMOS tube is connected with the second output end of the first voltage follower, the grid end of the first PMOS tube is connected with bias voltage, and the source end of the first PMOS tube is connected with the drain end of the second PMOS tube;

the source end of the second PMOS tube is connected with a power supply, and the grid end of the second PMOS tube is connected with the drain end of the first PMOS tube and serves as the output end of the first current sampling module.

11. A current zero-crossing detection circuit of a switching power supply inductor according to claim 8, wherein: the second current sampling module receives the sampling signal of the line voltage and the sampling signal of the output voltage, and converts the difference value of the sampling signal of the line voltage and the sampling signal of the output voltage into a current signal on a second resistor.

12. A current zero-crossing detection circuit of a switching power supply inductor according to claim 11, wherein: the second current sampling module includes: the second voltage follower, the third voltage follower, the second resistor, the third PMOS tube and the fourth PMOS tube;

the second voltage follower receives a sampling signal of the line voltage;

the third voltage follower receives a sampling signal of the output voltage;

the second resistor is connected between the output end of the second voltage follower and the output end of the third voltage follower;

the drain end of the third PMOS tube is connected with the output end of the third voltage follower, the grid end of the third PMOS tube is connected with bias voltage, and the source end of the third PMOS tube is connected with the drain end of the fourth PMOS tube;

and the source end of the fourth PMOS tube is connected with a power supply, and the grid end of the fourth PMOS tube is connected with the drain end of the third PMOS tube and serves as the output end of the second current sampling module.

13. A current zero-crossing detection circuit of a switching power supply inductor according to claim 8, wherein: the first detection voltage generation module charges a first capacitor within the duty cycle conduction time by using the first sampling current to obtain the first detection voltage.

14. A current zero crossing detection circuit of a switching power supply inductor according to claim 13, wherein: the first detection voltage generation module includes: the first capacitor, the first switch, the fifth PMOS tube and the sixth PMOS tube;

the lower polar plate of the first capacitor is grounded, and the upper polar plate of the first capacitor is connected with one end of the first switch;

the other end of the first switch is connected with the drain end of the fifth PMOS tube, and the first switch is controlled to be closed by the duty ratio conduction signal;

the source end of the fifth PMOS tube is connected with the drain end of the sixth PMOS tube, and the gate end of the fifth PMOS tube is connected with bias voltage;

and the source end of the sixth PMOS tube is connected with a power supply, and the grid end of the sixth PMOS tube is connected with the output end of the first current sampling module.

15. A current zero-crossing detection circuit of a switching power supply inductor according to claim 8, wherein: the second detection voltage generation module charges a second capacitor within the duty ratio on time by using the first sampling current, charges the second capacitor within the duty ratio off time by using the second sampling current, and obtains the second detection voltage by overlapping the charging voltages twice.

16. A current zero crossing detection circuit of a switching power supply inductor according to claim 15, wherein: the second detection voltage generation module includes: the second capacitor, a second switch, a seventh PMOS tube, an eighth PMOS tube, a third switch, a ninth PMOS tube and a tenth PMOS tube;

the lower polar plate of the second capacitor is grounded, and the upper polar plate of the second capacitor is respectively connected with one end of the second switch and one end of the third switch;

the other end of the second switch is connected with the drain end of the seventh PMOS tube, and the second switch is controlled to be closed by the duty ratio conducting signal;

the source end of the seventh PMOS tube is connected with the drain end of the eighth PMOS tube, and the gate end of the seventh PMOS tube is connected with bias voltage;

the source end of the eighth PMOS tube is connected with a power supply, and the grid end of the eighth PMOS tube is connected with the output end of the first current sampling module;

the other end of the third switch is connected with the drain end of the ninth PMOS tube, and the third switch is controlled to be closed by the duty ratio cut-off signal;

the source end of the ninth PMOS tube is connected with the drain end of the tenth PMOS tube, and the gate end of the ninth PMOS tube is connected with the bias voltage;

and the source end of the tenth PMOS tube is connected with a power supply, and the grid end of the tenth PMOS tube is connected with the output end of the second current sampling module.

17. A current zero-crossing detection circuit of a switching power supply inductor according to claim 8, wherein: the dead zone pulse generating circuit comprises a comparator, an AND gate and a trigger;

the first input end of the comparator is connected with the first detection voltage, and the second input end of the comparator is connected with the second detection voltage;

the first input end of the AND gate is connected with the output end of the comparator, and the second input end of the AND gate is connected with the duty ratio cut-off signal;

the input end of the trigger is connected with the high level, and the clock end of the trigger is connected with the output end of the AND gate.

18. The current zero-crossing detection circuit of the switching power supply inductor according to claim 1, characterized in that: the output ends of the first detection voltage generation module and the second detection voltage generation module are respectively connected with a reset tube so as to clear the first detection voltage and the second detection voltage.