CN107144821B - Efficient receiving channel based on time delay beam forming in broadband digital array radar - Google Patents

Abstract

The invention provides a high-efficiency receiving channel based on time-delay beam forming in a broadband digital array radar. Compared with a group of sub-filter banks for each receiving channel in the traditional receiving channel structure, the invention is based on the design of the channel filter of the Farrow structure, Each receiving channel uses the same L+1 sub-filter bank, which greatly reduces the complexity of the entire structure; since multiple channels share a set of sub-filters, it is only necessary to modify the fractional delay factor in the fractional delay module. The frequency response characteristics of the entire receiving channel can be reconstructed, and the flexibility of the system is better.

Description

Efficient Receiver Channel Based on Time Delay Beamforming in Wideband Digital Array Radar

technical field

The invention belongs to the signal processing technology, and specifically relates to the extraction and time delay synchronization adjustment technology of multiple receiving channels in a broadband digital array radar.

Background technique

In order to obtain higher range resolution and improve the ability to identify targets, wideband digital array radar WBDAR came into being. It uses broadband signals to obtain target information, which improves the ability to identify and distinguish targets while obtaining higher range resolution. But it also makes WBDAR need to use the real delay line TTD to perform large-angle electronic scanning in the area to replace the phase shifter. Compared with the traditional TTD analog method, the method of using digital delay filter can reduce the extra insertion loss and provide a continuously variable and precise delay to ensure that the broadband beam is directed to the target in any direction, which greatly compensates. Many disadvantages of analog delay compensation are eliminated.

In recent years, with the rapid development of analog and digital chips, the realization of WADAR has become feasible. However, the high-speed signal processing speed and a large amount of hardware resource consumption increase the complexity and cost of the system, thus limiting the realization of WBDAR. Therefore, how to optimize the system structure and reduce the complexity of the processing is still the focus of research.

In the traditional WBDAR receiving channel, the main structure usually includes microwave amplifier LNA, high-speed analog-to-digital conversion ADC module, quadrature local oscillator mixing unit NCO, signal extraction module (Decimation), amplitude and phase weighting module (Magnitude&Phase Weighting), Integer delay module (Unit Delay) variable fractional delay VFD filter, as shown in Figure 1. The M times signal extraction module consists of an anti-aliasing filter and a decimation module. The design of signal extraction and VFD filter becomes the key factor to improve the efficiency and reconfigurability of the system. In the traditional channel receiving structure, the antenna received signal passes through the microwave amplifier LNA to output the RF signal and is then sampled by the ADC to increase the dynamic range and reduce the receiver phase noise. The module performs signal extraction to reduce the signal data rate. The intermediate amplitude weighting and phase weighting are used to suppress the side lobes of the receiving beam and compensate for the phase difference caused by the arrival time difference of the multi-channel RF signals. Finally, after an integer delay and fractional delay VFD module, the corresponding signal is finally output. The VFD filter adopts the Farrow structure. As shown in Figure 2, it is composed of L+1 FIR sub-filters G _k (z), L delay units, and L adders in cascade, where d ^k is the fractional delay Factor, k=0,1,2...,L. It should be noted that the decimation and VFD filter modules are separated here. This structure increases the complexity of the system to a certain extent, reduces the work efficiency of the system, and at the same time, the system has poor reconfigurability.

In a digital signal processing system, the number of multipliers and adders becomes the main resource consumption of the whole hardware. Considering that the system may work at different frequencies, we use the ratio of multiplication rate and addition rate to evaluate the complexity of the system, where the multiplication rate _Rm is expressed as follows:

where M is the decimation factor and C _m is the number of multipliers. Similarly, the addition rate _Ra is expressed as follows:

where C _a is the number of adders.

In the traditional WBDAR channel receiving structure, in the case of one-level decimation, the number of multipliers C _mo and the number of adders C _ao are as follows:

C _mo =N[N ₁ +2+3+(L+1)(N _s +1)+2L], (3)

C _ao =N[2N ₁ +5+2N _s (L+1)+2L]+2N-2, (4)

Among them, N ₁ is the order of the anti-aliasing filter before decimation, N _s is the order of the sub-filter in the VFD filter, L is the number of parallel branches of the Farrow structure in the VFD filter, N is the number of the entire receiving channel, Only even-numbered anti-aliasing filters and odd-numbered order sub-filters are considered here, and other orders are similar.

Considering the case of 2-level extraction, R _mo and R _ao are expressed as follows:

Among them, N _i , i=1, 2 represent the order of the anti-aliasing filter before 1-stage decimation and 2-stage decimation, respectively, M _i , i=1, 2 represent the decimation in 1-stage decimation and 2-stage decimation, respectively factor, the decimation factor M=M ₁ M ₂ of the entire receiving channel.

It can be seen from the above analysis that in the traditional receiving channel structure, the complexity and efficiency have not reached the ideal state, and there is still room for further optimization. At the same time, its reconfigurability and flexibility are insufficient, which also needs to be further improved. place.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide an efficient, flexible and reconfigurable receiving channel structure in a broadband digital array radar.

The technical solution adopted by the present invention to solve the above technical problems is that an efficient receiving channel based on time delay beamforming in a broadband digital array radar includes N receiving channels, two first-order adders, and two sets of FIR sub-filter banks, The N-channel I signal output in the N-channel receiving channel is connected to the input end of a first-stage adder, the N-channel Q signal in the N-channel receiving channel is connected to the input end of another first-stage adder, and the first-stage adder The output ends of the FIR sub-filters are respectively connected with the corresponding input ends of a group of FIR sub-filter banks; the I signal and the Q signal represent mutually orthogonal signals; each receiving channel includes an analog-to-digital converter, an integer delay module, an quadrature A vibration mixing unit, a polyphase decomposition module, a fractional delay module, two second-stage adders, and a weighting module; the output end of the analog-to-digital converter is connected to the input end of the integer delay module, and the output end of the integer delay module is connected to the input end of the integer delay module. The input end of the quadrature local oscillator mixing unit is connected, the I signal and the Q signal of the quadrature local oscillator mixing unit are connected to the input end of the fractional delay module and the I signal of the fractional delay module through the polyphase decomposition module, and the fractional delay module The output end of the I signal is connected to a second-stage adder, the Q signal output end of the fractional delay module is connected to another second-stage adder, and the output end of the two second-stage adders is connected to the input end of the weighting module. The I signal output in the module is the I signal output of the receiving channel, and the Q signal output in the weighting module is the Q signal output of the receiving channel.

Compared with a group of sub-filter banks for each receiving channel in the traditional receiving channel structure, the present invention is based on the design of the channel filter of the Farrow structure, so that each receiving channel uses the same L+1 sub-filter bank, so that the entire structure has the same L+1 sub-filter bank. The complexity is greatly reduced; since multiple channels share a set of sub-filters, the frequency response characteristics of the entire receiving channel can be reconstructed only by modifying the fractional delay factor in the fractional delay module, and the system is more flexible.

The beneficial effects of the present invention are that the structural complexity is lower, and the flexibility and reconfigurability are stronger.

Description of drawings

Fig. 1 is a schematic diagram of a traditional WBDAR receiving channel structure;

Figure 2 shows the basic structure of Farrow;

Fig. 3 is the structural representation of the channel filter in the design process of the present invention;

FIG. 4 is a schematic structural diagram of a receiving channel of the present invention.

Detailed ways

The key part of the present invention includes the fractional delay decimator based on the Farrow structure, and the design of the channel filter matched with its functional realization.

The overall structure of the embodiment is shown in Figure 4, including N channels of receiving channels, 2 first-level adders, 2 groups of FIR sub-filters, N channels of I signal outputs in the N channels of receiving channels and the output of one first-level adder. The input ends are connected, and the N-channel Q signals in the N-channel receiving channels are connected with the input end of another one-stage adder, and the output ends of the first-stage adder are respectively connected with the input ends of a corresponding group of FIR sub-filters; I The signal and the Q signal represent mutually orthogonal signals;

Each receiving channel includes an analog-to-digital converter, an integer delay module, a quadrature local oscillator mixing unit, a polyphase decomposition module, a fractional delay module, two second-level adders, and a weighting module; the output end of the analog-to-digital converter It is connected with the input end of the integer delay module, the output end of the integer delay module is connected with the input end of the quadrature local oscillator mixing unit, and the I signal and the Q signal of the quadrature local oscillator mixing unit are divided into fractions by the polyphase decomposition module. The I signal of the delay module is connected to the input end of the Q signal, the I signal output end of the fractional delay module is connected to a second-stage adder, and the Q signal output end of the fractional delay module is connected to another second-stage adder , the output ends of the two second-level adders are connected with the input end of the weighting module, the I signal output in the weighting module is the I signal output of the receiving channel, and the Q signal output in the weighting module is the Q signal output of the receiving channel;

The channel filter consists of a fractional delay module, a two-stage adder and a FIR sub-filter bank, as shown in Figure 3;

表示，其中m＝0,1,2…,M-1表示多相分解的M个因子，k＝0,1,2…,L表示每个分解路中并行的L+1路乘法因子。二级加法器用于把这多相分解的M路中各自的L+1路并行分支信号相加求和。The M-channel polyphase decomposition module is used to complete an M-channel polyphase decomposition, and its main function is to reduce the rate of each channel signal to 1/M of the original; the channel filter contains M fractional delay weighting modules, At the same time, each phase decomposition factor contains L+1 parallel multiplication factors, using

represents, where m=0, 1, 2..., M-1 represents the M factors of the multiphase decomposition, and k=0, 1, 2..., L represents the L+1 multiplication factors in parallel in each decomposition path. The second-level adder is used to add and sum up the respective L+1 parallel branch signals of the M channels of the polyphase decomposition.

The transfer function of the FIR sub-filter bank is represented by G _k (z), k=0, 1, 2..., L, where each G _k (z) is the transfer function of a sub-FIR filter. If the channel filter needs to match the structure of the fractional delay decimator, it is necessary to set a reasonable fractional delay factor and impulse response of the channel filter.

Ideally, the frequency response of the channel filter is expressed as:

Among them, N _c is the order of the entire channel filter, w is the angular frequency, T is the time variable, ws is the cutoff angular frequency, _ws T=π/M, M is the decimation factor, and _d is the fractional delay of the entire channel. time factor. The transfer formula for the multiphase decomposition structure of the entire channel is:

Among them, m is the branch variable of the multiphase decomposition, m=0, 1..., M-1, z is the z variable, and H _m (z ^M ) is the transition formula of each branch. Here, the multiphase decomposition can be achieved by using a Farrow structure as shown in Figure 2. The transfer formula is:

where d ^k is the fractional delay factor of the kth parallel branch, and G _k (z) is the transfer function of the sub-filter bank in the z transform domain;

Therefore, the multiphase decomposition structure transfer formula (7) of the whole channel can be rewritten as:

为多相分解第每m路第k条并行分支对应的分数延时因子，m＝0,1...,M-1，k＝0,1,2…,L。in,

is the fractional delay factor corresponding to the k-th parallel branch of every m-th way of polyphase decomposition, m=0, 1..., M-1, k=0, 1, 2..., L.

The relationship between a FIR subfilter of order N _s and the number of polyphase decomposition branches M and the order N of the entire channel filter can be expressed by the following formula:

N=(N _s +1)M-1 (11)

Combining formulas (7), (8) and (11), we can get:

Putting (11) into (12), we get:

Among them, d _m is the fractional delay factor of the mth channel of polyphase decomposition, and d is the fractional delay of the whole channel. At this point, it can be concluded that the impulse response of each branch after the polyphase decomposition of the entire channel filter is:

Among them, n=0,1...,N ₁ , m=0,1...,M-1, N ₁ is the order of the Farrow structure sub-filter, g _k (n) is the time-domain impulse response function of the sub-filter .

The complexity of the structure of the present invention can be represented by the number of multipliers and adders of the system, and the results are as follows:

C _mn = 2NLM+3N(L+1)+(N _s +1)(L+1), (15)

_Can = 2N(L+1)(M-1)+5N(L+1)+2(N-1)(L+1)+2(L+1) _Ns +2L (16)

It can be seen that the high-efficiency receiving channel structure based on time-delay beamforming designed by the present invention greatly reduces the realization complexity of the receiving channel structure in the traditional broadband digital array radar. When N=8, M=2, _Ns =5, N1 ₌ 26, _N2 =0, L=3, the traditional receiving channel structure multiplication rate and addition can be deduced from formulas (3) and (4). The ratios are R _mo =244, R _ao =419, and in the receiving channel structure of the present invention, under the same configuration, when N _s =13, R _mn =124 can be obtained from formulas (15) and (16), R _an = 195, which is significantly better than the traditional structure. The number of multipliers and adders used is reduced, and the number of multiplication and addition operations to be completed per unit time is greatly reduced, thereby reducing the complexity of system implementation.

By designing the polyphase decomposition module and the matching channel filter, the flexibility and reconfigurability of the entire receiving channel structure are greatly increased. The traditional channel receiving structure needs to configure a large number of filter parameters, decomposition factors and fractional delay factors in advance, which limits the flexibility and reconfigurability of the entire receiving structure. The structure of the present invention replaces the traditional anti-aliasing filter and VFD structure by designing a suitable channel filter based on polyphase decomposition and Farrow structure, reduces parameter settings, and at the same time has higher flexibility, only the channel filter needs to be modified The fractional delay weighting parameter can change the frequency response of the channel.

The specific implementation steps of the entire receiving channel structure are as follows:

Step 1: Set the polyphase decomposition module and channel filter to replace the traditional anti-aliasing filter and the functions of the VFD structure. First, the signal passes through an M-way polyphase decomposition, and then enters the designed channel filter. The ideal frequency response function of the channel filter is given by equation (7), and is designed according to the impulse response of equation (14). The parameter setting of the channel filter includes three parts, one is the setting of the fractional delay factor in the channel filter, with reference to formula (13), the corresponding fractional delay factor d _m can be obtained; the second is the sub-filter bank G _k ( The order of z) is set N _s ; the third is the coefficient setting of the sub-filter bank G _k (z). The fractional delay module and the weighting module perform fractional delay weighting on the L+1 channel signals of the M groups, and after summing and merging, the L+1 channel signals are generated.

Step 2: First configure a channel structure of a receiving channel, the low noise amplifier module LNA, the data acquisition module ADC, and the integer delay module (Unit Delay D ₀ ) are connected in series in sequence, and then pass through a quadrature local oscillator mixing unit to reach the polyphase decomposition module.

Step 3: After the signals passed through the polyphase decomposition module and the fractional delay module are subjected to amplitude and phase weighting (weighting W _n ), L+1 signals are generated, where n=0, 1..., N-1.

Step 4. After the setting of one receiving channel is completed, set the structure of the remaining N-1 receiving channels, and the structure of each receiving channel is set according to steps 1 to 3. Finally, the N(L+1) signals of the N receiving channels are summed and combined by the first-stage adder to generate L+1 signals, which are divided into I and Q into the corresponding L+1 sub-filters. group, realizing that N channels share one sub-filter group.

After the above steps, two orthogonal output signals y _I and y _q that meet the requirements can be obtained.

Claims (1)

1. the high-efficiency receiving channel based on time-delay beamforming in the broadband digital array radar, is characterized in that, comprises N-way receiving channels, 2 first-level adders, 2 groups of FIR sub-filter banks, and N-way receiving channels in N-way receiving channels The I signal output is connected to the input of one first-level adder, the N-channel Q signal in the N-channel receiving channel is connected to the input of another first-level adder, and the output of the first-level adder is respectively connected to the corresponding 1 The input ends of the FIR sub-filter bank are connected; the I signal and the Q signal represent mutually orthogonal signals; each receiving channel includes an analog-to-digital converter, an integer delay module, a quadrature local oscillator mixing unit, and a polyphase decomposition. module, fractional delay module, two two-stage adders, weighting module; the output end of the analog-to-digital converter is connected with the input end of the integer delay module, and the output end of the integer delay module is connected with the quadrature local oscillator mixing unit. The input end is connected, the I signal and the Q signal of the quadrature local oscillator mixing unit are connected to the input end of the I signal and the Q signal of the fractional delay module through the polyphase decomposition module, and the I signal output end of the fractional delay module is connected to a The second-stage adder is connected, the Q signal output end of the fractional delay module is connected to another second-stage adder, the output end of the two second-stage adders is connected to the input end of the weighting module, and the I signal output in the weighting module is this channel The I signal output of the receiving channel, the Q signal output in the weighting module is the Q signal output of the receiving channel; The fractional delay factor of the fractional delay module is: Among them, d _m is the fractional delay factor of the mth path of polyphase decomposition, d is the fractional delay of the entire channel, M is the extraction factor of the entire channel filter, m is the branch variable of the polyphase decomposition of the extraction module, m= 0,1...,M-1; the channel filter consists of a fractional delay module, a two-stage adder and a FIR sub-filter bank; After the channel filter is polyphase decomposed, the obtained polyphase branch filter impulse response h(Mn+m) is expressed by the Farrow structure as:

Among them, N _s is the order of the Farrow structure FIR sub-filter n=0, 1..., Ns, m=0, 1..., M-1, g _k (n) is the FIR sub-filter time domain Impulse response function,

is the fractional delay factor corresponding to the k-th parallel branch of the m-th way of polyphase decomposition, m=0, 1..., M-1, k=0, 1, 2..., L, L is the channel filter The number of parallel branches in the Farrow structure.

Images