CN107068652A - Wafer stage chip encapsulating structure and method for packing - Google Patents

Abstract

The present invention relates to a wafer-level chip packaging structure and manufacturing method, including a chip unit, which has a first surface and a second surface oppositely arranged, and the first surface is arranged with at least one solder window for electrical connection; the second A TSV structure connected to the solder window is provided on the surface, and the TSV structure includes a through hole penetrating the first surface and the second surface and a groove provided on the second surface, and the distance between the boundary of the groove and the edge of the second surface is greater than 10um. The progress achieved relative to the prior art is to increase the structural strength of the chip.

Description

Wafer level chip packaging structure and packaging method

technical field

The invention relates to the technical field of semiconductors, in particular to a wafer-level chip packaging structure and a packaging method thereof.

Background technique

TSV (Through Silicon Vias) packaging structure is a kind of IC packaging method, which can be divided into memory packaging and wafer-level packaging for chip devices. Wafer-level packaging is applied to an optical image sensor (please refer to FIG. 1). In this case, the optical image sensor 2 has a glass substrate 3 supporting a TSV structure 4 to maintain structural strength. The openings 41, grooves 22, wiring 23 and Z-axis connection structures such as solder windows 24 are arranged on the edge 21 of the image sensor chip to facilitate manufacturing.

However, some chips (such as capacitive fingerprint sensor chips) require TSV packaging but do not have a glass plate as a support in order to reduce the thickness of the package. structure), will produce technical defects of insufficient chip edge strength, which will bring risks in subsequent processing. For example, when cutting the wafer, the risk of chip cracking due to stress is increased, and it will also bring risks in the later stage of placement and assembly.

Therefore, it is necessary to improve the TSV structure and manufacturing method to improve the structural strength of the chip to solve the above problems.

Contents of the invention

The purpose of this technical solution is to ensure the overall thickness of the chip so as to improve the structural strength of the chip. For this reason, the slot of the TSV is arranged inside the chip so that the slot and the edge of the chip maintain a certain safety distance, for example, greater than 10um. Since the TSV slot is arranged inside the chip, the thickness of the chip outside the TSV slot is the same as the thickness inside the slot, and the structural strength is improved.

The technical solution of the present invention comprises the following specific contents:

The wafer-level chip packaging structure is characterized in that it includes a chip unit, which has a first surface and a second surface oppositely arranged, the first surface is arranged with at least one solder window for electrical connection; the second surface is arranged A TSV structure connected to the solder window, the TSV structure includes a through hole penetrating the first surface and the second surface and a groove provided on the second surface, the distance between the boundary of the groove and the edge of the second surface is greater than 10um.

Preferably, the distance L between the boundary of the welding window and the edge of the first surface satisfies the relation

Preferably, at least one pad is provided on the second surface of the chip unit, and the solder window and the pad are electrically connected through the wiring formed on the through hole wall, the bottom wall of the slot, the side wall of the slot, and the second surface. .

In order to better solve the above-mentioned technical problems, the present invention also provides a method for manufacturing a wafer-level chip packaging structure, including steps:

S1: Arrange the solder window on the first surface of the chip unit, so that the distance L between the solder window and the edge of the first surface satisfies the relational expression

S2: forming a trapezoidal groove on the second surface of the chip unit, the projection of the bottom wall of the groove on the first surface covers the solder window, and the distance between the boundary of the groove and the edge of the second surface is greater than 10um;

S3: forming a through hole through the welding window and the bottom wall of the slot in the slot, so that the through hole is connected to the welding window;

S4: forming wiring on the wall of the through hole, the bottom wall of the slot, the side wall of the slot, and the second surface, and the wiring is electrically connected to the solder window and the pad.

Preferably, the aspect ratio k of the sidewall of the groove is approximately equal to 2.75.

Preferably, the trapezoidal groove is one or more stages of trapezoidal grooves.

In order to move the TSV slot to the inside of the chip, the present invention makes the height of the chip outside the TSV slot the same as the height inside the chip, improves the strength of the edge of the chip, and avoids the design of a left-right symmetrical solder window structure at the same time. This design has an influence on the circuit design.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic cross-sectional structure diagram of a TSV package structure of an image sensor in the prior art.

Fig. 2a is a schematic perspective view of the TSV package structure of the present invention.

Fig. 2b is a schematic perspective view of the TSV packaging structure of the present invention.

FIG. 3 is a schematic diagram of the second surface pad array of the present invention.

Fig. 4a is a schematic diagram of the cross-sectional structure of the present invention in the TSV manufacturing step S1.

Fig. 4b is a schematic diagram of the cross-sectional structure of the present invention in the TSV manufacturing step S2.

Fig. 4c is a schematic diagram of the cross-sectional structure of the present invention in the TSV manufacturing step S3.

Fig. 4d is a schematic diagram of the cross-sectional structure of the present invention in the TSV manufacturing step S4.

Fig. 4e is a schematic diagram of another embodiment of the present invention in a TSV structure.

Fig. 5 is a schematic diagram of the functional structure of the welding window of the present invention.

6a-6c are schematic diagrams of four kinds of welding window components in the welding window layout in the fifth embodiment of the present invention.

detailed description

In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

As shown in FIG. 2 a , the wafer-level chip packaging structure of the present invention includes a chip unit 1 , and the chip unit has a first surface 115 and a second surface 116 disposed opposite to each other. In the present invention, the fingerprint sensor chip is taken as an example, the first surface 115 is provided with functional circuits 132, 131 and a capacitor unit array (not shown in the figure) for sensing fingerprint images, and the functional circuits are electrically connected to the welding window . The second surface 116 is provided with a pad 12 and a TSV structure electrically connected to the solder window, and the TSV structure includes a through hole 112 penetrating the first surface 115 or the solder window 13 and the second surface 116, and the through hole 112 For the connected slots 11 , the distance between the borders of the slots 110 , 111 and the edge 117 of the second surface is greater than 10 um.

In this embodiment, the distance between the boundary 110 of the groove and the edge 117 of the second surface 116 is greater than 10um so that the thickness d1 outside the chip groove 11 is the same as the thickness d2 inside the chip (refer to FIG. When cutting on the circle, it can withstand the stress generated during cutting to avoid the risk of chip edge chipping.

In this embodiment, the boundary of the slot 11 includes a longitudinally extending boundary 110 and a laterally extending boundary 111; the distance between the boundary of the welding window and the edge of the second surface in the present invention is greater than 10um, which means that any boundary The distance from the edge of the welding window is greater than 10um. Therefore, the distance of the solder window boundary 110 closest to the second surface edge 117 is at least greater than 10um

In order to obtain the above-mentioned TSV packaging structure, the present invention provides the following manufacturing method:

S1: Arrange the solder window on the first surface of the chip unit, so that the distance L between the solder window and the edge of the first surface satisfies the relational expression

S2: forming a trapezoidal groove on the second surface of the chip unit, the projection of the bottom wall of the groove on the first surface covers the solder window, and the distance between the boundary of the groove and the edge of the second surface is greater than 10um;

S3: forming a through hole through the welding window and the bottom wall of the slot in the slot, so that the through hole is connected to the welding window;

S4: forming wiring on the wall of the through hole, the bottom wall of the slot, the side wall of the slot, and the second surface, and the wiring is electrically connected to the solder window and the pad.

The above steps are described in detail as follows:

Please refer to Fig. 4a and Fig. 4b, in step S1, the first surface 115 of the chip arranges the welding window 13, so that the welding window 12 is away from the edge 118 of the first surface 115, and the welding window 13 is away from the edge 118 of the first surface in order to make The boundary 133 of the welding window 13 maintains a certain distance L from the first edge 118 , and the distance L is set such that the boundary 110 of the slot 11 is greater than 10 um from the edge of the second surface 116 . In order to achieve the above purpose, the distance L satisfies the relation

In this embodiment, the first surface edge 118 should be understood as the outermost side of the first surface 115, the boundary of the solder window 113 should be understood as the boundary line between the solder window and the chip; the distance L should be understood as the boundary 113 The smallest achievable distance from the edge 118 of the first surface.

In this step, in order to open the through hole 112, the central axis x of the solder window 13 coincides with the central axis x of the slot 11. When the position of the solder window 13 on the chip unit changes, the position of the corresponding slot 11 The same position change occurs for the position as well.

In this step, functional circuits 131 and 132 and a fingerprint sensing array are arranged simultaneously with the welding window 13 .

In this step, the shape and quantity of the welding windows 13 are designed differently according to needs.

In this step, a plurality of soldering windows 13 may be provided, and a certain distance is maintained between the soldering windows 13 , such that when the through-holes 112 are prepared, the through-holes 112 corresponding to different pads 13 do not interfere with each other.

Please refer to FIG. 4b. In step S2, the groove 11 is prepared on the second surface 116 of the chip unit 1 by means of air/chemical etching. This facilitates the preparation of subsequent through holes 112 .

In this step, the etching method determines the aspect ratio of the side wall of the slot. The angle a between the side wall of the slot formed by air etching and the vertical direction is approximately 20°. The ratio of height h to width w of the side wall of the slot is k:

In this step, the projected area S (also refer to FIG. 1 ) of the bottom wall 1122 of the groove on the first surface covers the solder window 13 to facilitate the subsequent preparation of the through hole 112 . The groove 11 is a trapezoidal structure whose central axis x coincides with the central axis of the groove. When preparing the groove 11, keep the left boundary 110 of the groove greater than 10um from the left edge of the second surface 116 of the chip, and keep The upper and lower borders 110 at both ends of the slot 11 are more than 10um away from the upper and lower edges of the second surface of the chip (refer to FIG. 1 or FIG. 6b ).

In this embodiment, the second surface edge 117 should be understood as the outermost side of the second surface 116, and the groove boundary 110 should be understood as the boundary line between the groove 11 and the second surface; the boundary 110 and the second surface The distance of the edge 117 is to be understood as the smallest distance that the border 110 can reach from the second surface edge 118 .

Please refer to FIG. 4c, in step S3, etching is performed between the groove 11 and the solder window 13 to form a through hole 112 penetrating through the first surface 115 or the solder window 13 and the second surface 116. In this embodiment, the through hole 112 The shape is a hollow truncated cone, and may also be a cylinder in other embodiments.

Referring to Fig. 4d, a circular pad 12 is formed on the second surface 116 of the chip unit and at the periphery of the slot 11, and then electrically connected between the pad 12 and the solder window 13 by wiring 121, so that The functional circuit is electrically connected to the pad 12 .

In this embodiment, the wiring is formed on the wall of the through hole 1121 , the bottom wall of the slot 1122 , the side wall of the slot 1123 and the second surface 116 .

Please refer to FIG. 4e. In this embodiment, multi-level slots 11 can also be set, that is, overlapping trapezoidal slots 113. The wiring 121 extends along the trapezoidal shape of the trapezoidal slots 11 and 113. The distance from the edge 117 of the second surface is greater than 10 um, that is, at least ensure that the boundary distance 110 of the first-level trapezoidal groove of the multi-level trapezoidal groove is greater than 10 um from the edge 117 of the second surface when preparing the trapezoidal groove.

Please refer to Fig. 5 and Fig. 6a, the welding window and functional circuit arranged in the above-mentioned step S1, according to the sequence from top to bottom in the figure, are logical operation circuit 132, ESD protection circuit 131, welding window 13; welding window 13 and logic The arithmetic circuit 131 and the ESD protection circuit 132 form a circuit layout unit 14, and a plurality of the circuit layout units 14 are arranged side by side on the first surface 115 of the chip 1, and the solder window 13 is arranged on a side close to the edge 118 of the first surface The logic operation circuit 132 and the ESD protection circuit 131 are arranged on a side away from the edge 118 of the first surface. Therefore, welding window 13 and logical operation circuit 132, ESD protection circuit 131 relative positional relationship is the same as prior art, in order to meet the boundary distance of described groove 11 when groove is grooved in step S2, groove the second surface edge 117 If it is greater than 10um, the position of the arrangement unit moves away from the edge of the first surface as a whole relative to the prior art, that is, moves upward and to the right (with reference to the paper).

Please refer to the second arrangement of welding windows shown in FIG. 6 b , which is different from the arrangement of welding windows in FIG. 6 a in that a plurality of arrangement units 14 are added on the left side of the first surface 115 . The position of the added arrangement unit 14 moves away from the first surface edge 118 as a whole relative to the prior art, that is, moves downward and to the left (with reference to the paper).

Please refer to the third arrangement of the welding window shown in FIG. 6c. The difference from the arrangement of the welding window 13 in FIG. At the position of the first surface edge 118 , the welding window 13 is arranged in a direction away from the first surface edge 118 . Compared with the arrangement of the welding window in Fig. 6a, the advantage is that the circuit is arranged on the lower welding window 13 and the circuit layout needs to occupy a certain distance, and the welding window 13 is naturally far away from the edge 118 of the first surface, which can be used for the groove 11 in step S2. A sufficient distance is reserved so that the distance between the boundary 110 of the slot 11 and the slot on the second surface is greater than 10 um, and at the same time, the circuit fully utilizes the area of the chip, and the waste of part of the chip area in FIG. 6a does not occur.

It will be apparent to those skilled in the art that the invention is not limited to the details of the above-described exemplary embodiments, but that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the embodiments should be regarded in all points of view as exemplary and not restrictive, the scope of the invention being defined by the appended claims rather than the foregoing description, and it is therefore intended that the scope of the invention be defined by the appended claims rather than by the foregoing description. All changes within the meaning and range of equivalents of the elements are embraced in the present invention. Any reference sign in a claim should not be construed as limiting the claim concerned.

In addition, it should be understood that although this specification is described according to implementation modes, not each implementation mode only includes an independent technical solution, and this description in the specification is only for clarity, and those skilled in the art should take the specification as a whole , the technical solutions in the various embodiments can also be properly combined to form other implementations that can be understood by those skilled in the art.

Claims (7)

1. Wafer-level chip packaging structure, characterized in that it includes a chip unit, which has a first surface and a second surface oppositely arranged, and the first surface is arranged with at least one solder window for electrical connection; the second A TSV structure connected to the solder window is provided on the surface, and the TSV structure includes a through hole penetrating the first surface and the second surface and a groove provided on the second surface, and the distance between the boundary of the groove and the edge of the second surface is greater than 10um. 2. The wafer-level chip packaging structure according to claim 1, wherein the distance L between the boundary of the solder window and the edge of the first surface satisfies the relational expression 3. The wafer-level chip packaging structure according to claim 1, wherein at least one pad is provided on the second surface of the chip unit, and the solder window and the pad are formed on the through-hole wall, The wiring on the bottom wall of the slot, the side wall of the slot and the second surface is electrically connected. 4 . The wafer level chip packaging structure according to claim 1 , wherein the slot is one or more trapezoidal slots. 5. The manufacturing method of wafer level chip package structure as claimed in claim 1, is characterized in that, comprises the step: S1: Arrange the solder window on the first surface of the chip unit, so that the distance L between the solder window and the edge of the first surface satisfies the relational expression S2: forming a trapezoidal groove on the second surface of the chip unit, the projection of the bottom wall of the groove on the first surface covers the solder window, and the distance between the boundary of the groove and the edge of the second surface is greater than 10um; S3: forming a through hole through the welding window and the bottom wall of the slot in the slot, so that the through hole is connected to the welding window; S4: forming wiring on the wall of the through hole, the bottom wall of the slot, the side wall of the slot, and the second surface, and the wiring is electrically connected to the solder window and the pad. 6 . The manufacturing method of the wafer level chip packaging structure according to claim 5 , wherein the aspect ratio k of the sidewall of the groove is approximately equal to 2.75. 7 . The manufacturing method of the wafer-level chip packaging structure according to claim 5 , wherein the trapezoidal grooves are one-stage or multi-stage trapezoidal grooves. 8 .