CN107045858B - Driving method of liquid crystal display panel and liquid crystal display panel - Google Patents
Driving method of liquid crystal display panel and liquid crystal display panel Download PDFInfo
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- CN107045858B CN107045858B CN201611110256.3A CN201611110256A CN107045858B CN 107045858 B CN107045858 B CN 107045858B CN 201611110256 A CN201611110256 A CN 201611110256A CN 107045858 B CN107045858 B CN 107045858B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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Abstract
The invention discloses a driving method of a liquid crystal display panel and the liquid crystal display panel, firstly dividing each sub-pixel unit in the liquid crystal display panel into a plurality of areas arranged along the extending direction of a data line, then loading grid scanning signals with different pulse widths to each area, and specifically loading grid scanning signals with gradually reduced pulse widths to grid lines connected with each sub-pixel unit in each area according to the sequence of the distance between the connection point between the sub-pixel unit and the data line and the input end of the data signal from far to near; and when a grid scanning signal is loaded on each grid, each data line is adopted to charge each sub-pixel unit connected with the grid line, the charging time length is changed according to the pulse width of the grid scanning signal, so that the electric quantity keeping time length of each sub-pixel in a region which is farther from the input end of the data signal is ensured to be relatively longer, and the problems of display color cast and the like caused by insufficient charging at the tail end due to overlarge load of the data line under the condition of high resolution are solved.
Description
Technical Field
The present invention relates to the field of display, and more particularly, to a driving method of a liquid crystal display panel and a liquid crystal display panel.
Background
Currently, a liquid crystal display device generally includes a liquid crystal display panel in which a plurality of pixels are arranged in a matrix form, and a driving circuit including a gate driving circuit that drives gate lines and a data driving circuit that drives data lines. In order to reduce the cost of the liquid crystal display device, it is generally desired to reduce the number of output channels of the data driving circuit while maintaining the resolution. Based on this, as shown in fig. 1, a demultiplexer 01(Demux) is used in the liquid crystal display panel to connect every three data lines to one data signal input terminal S1 or S2, and one data signal input terminal is connected to one output channel of the data driving circuit, so that the output channels of the data driving circuit can be reduced to one third.
When the multichannel distributor is adopted to charge the pixels, the grid lines are opened line by line, clock pulse signals are loaded to each clock control signal line in sequence, and data signals are loaded to each data line connected with the same multichannel distributor in a time-sharing mode, so that one line of pixels is charged. For example as shown in FIG. 2When the Gate line Gate 1 is turned on, clock control signal lines CKH R, CKH G, and CKH B connected to the demultiplexer are sequentially loaded with clock pulse signals. And charges the pixel R1 when the clock signal is applied to CKH R, charges the pixel G1 when the clock signal is applied to CKH G, and charges the pixel B1 when the clock signal is applied to CKH B. The charge retention periods of the pixels R1, G1, and B1 are tR，tG，tB. When the Gate line Gate n is turned on, the above operation is repeated to charge the pixels Rn, Gn, and Bn.
As can be seen from the above description of the conventional display mode, although the clock pulse signals with the same pulse width are applied to the clock control signal lines, the charging time for charging the pixels R, G, B when the clock pulse signals are applied is the same, but the clock pulse signals are sequentially applied to the clock control signal lines CKH R, CKH G, CKH B, that is, the start times of the clock pulse signals are not the same, so that after the clock pulse signals are changed to low level, the pixels are still in the low-charge state due to the delay (loading) effect in the circuit. That is, since the charging start time of each pixel is the on time of the CKH pulse signal and the end time is the off time of the gate line, the actual charging time of each pixel is different, i.e. tR>tG>tB. Moreover, under the condition of low resolution (low PPI), the existing display mode can meet the charging requirements of the pixels R, G and B, but when the resolution is high (high PPI), a delay problem (RC loading) is caused due to an excessive load of the data line, although the clock control signal line loads the clock pulse signal with the same pulse width, the charging duration of the data line connected to each pixel R, G, B when the clock pulse signal is loaded is the same, but since the delay of the data line at the far end is greater than the delay of the near end, the charging duration requirement of the data line at the far end is greater than the near end requirement, which aggravates the condition that the pixel charging of each area in the liquid crystal display panel is inconsistent, and causes the problem of color cast of the display effect. As shown in fig. 3, the end of the data line is more heavily loaded than the beginning, where the beginning refers to the end where the signal is initially loaded and the end refers to the farthest end where the signal can reach. Thus, it is possible to provideThe problems of color shift at the end of the data line are particularly serious.
Therefore, how to solve the problem of color shift of display caused by an excessive load of a data line under the condition of high resolution is a problem which needs to be solved in the field.
Disclosure of Invention
The embodiment of the invention provides a driving method of a liquid crystal display panel and the liquid crystal display panel, which are used for solving the problems of display color cast and the like caused by overlarge load of a data line.
The embodiment of the invention provides a driving method of a liquid crystal display panel, wherein the liquid crystal display panel comprises the following steps: the pixel structure comprises a plurality of grid lines, a plurality of data lines and a plurality of sub-pixel units, wherein the data lines are arranged in an insulated and intersected manner with the grid lines; each of the sub-pixel units is divided into a plurality of regions arranged along an extending direction of the data line, and the driving method includes:
loading grid scanning signals with gradually reduced pulse width to the grid lines connected with the sub-pixel units in each region according to the sequence of the distance between the connection point between the sub-pixel units and the data line and the data signal input end from far to near, and loading grid scanning signals with the same pulse width to the grid lines connected with the sub-pixel units in the same region;
and charging each sub-pixel unit connected with the grid line by using each data line while loading a grid scanning signal to each grid, wherein the charging time length is changed according to the pulse width of the grid scanning signal.
The embodiment of the invention also provides a liquid crystal display panel which is driven by any one of the driving methods provided by the embodiment of the invention.
The invention has the following beneficial effects:
according to the driving method of the liquid crystal display panel and the liquid crystal display panel provided by the embodiment of the invention, each sub-pixel unit in the liquid crystal display panel is divided into a plurality of areas arranged along the extending direction of a data line, then grid scanning signals with different pulse widths are loaded to each area, and specifically, grid scanning signals with gradually reduced pulse widths are loaded to grid lines connected with each sub-pixel unit in each area according to the sequence from far to near of the distance between the connecting point between the sub-pixel unit and the data line and the input end of the data signal; and when a grid scanning signal is loaded on each grid, each data line is adopted to charge each sub-pixel unit connected with the grid line, the charging time length is changed according to the pulse width of the grid scanning signal, so that the electric quantity keeping time length of each sub-pixel in a region which is farther from the input end of the data signal is ensured to be relatively longer, and the problems of display color cast and the like caused by insufficient charging at the tail end due to overlarge load of the data line under the condition of high resolution are solved.
Drawings
FIG. 1 is a schematic diagram of a prior art LCD panel;
FIG. 2 is a timing diagram illustrating a driving method of a prior art LCD panel;
FIG. 3 is a load equivalent diagram of a data line in the prior art;
fig. 4 is a schematic diagram illustrating a driving method of a liquid crystal display panel according to an embodiment of the invention;
fig. 5 is a second schematic diagram of a driving method of a liquid crystal display panel according to an embodiment of the invention;
FIG. 6 is a timing diagram illustrating a driving method of a liquid crystal display panel according to an embodiment of the present invention;
fig. 7 is a second timing chart of the driving method of the liquid crystal display panel according to the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 4, the liquid crystal display panel according to the embodiment of the present invention includes: a plurality of grid lines Gate a, Gate B and Gate c, a plurality of Data lines Data R, Data G and Data B which are arranged in an insulated and intersected manner with the grid lines Gate a, Gate B and Gate c, and a plurality of sub-pixel units R, G or B which are arranged in an array manner; each of the sub-pixel cells R a, R B, R C, G a, G B, G C, B a, B B, B C is divided into a plurality of regions A, B or C aligned along the extending direction of the Data lines Data R, Data G, and Data B. The driving method provided by the embodiment of the invention specifically comprises the following steps:
as shown in fig. 4, in order from far to near the connection points between the sub-pixel cells R a, R B, R c, G a, G B, G c, B a, B B, B c and the Data lines Data R, Data G and Data B and the Data signal input terminal S, gate scan signals with gradually reduced pulse widths are applied to the Gate lines Gate a, Gate b and Gate C connected to the sub-pixel units R a, R b, R C, G a, G b, G C, B a, B b and B C in each region A, B or C, and Gate scanning signals with the same pulse width are loaded on the Gate lines Gate a, Gate b or Gate c connected with the sub-pixel units R a, G a, B a or R b, G b, B b or R c, G c and B c in the same area;
while a Gate scan signal is applied to each Gate a, Gate B, or Gate c, each sub-pixel unit R a, Ga, B a, or R B, G B, B B, or R c, G c, B c connected to the Gate line Gate a, Gate B, or Gate c is charged with each Data line Data R, Data G, and Data B, and the charging time period varies according to the pulse width of the Gate scan signal.
In fig. 4, the description is given taking as an example that each sub-pixel unit is divided into three regions A, B, C arranged along the extending direction of the Data lines Data R, Data G, and Data B, and the number of the region division is not limited in the specific implementation. For example, in the liquid crystal display panel shown in fig. 4, since the Data signal input terminal S is located at the bottom of the Data lines Data R, Data G, and Data B, the region a is farthest from the Data signal input terminal S, and the pulse width of the Gate scanning signal applied to the Gate line Gate a in the region a is the largest; the region C is closest to the data signal input terminal S, and the pulse width of the Gate scanning signal applied to the Gate line Gate b in the region C is the smallest. When the Gate scanning signal is loaded on the Gate line Gate a in the region a, each Data line Data R, Data G and Data B charges each sub-pixel unit R a, G a and B a in the region a, and the maximum charging time is the pulse width duration of the Gate scanning signal; similarly, when the Gate line Gate C in the region C is loaded with the Gate scan signal, each of the Data lines Data R, Data G, and Data B charges each of the sub-pixel units R C, G C, and B C in the region C, and the maximum charging time is the pulse width duration of the Gate scan signal. Therefore, the charging period of each sub-pixel unit R a, G a, B a in the region a is the longest, and the charging period of each sub-pixel unit R C, G C, B C in the region C is the shortest.
In this way, it can be ensured that the charge holding time period of each sub-pixel unit in the region farther from the data signal input terminal S is relatively longer, thereby improving the problem of display color shift and the like due to insufficient charging of the end due to excessive load of the data line in the case of high resolution.
In practical implementation, in the above driving method provided by the embodiment of the present invention, the liquid crystal display panel may be divided into equal regions, that is, each region A, B, C has the same number of rows of sub-pixel units. At this time, according to the sequence from the far to the near of the distance between the connection point between the sub-pixel unit and the data line and the data signal input end, the gate scanning signal with the gradually decreasing pulse width is applied to the gate line connected to each sub-pixel unit in each region, which may specifically adopt the following manner:
and loading grid scanning signals with reduced pulse width equal difference on grid lines connected with the sub-pixel units in each region according to the sequence of the distance between the connection point between the sub-pixel units and the data line and the data signal input end from far to near.
For example, in the case of the liquid crystal display panel shown in fig. 4, the regions A, B and C have three rows of sub-pixel units, respectively, and the difference between the pulse widths of the Gate scanning signals applied to the Gate lines Gate a in the region a and the Gate scanning signals applied to the Gate lines Gate B in the region B is equal to the difference between the pulse widths of the Gate scanning signals applied to the Gate lines Gate B in the region B and the pulse widths of the Gate scanning signals applied to the Gate lines Gate C in the region C.
Of course, in specific implementation, the area division of the liquid crystal display panel is not limited to the above-mentioned equal areas, and the area division of the liquid crystal display panel may also be performed according to the severity of the data signal delay, for example, in a portion farther from the data signal input end, the density of the area division is greater, that is, in a portion farther from the data signal input end, the signal delay is more severe, so that, for a portion where the number of rows of the sub-pixel units is less, a gate scanning signal with a longer pulse width is applied to the area with the severe signal delay, so as to ensure that the data line can have an electric quantity holding time with a sufficient time length for each sub-pixel unit in the area.
In practical implementation, in the above driving method provided by the embodiment of the present invention, the scanning order of the gate lines in the liquid crystal display panel may be as follows: and in each frame of display time, sequentially loading a grid scanning signal to each grid line according to the sequence of the distance between the connecting point between the sub-pixel unit and the data line and the data signal input end from far to near. For example, in the liquid crystal display panel shown in fig. 4, the gate scanning signals may be sequentially applied to the respective gate lines in the order from top to bottom. Of course, the opposite is also possible, and the description is not repeated herein.
Further, in order to reduce the cost of the liquid crystal display panel, the number of output channels of the data driving circuit may be reduced while maintaining the resolution using a demultiplexer. Specifically, in the driving method of the liquid crystal display panel according to the embodiment of the present invention, as shown in fig. 5, in the liquid crystal display panel, a plurality of sub-pixel units R a, G a, B a or R b, G b, B b or R c, G c, B c of different colors connected to the same Gate line Gate a, Gate b or Gate c constitute one pixel unit; each data line charging a plurality of sub-pixel cells R a, G a, B a or R b, G b, B b or R c, G c, B c with different colors is connected to one data signal input terminal S1 through the demultiplexer 10; each demultiplexer 10 has a plurality of control terminals corresponding to a plurality of sub-pixel units R a, G a, B a or R B, G B, B B or R c, G c, B c of different connected colors, and each control terminal is connected to a corresponding clock control signal line for controlling the charging time of the sub-pixel units of different colors, for example, the sub-pixel units in fig. 5 include three sub-pixel units of red R, green G, and blue B; the clock control signal line includes: the first signal line CKH R is used for controlling the charging time of the red sub-pixel unit, the second signal line CKH G is used for controlling the charging time of the green sub-pixel unit, and the third signal line CKH B is used for controlling the charging time of the blue sub-pixel unit.
Based on this, the driving method provided in the embodiment of the present invention may further include:
and loading a clock signal with the pulse width changing according to the pulse width of the grid scanning signal to each clock control line in sequence while loading the grid scanning signal to each grid line Gate a, Gate b or Gate c.
In specific implementation, when a Gate scanning signal is applied to one Gate line Gate a, Gate B, or Gate c, as shown in fig. 5, clock signals with the same pulse width may be sequentially applied to each clock control signal line, for example, when a Gate scanning signal is applied to the Gate line Gate a in the region a in fig. 5, clock signals with the same pulse width are sequentially applied to the first signal line CKH R, the second signal line CKH G, and the third signal line CKH B; the same holds true for the region B and the region C, and when a Gate scan signal is applied to one Gate line, the sum of the pulse widths of the clock signals applied to the respective clock control signal lines may be equal to the pulse width of the Gate scan signal applied to the Gate line, for example, when a Gate scan signal is applied to the Gate line Gate a in the region a, the pulse widths of the clock signals applied to the first signal line CKHR, the second signal line CKH G, and the third signal line CKH B are one third of the Gate scan signal, and the same holds true for the region B and the region C.
Thus, in the above driving method according to the embodiment of the present invention, as shown in fig. 6, for the clock signals of which the first signal line CKHR, the second signal line CKH G and the third signal line CKH B are loaded with asymmetric pulse widths at different times in the timing sequence, the clock signals of which the loaded pulse widths are symmetrically distributed with respect to the clock signals of which the loaded pulse widths are shown by the dotted lines, the unutilized time ② having the sufficient charge retention time period in the region C can be supplemented to the position of the charge retention time period ① lacking in charge in the region a, so as to improve the problem of insufficient charge in the region a.
In practical implementation, when the demultiplexer is used to save the output channels of the data driving circuit in the above driving method provided by the embodiment of the present invention to reduce the cost, the problem that the charge retention time periods of the sub-pixel units constituting the same pixel unit are not the same is caused, and in the case of high resolution, the situation of insufficient charging easily occurs at the sub-pixel unit with the shortest charge retention time period.
Based on this, in the driving method provided in the embodiment of the present invention, while loading the gate scan signal to each gate line, the clock signals with pulse widths varying according to the pulse width of the gate scan signal are sequentially loaded to each clock control line, and specifically, the following method may be adopted to alleviate the problem of insufficient charging caused by inconsistent electric quantity holding durations of the sub-pixel units:
while loading a Gate scan signal to one Gate line Gate a, Gate B, or Gate C, clock signals with gradually increasing pulse widths may be sequentially loaded to each clock control signal line, for example, in fig. 7, when loading a Gate scan signal to the Gate line Gate a in the region a, clock signals are sequentially loaded to the first signal line CKH R, the second signal line CKH G, and the third signal line CKH B, and the pulse widths of the clock signals are gradually increased, and so on for the region B and the region C. When a Gate scanning signal is applied to one Gate line Gate a, Gate b, or Gate c, the sum of the pulse widths of the clock signals applied to the respective clock control signal lines may be equal to the pulse width of the Gate scanning signal applied to the Gate line.
Specifically, when clock signals with gradually increasing pulse widths are sequentially loaded to the clock control signal lines, clock signals with increasing pulse widths and the like can be sequentially loaded to the clock control signal lines, for example, in fig. 7, clock signals with increasing pulse widths and the like are sequentially loaded to the first signal line CKH R, the second signal line CKH G, and the third signal line CKH B; the pulse width of the clock signal loaded on the second signal line CKH G may be equal to one third of the pulse width of the gate scan signal, so that the difference between the pulse widths of the clock signal loaded on the second clock control signal line CKH G and the clock signal loaded on the first signal line CKH R is equal to the difference between the pulse widths of the clock signal loaded on the third signal line CKH B and the clock signal loaded on the second signal line CKH G.
Thus, in the above-described driving method according to the embodiment of the present invention, as shown in fig. 7, although the pulse widths of the clock signals applied to the first signal line CKHR, the second signal line CKH G, and the third signal line CKH B are different, the pulse widths of the clock signals applied to the first signal line CKH R, the second signal line CKH G, and the third signal line CKH B at different timings in the sequence also exhibit an asymmetric distribution, and the clock signals symmetrically distributed with respect to the applied pulse width shown by the dotted line can supplement the unused time ② having a sufficient charge retention period in the region C to the position of the charge retention period ① lacking in the charge shortage in the region a to improve the problem of the charge shortage in the region a.
Based on the same inventive concept, the embodiment of the invention provides a liquid crystal display panel, and the liquid crystal display panel is driven by any one of the driving methods provided by the embodiment of the invention.
According to the driving method of the liquid crystal display panel and the liquid crystal display panel provided by the embodiment of the invention, each sub-pixel unit in the liquid crystal display panel is divided into a plurality of areas arranged along the extending direction of a data line, then grid scanning signals with different pulse widths are loaded to each area, and specifically, grid scanning signals with gradually reduced pulse widths are loaded to grid lines connected with each sub-pixel unit in each area according to the sequence from far to near of the distance between the connecting point between the sub-pixel unit and the data line and the input end of the data signal; and when a grid scanning signal is loaded on each grid, each data line is adopted to charge each sub-pixel unit connected with the grid line, the charging time length is changed according to the pulse width of the grid scanning signal, so that the electric quantity keeping time length of each sub-pixel in a region which is farther from the input end of the data signal is ensured to be relatively longer, and the problems of display color cast and the like caused by insufficient charging at the tail end due to overlarge load of the data line under the condition of high resolution are solved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (5)
1. A method of driving a liquid crystal display panel, the liquid crystal display panel comprising: the pixel structure comprises a plurality of grid lines, a plurality of data lines and a plurality of sub-pixel units, wherein the data lines are arranged in an insulated and intersected manner with the grid lines; each of the sub-pixel units is divided into a plurality of regions arranged along an extending direction of the data line, and the driving method includes:
loading grid scanning signals with gradually reduced pulse width to the grid lines connected with the sub-pixel units in each region according to the sequence of the distance between the connection point between the sub-pixel units and the data line and the data signal input end from far to near, and loading grid scanning signals with the same pulse width to the grid lines connected with the sub-pixel units in the same region;
loading a grid scanning signal on each grid line, and simultaneously charging each sub-pixel unit connected with the grid line by using each data line, wherein the charging time length is changed according to the pulse width of the grid scanning signal;
wherein, in the liquid crystal display panel, the sub-pixel units are divided into three regions arranged along an extending direction of the data lines, and each of the regions has a plurality of rows of the sub-pixel units;
in the liquid crystal display panel, a plurality of sub-pixel units which are connected with the same grid line and have different colors form a pixel unit; each data line for charging a plurality of sub-pixel units with different colors is connected with one data signal input end through a multi-way distributor; each demultiplexer is provided with a plurality of control ends which correspond to the connected sub-pixel units with different colors one by one, and each control end is correspondingly connected with a clock control signal line used for controlling the charging duration of the sub-pixel units with different colors; the method further comprises the following steps: loading a gate scanning signal to each gate line, and simultaneously loading a clock signal with a pulse width changing according to the pulse width of the gate scanning signal to each clock control line in sequence;
loading a gate scanning signal to each gate line, and simultaneously loading a clock signal with a pulse width changing according to the pulse width of the gate scanning signal to each clock control line in sequence, specifically comprising: loading a gate scanning signal on one gate line, and simultaneously loading clock signals with gradually increasing pulse widths on each clock control signal line in sequence, wherein the sum of the pulse widths of the clock signals loaded on each clock control signal line is equal to the pulse width of the gate scanning signal loaded on the gate line;
the loading of clock signals with gradually increasing pulse widths to each clock control signal line in sequence specifically includes: and sequentially loading clock signals with increased pulse width equal difference to each clock control signal line.
2. The driving method according to claim 1, wherein in the liquid crystal display panel, each of the regions has the same number of rows of the sub-pixel units; the loading, to the gate line connected to each of the sub-pixel units in each of the regions, a gate scan signal with a gradually decreasing pulse width in an order from a far distance to a near distance between a connection point between the sub-pixel unit and a data line and a data signal input end specifically includes:
and loading grid scanning signals with reduced pulse width equal difference to the grid lines connected with the sub-pixel units in each region according to the sequence of the distance between the connection point between the sub-pixel units and the data line and the data signal input end from far to near.
3. The driving method according to claim 2, further comprising: and in each frame of display time, sequentially loading a grid scanning signal to each grid line according to the sequence of the distance between the connecting point between the sub-pixel unit and the data line and the data signal input end from far to near.
4. The driving method according to claim 1, wherein in the liquid crystal display panel, the sub-pixel units include three sub-pixel units of red, green, and blue; the clock control signal line includes: the first signal line is used for controlling the charging time of the red sub-pixel unit, the second signal line is used for controlling the charging time of the green sub-pixel unit, and the third signal line is used for controlling the charging time of the blue sub-pixel unit;
the loading of the clock signal with the pulse width changed according to the pulse width of the gate scanning signal to each clock control line in sequence while loading the gate scanning signal to each gate line specifically includes:
and loading a gate scanning signal on one gate line, and simultaneously loading clock signals with the pulse width being increased in an equal difference manner on the first signal line, the second signal line and the third signal line in sequence, wherein the pulse width of the clock signal loaded on the second signal line is equal to one third of the pulse width of the gate scanning signal.
5. A liquid crystal display panel characterized by being driven by the driving method according to any one of claims 1 to 4.
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