CN106997752B

CN106997752B - Source driver for display device

Info

Publication number: CN106997752B
Application number: CN201710053150.2A
Authority: CN
Inventors: 李载官
Original assignee: Silicon Works Co Ltd
Current assignee: LX Semicon Co Ltd
Priority date: 2016-01-21
Filing date: 2017-01-22
Publication date: 2021-05-14
Anticipated expiration: 2037-01-22
Also published as: KR102694705B1; CN106997752A; KR20170087832A

Abstract

The present invention relates to a source driver for a display device, which can eliminate a delay of a digital-to-analog converter (DAC), and in which a portion of a gamma line for supplying a gamma voltage to the DAC is designed to have a large width and a small resistance value. Before driving the first gamma voltage to a level corresponding to display data, the DAC may select an adjacent gamma line having a small resistance value and drive the second gamma voltage, thereby eliminating a delay time.

Description

Source driver for display device

Technical Field

The present invention relates to a source driver, and more particularly, to a source driver for a display device, which is capable of eliminating an output delay of a Digital Analog Converter (DAC).

Background

The flat panel display device includes a source driver that provides a source signal to display on a display panel. The source driver supplies a source signal corresponding to display data supplied from an external source to the display panel.

The Display panel may include a Liquid Crystal Display (LCD) panel or a Light Emitting Diode (LED) panel. The LCD panel displays a screen using a shutter operation of liquid crystal at each pixel, and the LED panel displays a screen using light emission of LEDs at each pixel.

Recently, display devices are required to have high resolution. However, an increase in resolution may reduce the driving time for each pixel or horizontal line. Therefore, in order to compensate for the short driving time, the source driver must eliminate the output delay or particularly the output delay of the DAC. However, it is difficult to design a source driver capable of eliminating output delay.

In particular, the delay time of the source driver or DAC must be overcome in an IC (integrated circuit) in addition to the load of the display panel.

Disclosure of Invention

Various embodiments relate to a source driver for a display device, which includes a gamma line (i.e., a gamma line) a portion of which is designed to have a small resistance value and a large width, and can eliminate an output delay of a DAC included therein by using the gamma line having the small resistance value.

Further, various embodiments relate to a source driver for a display device, in which one of gamma lines included in one group is configured to have a small resistance value, and the source driver roughly drives the gamma line having the small resistance value and then finely drives a gamma voltage corresponding to display data, thereby eliminating an output delay of a DAC.

In addition, various embodiments relate to a source driver for a display device that roughly drives an interpolation voltage of a certain level using a reference gamma voltage corresponding to a group corresponding to display data and then finely drives a gamma voltage corresponding to the display data, thereby eliminating an output delay of a DAC.

In one embodiment, a source driver for a display device may include: a decoder connected to the plurality of gamma lines to supply gamma voltages and configured to select and drive a first gamma voltage corresponding to display data; and a buffer configured to drive the first gamma voltage of the decoder and output the driven voltage as a source voltage. Among the plurality of gamma lines, a plurality of gamma lines for supplying gamma voltages corresponding to consecutive gray scale values may be divided into a group, a second gamma line among the plurality of gamma lines included in the group may have a larger line width and thus a smaller resistance value than the other gamma lines, and the decoder may select and drive a second gamma voltage of the second gamma line and then select and drive a first gamma voltage of a first gamma line corresponding to the display data in response to the display data corresponding to the group.

In another embodiment, a source driver for a display device may include: a decoder connected to the plurality of gamma lines to supply gamma voltages and configured to select and drive a first gamma voltage corresponding to display data; and a buffer configured to drive the first gamma voltage of the decoder and output the driven voltage as a source voltage. Among the plurality of gamma lines, a plurality of gamma lines for supplying gamma voltages corresponding to consecutive gray scale values may be divided into a group, a second gamma line among the plurality of gamma lines included in the group may have a larger line width and thus a smaller resistance value than the other gamma lines, and the decoder may select and drive a second gamma voltage of the second gamma line and then select and drive a first gamma voltage of a first gamma line corresponding to the display data in response to the display data corresponding to the group.

In another embodiment, a source driver for a display device may include: a decoder connected to a first group of gamma lines to supply gamma voltages corresponding to consecutive gray scale values in a first range and connected to a second group of reference gamma lines to supply reference gamma voltages in a second range different from the first range, the decoder including a plurality of transmission lines and configured to determine first gamma voltages corresponding to display data; and a buffer configured to drive the first gamma voltages applied through the plurality of transmission lines and output the driven voltages as source voltages. A second gamma line included in the plurality of gamma lines in the first group may have a larger line width than the other gamma lines, and thus have a smaller resistance value than the other gamma lines, and the decoder may drive the second gamma voltages by supplying the second gamma voltages of the second gamma lines to the plurality of transmission lines in response to the display data corresponding to the first range, driving a first gamma voltage of a first gamma line corresponding to the display data by supplying the first gamma voltage to the plurality of transmission lines, and deciding the first gamma voltage by supplying a first reference gamma voltage to the plurality of transmission lines or distributing and supplying the first reference gamma voltage and a second reference gamma voltage having a higher gray level than the first reference gamma voltage to the plurality of transmission lines in response to display data corresponding to the second range.

According to an embodiment of the present invention, a portion of a gamma line for transmitting a gamma voltage may be designed to have a large width and a small resistance value, and the gamma line having the small resistance value may be driven before driving the gamma voltage corresponding to display data. Accordingly, the DAC can rapidly drive the gamma voltages corresponding to the display data and eliminate the output delay of the source driver.

Further, the DAC selecting the gamma voltages corresponding to the display data may roughly drive the gamma lines having a small resistance value among the gamma lines included in one group and then finely drive the gamma voltages corresponding to the display data, thereby eliminating output delays of the DAC and the source driver.

Further, the DAC selecting the gamma voltage corresponding to the display data roughly drives the interpolation voltage of a certain level using the reference gamma voltage and then finely drives the gamma voltage corresponding to the display data, thereby eliminating output delays of the DAC and the source driver.

Drawings

Fig. 1 is a diagram illustrating a source driver according to an embodiment of the present invention.

Fig. 2 is a circuit diagram showing a DAC of a source driving module according to an embodiment of the present invention.

Fig. 3 is a diagram showing a layout of γ lines applied to the embodiment of fig. 2.

Fig. 4 to 7 are diagrams for describing a method for driving a gamma voltage according to the embodiment of fig. 2.

Fig. 8 is a circuit diagram showing a DAC of a source driving module according to another embodiment of the present invention.

Fig. 9 is a diagram for describing an interpolation voltage and a layout of a gamma line applied to the embodiment of fig. 8.

Fig. 10 is a circuit diagram showing a DAC of a source driving module according to another embodiment of the present invention.

Fig. 11 is a diagram showing a layout of γ lines applied to the embodiment of fig. 10.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Terms used in the present specification and claims are not limited to typical dictionary definitions, but must be interpreted as meanings and concepts consistent with the technical idea of the present invention.

The embodiments described in the present specification and the configurations shown in the drawings are preferred embodiments of the present invention, and do not represent the entire technical idea of the present invention. Therefore, various equivalents and modifications capable of substituting the embodiments and configurations may be provided at the time of filing this application.

The source driver 100 for a display device receives display data from an external source (not shown), generates source signals corresponding to the display data, and outputs the source signals through a plurality of channels.

Referring to fig. 1, the source driver 100 includes a source driving module 102 and a γ circuit 108, and is manufactured as one chip. The source driver 100 may be designed such that the γ circuit 108 is disposed at the center of the chip and the source driving modules 102 are disposed at both sides of the γ circuit 108.

The source driving module 102 outputs a source signal by selecting and driving a gamma voltage corresponding to display data among gamma voltages supplied from the gamma circuit 108. For this operation, the source driving module 102 includes a latch, a level shifter, a DAC, and an output buffer.

The latch is used to latch display data including a plurality of bits input in series and provide the latched data in parallel, and the level shifter is used to adjust the level of the display data according to the input specification of the DAC.

The DAC is used to select gamma voltages corresponding to display DATA <7:0> and output the selected gamma voltages to the output buffer. The DAC will be described later with reference to fig. 2.

The output buffer is used for providing the source voltage from the DAC to the display panel.

A latch, a DAC, and an output buffer are implemented for each channel of the source driver, and a source voltage is output to the display panel through each channel.

The gamma circuit 108 supplies a gamma voltage corresponding to display data to the source driving module 102 at both sides of the source driving module 102, and supplies the gamma voltage to all channels of the source driving module 102 through a gamma line VGL formed through the gamma circuit 108 and the source driving module 102.

The gamma circuit 108 supplies a gamma voltage for gray scale. For example, when 256 gray levels are set, 256 γ voltages for representing the 256 gray levels are supplied from the γ circuit 108 to the source driving module 102 through the γ line VGL, as shown in fig. 2 and 3. In contrast, 64 reference γ voltages for representing 256 gray levels may be supplied from the γ circuit 108 to the source driving module 102 through the γ line VGL, as shown in fig. 8 and 9.

The embodiments of fig. 2 and 3 are based on the assumption that 256 gamma voltages are supplied to the DAC included in the source driving module 102. Fig. 2 illustrates a DAC comprising a decoder 10 and a buffer 12.

In fig. 2, the decoder 10 is configured to receive gamma voltages, VG < M +4>,. VGL < N >, VGL < N-1>,. through a plurality of gamma lines, VG < M +4>,. VGL < N >, VGL < N-1>,. and so on, VG < M +4>,. VG < N >, VG < N-1>, and so on, and select and drive the gamma voltage Vin corresponding to the display DATA <7:0 >. The buffer 12 is configured to drive the γ voltage Vin and output the driven voltage as the source voltage Vout.

Fig. 3 shows four gamma lines VGL < N +3>, VGL < N +2>, VGL < N +1> and VGL < N > corresponding to consecutive gray values and grouped in a plurality of gamma lines, and four gamma lines VGL < N +3>, VGL < N +1>, VGL < N +2>, VGL < N +1> and VGL < N > provide four gamma voltages VG < N +3>, VG < N +2>, VG < N +1> and VG < N >.

As shown in fig. 3, among a plurality of γ lines VGL < N +3>, VGL < N +2>, VGL < N +1>, and VGL < N > included in one group, the γ line VGL < N +2> has a larger line width than the other γ lines VGL < N +3>, VGL < N +1>, and VGL < N >. Accordingly, the γ line VGL < N +2> has a smaller resistance value than the other γ lines VGL < N +3>, VGL < N +1>, and VGL < N >. The other gamma lines VGL < N +3>, VGL < N +1>, and VGL < N > are designed to have the same width while having a smaller width than the gamma line VGL < N +2 >.

In the present embodiment, a plurality of γ lines, VGL < M +4>,. VGL < N >, VGL < N-1>,. may be divided into a plurality of groups, and each group may include one γ line having a larger line width than the other γ lines.

According to the above-described configuration, the decoder 10 selects and drives the gamma voltages VG < N +2> of the gamma lines VGL < N +2> in the group corresponding to the display DATA <7:0>, and then selects and drives the gamma voltages of the gamma lines corresponding to the display DATA <7:0 >.

The display DATA <7:0> may include coarse DATA and fine DATA. For example, the high-order five-bit DATA <7:2> of the display DATA DATA <7:0> may be defined as coarse DATA, and the low-order two-bit DATA <1:0> may be defined as fine DATA. The 5-bit coarse data may divide 256 γ lines into 64 groups.

The decoder 10 may select a group according to the coarse DATA <7:2> and select a specific voltage included in the group according to the fine DATA <1:0 >. The 2-bit fine data may divide four gamma lines included in the group.

Referring to fig. 4, an operation in which the decoder 10 selects and outputs the gamma voltage VG < N > in response to the display DATA <7:0> will be described.

When the DATA <7:0> is input, the decoder 10 recognizes the coarse DATA <7:2>, selects the gamma voltage VG < N +2> of the gamma line VGL < N +2> having a small resistance value and a large width among the gamma lines VGL < N +3>, VGL < N +2>, VGL < N +1> and VGL < N > included in the group corresponding to the coarse DATA <7:2>, and drives the gamma voltage Vin to the gamma voltage VG < N +2 >. The period is defined as a coarse period. The gamma voltages selected by the decoder 10 in the coarse period may be understood as the second gamma voltages.

After a predetermined time elapses, the decoder 10 selects the gamma voltage VG < N > of the gamma line VGL < N > corresponding to the fine DATA <1:0> and drives the gamma voltage Vin to the gamma voltage VG < N >. This period is defined as a fine period. The gamma voltages selected by the decoder 10 in the fine period may be understood as the first gamma voltages.

Since the gamma voltage VG < N +2> selected by the decoder 10 in the coarse period is supplied through the gamma line VGL < N +2> having a small resistance value, the gamma voltage VG < N +2> can be raised in a short time.

Accordingly, the decoder 10 may be coarsely driven to the gamma voltage VG < N +2> for a short time in the coarse period and then finely driven to the gamma voltage VG < N > in the fine period. Therefore, the gamma voltage Vin can reach the target level in a shorter time than the gamma voltage VG < N > that drives only the gamma line VGL < N > having a large resistance value.

Fig. 5 illustrates a coarse operation and a fine operation for selecting and outputting the gamma voltage VG < N +1> through the decoder 10 according to an embodiment of the present invention. Fig. 6 illustrates a coarse operation and a fine operation for selecting and outputting the gamma voltage VG < N +2> through the decoder 10 according to an embodiment of the present invention. Fig. 7 illustrates a coarse operation and a fine operation for selecting and outputting the gamma voltage VG < N +3> through the decoder 10 according to an embodiment of the present invention.

Referring to fig. 5 to 7, the decoder 10 according to the embodiment of the present invention raises the gamma voltage Vin to the gamma voltage VG < N +2> with a short delay time during the coarse period, and lowers or raises the gamma voltage VG < N +2> to the gamma voltages VG < N +1> and VG < N +3> as the target voltage or maintains the gamma voltage VG < N +2> during the fine period.

According to the present embodiment, the source driver can reduce the required delay time until the gamma voltage Vin input to the buffer 12 rises to a voltage level corresponding to the DATA <7:0 >.

Therefore, when the source driver and the DAC of the source driver are applied to a high resolution display device requiring a short driving time for each pixel or horizontal line, the source driver can output the output signal Vout with a short delay time.

Further, the present invention may be implemented as shown in fig. 8 and 9 in order to improve the output delay of the DAC when 64 reference gamma voltages corresponding to 256 gray levels are supplied from the gamma circuit 108 to the source driving module 102 through the reference gamma lines.

For this operation, the decoder 10 is connected to 64 reference γ lines, VGL < N +4>, VGL < N-4>, and includes four transmission lines Vin <3:0 >.

The decoder 10 may supply the first reference gamma voltage to the plurality of transmission lines in response to the display DATA <7:0>, or divide and supply the first reference gamma voltage and the second reference gamma voltage having a higher gray level than the first reference gamma voltage to the plurality of transmission lines, thereby deciding the first gamma voltage transmitted to the buffer 12 through the four transmission lines Vin <3:0 >.

In the embodiments of fig. 8 and 9, the first and second reference gamma voltages may be defined as voltages having adjacent gray scale values, and the first reference gamma voltage may be defined as a voltage having a gray scale value lower by one level than the second reference gamma voltage. For example, when the gamma voltage VG < N > is used as the first reference gamma voltage, the gamma voltage VG < N +4> may be understood as the second reference gamma voltage.

In the embodiments of fig. 8 and 9, the gamma voltage applied to the input side of the buffer 12 in the coarse period may be defined as the second gamma voltage, and the gamma voltage applied to the input side of the buffer 12 in the fine period may be defined as the first gamma voltage.

The buffer 12 drives the first gamma voltages applied through the four transmission lines Vin <3:0> and outputs the driven voltages as the source voltage Vout.

In order to determine the gamma voltages applied to the buffer 12, the decoder 10 may commonly transmit the first reference gamma voltage to the four transmission lines Vin <3:0> or distribute and transmit the first reference gamma voltage and the second reference gamma voltage to the four transmission lines Vin <3:0 >.

At this time, the decoder 10 may increase the number of transmission lines for outputting the second reference gamma voltage as the gray level of the gamma voltage increases.

This configuration will be described with reference to table 1 below.

< Table 1>

In table 1, interpolation voltages to be formed between the first reference gamma voltage VG < N > and the second reference gamma voltage VG < N +4> are defined as VG < N +1>, VG < N +2> and VG < N +3 >. In order for the buffer 12 to output the first reference gamma voltage VG < N > as the source voltage Vout, the decoder 10 provides the first reference gamma voltage VG < N > to each of the four transmission lines Vin <3:0 >.

In addition, in order for the buffer 12 to output the interpolation voltage VG < N +1> as the source voltage Vout, the decoder 10 supplies the first reference gamma voltage VG < N > to three transmission lines Vin <3>, Vin <2> and Vin <1>, and supplies the second reference gamma voltage VG < N +4> to one transmission line Vin <0 >. The voltage applied to the buffer 12 may be set to an average of the voltages distributed and supplied to the four transmission lines Vin <3:0 >. As a result, the interpolation voltage VG < N +1> may be applied to the buffer 12, and the buffer 12 may drive the interpolation voltage VG < N +1> to be output as the source voltage Vout.

In addition, in order for the buffer 12 to output the interpolation voltage VG < N +2> as the source voltage Vout, the decoder 10 supplies the first reference gamma voltage VG < N > to the two transmission lines Vin <3> and Vin <2>, and supplies the second reference gamma voltage VG < N +4> to the two transmission lines Vin <1> and Vin <0 >. As a result, the interpolation voltage VG < N +2> may be applied to the buffer 12, and the buffer 12 may drive the interpolation voltage VG < N +2> to be output as the source voltage Vout.

In order for the buffer 12 to output the interpolation voltage VG < N +3> as the source voltage Vout, the decoder 10 supplies the first reference gamma voltage VG < N > to one transmission line Vin <3>, and supplies the second reference gamma voltage VG < N +4> to three transmission lines Vin <2>, Vin <1>, and Vin <0 >. As a result, the interpolation voltage VG < N +3> may be applied to the buffer 12, and the buffer 12 may drive the interpolation voltage VG < N +3> to be output as the source voltage Vout.

In the embodiments of fig. 8 and 9, in the coarse period, the second gamma voltage may be driven to an interpolation voltage between the first reference gamma voltage and the second reference gamma voltage in response to a high order bit of the display data, and in the fine period, the first gamma voltage may be driven to the interpolation voltage or the first gamma voltage having a target level in response to a low order bit of the display data.

More specifically, the decoder 10 sequentially performs the coarse period and the fine period.

The decoder 10 performs a coarse period operation, that is, in response to a signal contained in the display DATA <7:0> and supplies the first reference gamma voltage VG < N > and the second reference gamma voltage V < GN +4> as a first combination to the transmission line Vin <3:0> and applies an interpolation voltage between the first reference gamma voltage and the second reference gamma voltage as a second gamma voltage to the buffer 12.

The first combination may be defined as a combination for presetting an interpolation voltage. For example, when the interpolation voltage VG < N +2> is set in the coarse period, the first combination may be described as a combination for providing the first reference voltage VG < N > to the two transmission lines Vin <3> and Vin <2> and providing the second reference gamma voltage VG < N +4> to the two transmission lines Vin <1> and Vin <0 >.

The interpolation voltage VG < M +2> selected to output the second gamma voltage set in the coarse period may have the smallest delay time. Due to the influence of parasitic capacitance, each of the four transmission lines Vin <3:0> has a unique delay time corresponding to the input voltage. The delay time of each interpolated voltage may be determined by the combined effect of the parasitic capacitors in the four transmission lines Vin <3:0 >. As a result, the interpolation voltage VG < N +2> of the three interpolation voltages VG < N +1>, VG < N +2> and VG < N +3> between the first reference gamma voltage VG < N > and the second reference gamma voltage VG < N +4> may have the smallest delay time. Further, the interpolation voltage VG < N +2> may be used as the interpolation voltage for the coarse period.

After the coarse period operation, the decoder 10 performs the fine period operation, that is, in response to the DATA included in the display DATA <7:0> and the first and second reference gamma voltages VG < N > and VG < N +4> are supplied as a second combination to the transmission line Vin <3:0> and the first gamma voltage is applied to the buffer 12.

For the coarse period, the decoder 10 may recognize the high-order bits DATA <7:2> as coarse DATA. That is, the decoder 10 may recognize the coarse DATA <7:2> and select the interpolation voltage VG < N +2> as the second gamma voltage for the coarse period. For the fine period, the decoder 10 may recognize the low-order bits DATA <1:0> as fine DATA. That is, the decoder 10 may recognize the fine DATA <1:0> and select one of the first reference gamma voltage VG < N > and the interpolation voltages VG < N +1>, VG < N +2> and VG < N +3> as the first gamma voltage for the fine period.

Therefore, in order to generate the interpolation voltage VG < N +2> as the second gamma voltage corresponding to the coarse DATA DATA <7:2> when the display DATA DATA <7:0> is input, the decoder 10 outputs VG < N >, VG < N +4> and VG < N +4> to the four transmission lines Vin <3:0>, and the buffer 12 drives and outputs the interpolation voltage VG < N +2> generated by the four inputs Vin <3:0> (i.e., VG < N >, VG < N +4> and VG < N +4 >). After a predetermined time elapses, the decoder 10 changes or maintains the voltages of the four transmission lines Vin <3:0> so as to generate a first reference gamma voltage VG < N > and one of interpolation voltages VG < N +1>, VG < N +2>, and VG < N +3> as a first gamma voltage corresponding to the fine DATA <1:0>, and the buffer 12 drives the first gamma voltage generated by the four inputs Vin <3:0> (i.e., VG < N >, VG < N +4>, and VG < N +4>) and outputs the driven voltage as the source voltage Vout.

Accordingly, in the embodiments of fig. 8 and 9, the decoder 10 may also sequentially perform the coarse period and the fine period and reduce a delay time required to raise the first γ voltage transmitted to the buffer 12 to a target level.

The embodiments of fig. 2 and 3 and the embodiments of fig. 8 and 9 may be incorporated into the embodiments of fig. 10 and 11.

For this embodiment, the decoder 10 is connected to a first group of γ lines for supplying γ voltages corresponding to consecutive gray scale values in a first range and a second group of γ lines for supplying reference γ voltages in a second range different from the first range, the decoder 10 includes a plurality of transmission lines Vin <3:0> and is configured to determine a first γ voltage corresponding to display DATA <7:0 >.

The buffer 12 drives the first gamma voltage applied through the transmission line Vin <3:0> and outputs the driven voltage as the source voltage Vout.

In the above-described configuration, the plurality of γ lines included in the first range may be exemplified as VGL <255> to VGL <246> of fig. 10 and 11, and the first group of γ lines may be exemplified as VGL <255> to VGL <251 >.

The second gamma line of the first group of gamma lines VGL <255> to VGL <251> may be exemplified as VGL <253 >. Since the γ line VGL <253> has a larger line width than the other γ lines in the first group, the γ line VGL <253> has a smaller resistance value than the other γ lines.

In the above-described configuration, the plurality of reference γ lines included in the second range may be exemplified as reference γ lines VGL < N +4>, VGL < N > and VGL < N-4> of fig. 10 and 11, interpolation voltages between the γ voltage VG < N +4> of the reference γ line VGL < N +4> and the γ voltage VG < N > of the reference γ line VGL < N > may be represented by VG < N +3>, VG < N +2> and VG < N +1>, respectively, and interpolation voltages between the γ voltage VG < N > of the reference γ line VGL < N > and the γ voltage VG < N-4> of the reference γ line VGL < N-4> may be represented by VG < N-1>, VG < N-2> and VG < N-3>, respectively.

The decoder 10 decodes the display DATA by responding to the display DATA <7:0> the second gamma voltage (e.g., VG <253>) of the second gamma line (e.g., VGL <253>) is supplied to the transmission line Vin <3:0> to drive the second gamma voltage, and then the first gamma voltage of the first gamma line corresponding to the display DATA <7:0> is driven by supplying the first gamma voltage to the transmission line Vin <3:0>, as in the embodiments of fig. 2 and 3.

Further, the decoder 10 may decode the display DATA by responding to the display DATA <7:0>, the first reference gamma voltage is supplied to the transmission line Vin <3:0> or the first reference gamma voltage (e.g., VG < N >) of the first reference gamma line (e.g., VGL < N >) and the second reference gamma voltage (e.g., VG < N +4>) of the second reference gamma line (e.g., VGL < N +4>) having a higher gray level than the first reference gamma voltage are distributed and supplied to the transmission line Vin <3:0>, to determine the first gamma voltage, as in the embodiments of fig. 8 and 9.

The configuration and operation of the decoder 10 corresponding to the display DATA <7:0> included in the first range may be understood as the embodiment of fig. 2 and 3, and the configuration and operation of the decoder 10 corresponding to the display DATA <7:0> included in the second range may be understood as the embodiment of fig. 8 and 9. Therefore, the description of the repetitive configuration and operation is omitted here.

When the source driver and the DAC of the source driver according to the embodiment of the present invention are applied to a high resolution display device requiring a short driving time for each pixel or horizontal line, the source driver and the DAC may output the output signal Vout with a short delay time.

In addition, since the number of voltage lines for supplying the γ voltage can be reduced, the chip size can be reduced, so that convenience can be provided in designing the driving circuit.

While various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely exemplary. Accordingly, the disclosure described herein should not be limited based on the described embodiments.

Claims

1. A source driver for a display device, comprising:

a first gamma line to which a first gamma voltage is applied;

a second gamma line having a width wider than that of the first gamma line and to which a second gamma voltage is applied;

a decoder configured to receive the first and second gamma voltages, and output the second gamma voltage corresponding to an input of display data having a gray value corresponding to the first gamma voltage, and output the first gamma voltage after outputting the second gamma voltage;

a buffer configured to output a source voltage by using the first gamma voltage; and

a transmission line configured to transmit the second gamma voltage and the first gamma voltage of the decoder to the buffer,

wherein a second delay time required to output the second gamma voltage from the decoder is shorter than a first delay time required to output the first gamma voltage from the decoder due to a difference in width between the first gamma voltage and the second gamma voltage.

2. The source driver of claim 1, wherein the decoder outputs the second gamma voltage through coarse data included in the display data, and outputs the first gamma voltage through fine data included in the display data.

3. The source driver of claim 2, wherein the decoder recognizes a part of bits included in the display data as the coarse data and recognizes other bits as the fine data.

4. The source driver of claim 3, wherein the decoder recognizes a lower two bits among bits contained in the display data as the fine data and recognizes other bits as the coarse data.

5. The source driver of claim 1, wherein,

wherein the source driver includes a plurality of gamma lines divided into a plurality of groups,

wherein each group includes the first and second gamma lines, an

Wherein the decoder outputs the second gamma voltage and the first gamma voltage by selecting a group corresponding to coarse data of the display data when the display data is input.

6. A source driver for a display device, comprising:

a first reference gamma line to which a first reference gamma voltage is applied;

a second reference gamma line to which a second reference gamma voltage higher than the first reference gamma voltage is applied;

a plurality of transmission lines;

a decoder configured to receive the first reference gamma voltage and the second reference gamma voltage and distributively output the first reference gamma voltage and the second reference gamma voltage to the plurality of transmission lines; and

a buffer configured to receive a second gamma voltage and a first gamma voltage through distributed outputs of the first reference gamma voltage and the second reference gamma voltage through the plurality of transmission lines and output a source voltage by using the first gamma voltage,

wherein a second delay time for the second gamma voltage to be transmitted to the buffer is shorter than a first delay time for the first gamma voltage to be transmitted to the buffer, an

Wherein the decoder changes a state in which the first reference gamma voltage and the second reference gamma voltage are distributively output to the plurality of transmission lines when the display data having the gray scale value corresponding to the first gamma voltage is input, such that the first gamma voltage is applied after the second gamma voltage is applied to the buffer.

7. The source driver of claim 6, wherein the decoder gradually increases the number of transmission lines for outputting the second reference gamma voltage as the level of the first gamma voltage increases.

8. The source driver of claim 6, wherein the decoder performs a coarse period operation in which the first reference gamma voltage and the second reference gamma voltage are distributively output as a first combination to the plurality of transmission lines corresponding to coarse data included in the display data, and then performs a fine period operation in which the first reference gamma voltage and the second reference gamma voltage are distributively output as a second combination to the plurality of transmission lines corresponding to fine data included in the display data.

9. The source driver of claim 8, wherein the decoder recognizes a part of bits included in the display data as the coarse data and recognizes other bits as the fine data.

10. The source driver of claim 6, wherein the decoder performs a coarse-period operation of distributively outputting the first and second reference gamma voltages to the plurality of transmission lines such that the second gamma voltage has an intermediate value between the first and second reference gamma voltages, and then performs a fine-period operation of distributively outputting the first and second reference gamma voltages to the plurality of transmission lines such that the first gamma voltage corresponds to the gray scale value.

11. A source driver for a display device, comprising:

a first gamma line to which a first gamma voltage is applied;

a plurality of transmission lines;

a decoder configured to receive the first gamma voltage, the second gamma voltage, the first reference gamma voltage, and the second reference gamma voltage, and when display data is input, output the second gamma voltage to the plurality of transmission lines or distributively output the first reference gamma voltage and the second reference gamma voltage as a first combination, and then output the second gamma voltage to the plurality of transmission lines or distributively output the first reference gamma voltage and the second reference gamma voltage as a second combination; and

a buffer coupled to the plurality of transmission lines and configured to output a source voltage by using the first gamma voltage and a third gamma voltage inputted through the second combination,

wherein a second delay time required to output the second gamma voltage from the decoder is shorter than a first delay time required to output the first gamma voltage from the decoder due to a difference in width between the first gamma voltage and the second gamma voltage, an

Wherein a fourth delay time of a fourth gamma voltage input to the buffer through the second combination is shorter than a third delay time of the third gamma voltage input to the buffer through the first combination.

12. The source driver of claim 11, wherein the decoder outputs the second gamma voltages or distributively outputs the first reference gamma voltages and the second reference gamma voltages to the plurality of transmission lines as the first combination through coarse data included in the display data, and outputs the second gamma voltages or distributively outputs the first reference gamma voltages and the second reference gamma voltages to the plurality of transmission lines as the second combination through fine data included in the display data.

13. The source driver of claim 11, wherein the decoder outputs the first and second gamma voltages in a case where a gradation value of the display data corresponds to a first range, and distributively outputs the first and second reference gamma voltages to the plurality of transmission lines as the first and second combinations in a case where a gradation value of the display data corresponds to a second range.