CN106952949B - Graphene field effect transistor and method of forming same - Google Patents

Abstract

A graphene field effect transistor and a method for forming the same, wherein the method for forming the graphene field effect transistor includes: providing a substrate, the substrate including a first region, a second region, and a region between the first region and the second region Form the graphite material layer on the substrate; process the graphite material layer to form a multilayer graphene layer; remove the multilayer graphene layer of the first region and the second region from the thickness direction A part, forming a single-layer graphene layer or a double-layer graphene layer; forming a gate dielectric layer on the surface of the multi-layer graphene layer in the third region; removing the single-layer graphene layer or double-layer graphene layer in the first region and the second region A part of the graphene layer forms a source region and a drain region respectively; electrodes are respectively formed on the source region, the drain region, and the gate dielectric layer. The embodiment of the present invention realizes the in-situ growth of graphene, adopts the top-down graphene preparation method, simplifies the process, and the process is easy to control.

Description

Graphene field effect transistor and method of forming same

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a graphene field effect transistor and a forming method thereof.

Background technique

Graphene is a new type of two-dimensional nanomaterial with a planar benzene ring structure. The thickness of a single layer of graphene is only about one atomic layer thick; due to its zero-gap energy band structure, the electron mobility at room temperature can reach three times the speed of light. One percent, lower resistivity than copper or silver, and thanks to the chemical bonds between carbon atoms, graphene is a hundred times stronger mechanically than steel. It is precisely because of these excellent properties exhibited by the special structure of graphene that graphene has been used in transistors, transparent electrodes, display screens, supercapacitors, solar cells and other fields, and achieved good results.

However, since single-layer graphene or bilayer graphene itself does not have an energy gap, many advantages of graphene cannot be applied to field-effect transistors. Hydrogenated graphene and multilayer (three layers and above) graphene have adjustable energy gaps, so they can be directly applied to the manufacture of field effect transistors at room temperature. For single-layer graphene or double-layer graphene, in the case of quantum confinement, energy gaps can also be generated, such as the formation of single-layer graphene nanoribbons or double-layer graphene nanoribbons, so that it can be applied to graphene field effect transistor.

At present, in the manufacturing process of graphene field effect transistors, the preparation methods of graphene mainly include micromechanical exfoliation method, chemical exfoliation method, silicon carbide epitaxial growth method and chemical vapor deposition method. The chemical vapor deposition method includes: growing graphene on a metal substrate by chemical vapor deposition, and then transferring the graphene from the metal substrate to a non-metal substrate for utilization. The micromechanical exfoliation method includes: using the micromechanical exfoliation method to obtain graphene from highly oriented pyrolytic graphite (HighlyOriented Pyrolytic Graphene, HOPG), and then transferring it to a non-metallic substrate. However, both methods have obvious disadvantages, because some non-ideal factors, such as wrinkles, holes, impurities, etc., will inevitably be introduced during the graphene transfer process, which will affect the electrical properties of the device. In addition, it is often difficult for transferred graphene to form good ohmic contacts with non-metallic substrates.

Contents of the invention

The technical problem solved by the invention is to provide a graphene field effect transistor and its forming method, which simplifies the preparation process of the graphene field effect transistor, and the preparation process is easy to control.

In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a graphene field effect transistor, including: providing a substrate, the substrate includes a first region, a second region, and a region between the first region and the second region The third region; forming a graphite material layer on the substrate; processing the graphite material layer to form a multilayer graphene layer; removing a part of the multilayer graphene layer in the first region and the second region from the thickness direction, Form a single-layer graphene layer or a double-layer graphene layer; form a gate dielectric layer on the surface of the multi-layer graphene layer in the third region; remove the single-layer graphene layer or double-layer graphite in the first region and the second region A part of the alkene layer is used to form a source region and a drain region respectively; electrodes are respectively formed on the source region, the drain region, and the gate dielectric layer.

Optionally, the graphite material layer is highly oriented pyrolytic graphite; the thickness range of the highly oriented pyrolytic graphite is to

Optionally, the method of processing the graphite material layer to form a multilayer graphene layer includes etching by atomic layer etching, and the thickness range of the multilayer graphene layer is to

Optionally, removing a part of the multilayer graphene layer in the first region and the second region from the thickness direction to form a single layer graphene layer or a double layer graphene layer includes: the multilayer graphene layer in the third region A patterned layer is formed on the ene layer, exposing the multilayer graphene layer of the first region and the second region to be etched; using the patterned layer as a mask, the first region and the second region are etched by atomic layer etching. The multi-layer graphene layer in the second region forms a single-layer graphene layer or a double-layer graphene layer; removing the patterned layer.

Optionally, the thickness range of the single-layer graphene layer or double-layer graphene layer formed is to

Optionally, the method of removing a part of the single-layer graphene layer or the double-layer graphene layer in the first region and the second region to form a source region and a drain region respectively includes: along a direction perpendicular to the length of the channel, Respectively remove a part of the single-layer graphene layer or the double-layer graphene layer in the first region, and a part of the single-layer graphene layer or the double-layer graphene layer in the second region to form a graphene layer located in the first region and the second region Single-layer graphene nanoribbons or double-layer graphene nanoribbons are used as source and drain regions, respectively.

Optionally, the dimension range of the single-layer graphene nanoribbon or double-layer graphene nanoribbon formed along the direction perpendicular to the channel length of the transistor is to

Optionally, the method of removing a part of the single-layer graphene layer or the double-layer graphene layer in the first region and the second region includes using an atomic layer etching method.

Optionally, the atomic layer etching method includes dry etching and wet etching steps.

Optionally, the etching gas of the dry etching includes the plasma of an organic compound containing any metal ion in zinc, copper, iron, cadmium and silver, or in nitrogen, fluorine, oxygen and chlorine any gas.

Optionally, the wet etching includes etching with hydrochloric acid, hydrofluoric acid, phosphoric acid, sulfuric acid, or nitric acid.

Optionally, the atomic layer etching method is carried out under the monitoring of Raman spectroscopy.

Correspondingly, an embodiment of the present invention also provides a graphene field effect transistor, including: a substrate, the substrate includes a first region, a second region, and a third region located between the first region and the second region; Single-layer graphene nanobelts or double-layer graphene nanobelts in the first region and the second region, the single-layer graphene nanobelts or double-layer graphene nanobelts in the first region and the second region constitute the field effect The source region and the drain region of the transistor, the multilayer graphene layer in the third region; the gate dielectric layer on the surface of the multilayer graphene layer in the third region; the electrodes on the source region, the drain region, and the gate dielectric layer.

Optionally, the thickness range of the single-layer graphene nanobelt or double-layer graphene nanobelt is to The size range of the single-layer graphene nanobelt or the double-layer graphene nanobelt along the direction perpendicular to the length of the transistor channel is to

Optionally, the thickness range of the multilayer graphene layer is to

Optionally, the base includes a substrate and a lining layer on the substrate, the material of the lining layer is SiO _x , where the value of X is between 0.5 and 3.

Optionally, the SiO _X has a thickness ranging from 200nm to 350nm.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the forming method of the embodiment of the present invention, by forming a graphite material layer on the substrate, the graphite material layer is used to prepare the multi-layer graphene layer and single-layer graphene layer or double-layer graphene layer required for forming a graphene field effect transistor. , realizes the in-situ growth of graphene, overcomes the non-ideal factors introduced in the process of transferring graphene to the substrate, which destroys the performance of graphene field effect transistors; and the embodiment of the present invention uses top-down graphite The preparation method of alkenes simplifies the preparation process, and the preparation process is easy to control.

Optionally, the embodiment of the present invention uses highly oriented pyrolytic graphite as the graphite material layer, and uses the atomic layer etching method to prepare multi-layer graphene layers and single-layer graphene layers or double-layer graphene, with the formed graphene plane Relatively smooth, large single lattice area, easy separation between graphene layers and other advantages; overcome the micromechanical exfoliation method to prepare multi-layer graphene layers and single-layer graphene layers or double-layer graphene layers from highly oriented pyrolytic graphite The area and quality of the graphene layer are uncontrollable, and the graphene is easily damaged during the transfer process.

In the graphene field effect transistor of the embodiment of the present invention, a single-layer graphene nanoribbon or a double-layer graphene nanoribbon with an energy gap is used as the source-drain region, and the multi-layer graphene layer is located between the source-drain region, so that the source-drain region The single-layer graphene layer or the double-layer graphene layer in the multilayer graphene layer located between the regions and in the same layer as the single-layer graphene nanoribbon or the double-layer graphene nanoribbon is used as the channel region. Since the single-layer graphene layer or double-layer graphene has carrier ballistic transport capability and high carrier mobility, the formed graphene field effect transistor has high carrier mobility.

Description of drawings

1 to 9 are schematic cross-sectional views of intermediate structures of a method for forming a graphene field effect transistor according to an embodiment of the present invention.

Detailed ways

The present invention provides a graphene field effect transistor and its forming method, which will be described in detail below in conjunction with the accompanying drawings.

1 to 9 are schematic cross-sectional views of intermediate structures of a method for forming a graphene field effect transistor according to an embodiment of the present invention.

Referring to FIG. 1 , a base 100 is provided, the base 100 includes a first region 100a, a second region 100b, and a third region 100c between the first region 100a and the second region 100b; the base 100 includes a substrate 101 and A lining layer 102 , the lining layer 102 is formed on the substrate 101 ; a graphite material layer 110 is formed on the substrate 100 .

In the embodiment of the present invention, the substrate 101 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate or a III-V compound substrate, such as nitrogen Gallium nitride substrate or gallium arsenide substrate, etc.; the substrate 101 can also be a substrate formed of other semiconductor materials; the substrate 101 can also be selected from a structure having an epitaxial layer or a silicon-on-epitaxial layer. In this embodiment, the substrate 101 is a single crystal silicon substrate.

The lining layer 102 may be SiO _x , where the value of X is between 0.5 and 3. The formed SiO _x liner layer has a thickness ranging from 200 nm to 350 nm. It should be noted that the lining layer 102 is used to distinguish the structure of graphene when the number of layers of graphene made from highly oriented pyrolytic graphite is subsequently determined by Raman spectroscopy. In this embodiment, the material of the lining layer 102 is SiO ₂ , and the thickness of the SiO ₂ is 300 nm.

The material of the graphite material layer 110 is highly oriented pyrolytic graphite (HOPG). The thickness range of the highly oriented pyrolytic graphite is to Specifically, the thickness of the highly oriented pyrolytic graphite described in this embodiment is

Referring to FIG. 2 , the highly oriented pyrolytic graphite is processed by atomic layer etching (Atomic Layer Etch, ALE), and the monoatomic layer is peeled off to obtain a multilayer graphene layer 120 .

The atomic layer etching method includes dry etching and wet etching steps: that is, first sputtering the surface of the highly oriented pyrolytic graphite with dry etching gas; The surface of the final highly oriented pyrolytic graphite is treated, and the above steps are repeated until a multi-layer graphene layer 120 with better layer uniformity and fewer defects is obtained. It should be noted that the multi-layer graphene layer 120 is composed of n single-layer graphene layers 121 , where n is greater than or equal to three.

The dry etching gas includes the plasma of an organic compound containing any metal ion in zinc, copper, iron, cadmium and silver, or any gas in nitrogen, fluorine, oxygen and chlorine, The flow rate of etching gas is 1sccm to 5000sccm, the power is 100W to 1000W, the bias voltage is 0V to 500V, the frequency is 2MHz to 4GHz, the etching temperature is -140°C to 200°C, the pressure is 1mTorr to 1000Torr, and the sputtering time is 1s to 100s. The wet etching reagent includes one of hydrochloric acid, hydrofluoric acid, phosphoric acid, sulfuric acid or nitric acid or any combination thereof, and the volume ratio of the wet etching reagent to _H2O is 1:1 to 1: 1000, the processing time is from 1s to 500s. The thickness range of the described multilayer graphene layer 120 that forms is to

In this embodiment, the dry etching gas is oxygen, the flow rate of the gas is 20 sccm, the power is 500W, the bias voltage is 200V, the frequency is 5MHz, the etching temperature is 50°C, the pressure is 20Torr, and the sputtering time for 50s. The wet etching uses hydrochloric acid as an etchant, the volume ratio of H ₂ O to HCl in the hydrochloric acid solution is 200:1, and the processing time is 100s. The thickness of the described multilayer graphene layer 120 that forms is

While using the atomic layer etching method to process the highly oriented pyrolytic graphite, it also includes using Raman spectroscopy to identify the structure of the highly oriented pyrolytic graphite being processed, so as to determine the multilayer graphene layer 120 obtained by etching The number of layers, while controlling the number of cycles of the atomic layer etching method.

Referring to FIG. 3 , a mask layer 130 is formed on the surface of the multilayer graphene layer 120 in the third region 100 c of the substrate 100 , and the mask layer 130 is a photoresist layer. The multilayer graphene layers 120 in the first region 100a and the second region 100b are used to form a source region and a drain region respectively, and the multilayer graphene layers 120 in the third region 100c are used to form a channel region. The mask layer 130 is used to protect the multi-layer graphene layer 120 in the third region 100c during subsequent etching.

Referring to Fig. 4, using the mask layer 130 as a mask, the multi-layer graphene layer 120 of the first region 100a and the second region 100b is etched by an atomic layer etching method to obtain a single-layer graphene layer or a double-layer graphite vinyl layer 121.

The atomic layer etching method includes dry etching and wet etching steps. The gas for the dry etching includes plasma of an organic compound containing any metal ion in zinc, copper, iron, cadmium and silver, or any gas in nitrogen, fluorine, oxygen and chlorine, The flow rate of etching gas is 1sccm to 5000sccm, the power is 100W to 1000W, the bias voltage is 0V to 500V, the frequency is 2MHz to 4GHz, the etching temperature is -140°C to 200°C, the pressure is 1mTorr to 1000Torr, and the sputtering time is 1s to 100s. The wet etching reagent includes one of hydrochloric acid, hydrofluoric acid, phosphoric acid, sulfuric acid or nitric acid or any combination thereof, and the volume ratio of the wet etching reagent to _H2O is 1:1 to 1: 1000, the processing time is from 1s to 500s. The thickness of the described single-layer graphene layer or double-layer graphene layer 121 that forms is to

In this embodiment, the dry etching gas is oxygen, the flow rate of the gas is 20 sccm, the power is 500W, the bias voltage is 200V, the frequency is 5MHz, the etching temperature is 50°C, the pressure is 200Torr, and the sputtering time for 50s. The wet etching uses hydrochloric acid as an etchant, the volume ratio of H ₂ O to HCl in the hydrochloric acid solution is 200:1, and the processing time is 100s. The thickness of the described monolayer graphene layer 121 that forms is

While adopting the atomic layer etching method to process the multilayer graphene layer 120, the number of layers of the multilayer graphene layer 120 in processing is also identified by Raman spectroscopy, so as to determine the obtained single layer graphene layer Or the number of layers of the bilayer graphene layer 121, and the number of cycles of the atomic layer etching method.

Fig. 5 and Fig. 6 are the schematic cross-sectional structural diagrams of Fig. 4 along AA' (or BB') direction.

5, it can be seen that the single-layer graphene layer or double-layer graphene layer 121 located in the first region 100a (or second region 100b) after the above-mentioned process is perpendicular to the channel length direction, that is, perpendicular to the The relative size in the direction of electron transport in the channel region is large. It should be noted that since the single-layer graphene layer or the double-layer graphene layer 121 itself does not have an energy gap, it cannot be directly applied to the manufacture of field effect transistors. Research results in recent years have shown that single-layer graphene or double-layer graphene can realize the opening of the energy gap under the conditions of quantum confinement effects and exhibit semiconductor properties. Therefore, in this embodiment, it is necessary to perform quantum confinement on the obtained single-layer graphene layer or double-layer graphene layer 121 to realize its semiconducting properties. For the multi-layer graphene layer 120 located in the third region 100c, since it has an energy gap, it can be directly used as a channel region material and applied in the manufacture of a graphene field effect transistor.

With reference to Fig. 6, Fig. 6 is to remove a part of the single-layer graphene layer or double-layer graphene layer 121 (as shown in Fig. 5) of the first region 100a and the second region 100b, the structural representation after it has been carried out quantum confinement .

For the single-layer graphene layer or double-layer graphene layer 121 (as shown in FIG. 5 ) located in the first region 100a and the second region 100b, electron transport along the direction perpendicular to the length of the channel, that is, perpendicular to the channel region direction to form single-layer graphene nanoribbon or double-layer graphene nanoribbon (Graphene Nanoribbon) 121a and 121b respectively located in the first region 100a and the second region 100b, serving as source region and drain region respectively.

Specifically, in this embodiment, photolithography and atomic layer etching are used to remove part of the single-layer graphene layer or double-layer graphene layer 121 located in the first region 100a and the second region 100b, including: forming a single-layer The regions of graphene nanoribbons or double-layer graphene nanoribbons 121a and 121b form a patterned photoresist layer, which exposes the single-layer graphene layer or double-layer graphene layer that needs to be removed In area 121, using the patterned photoresist layer as a mask, the single-layer graphene layer or the double-layer graphene layer 121 is etched by an atomic layer etching method to form a single-layer graphene nanoribbon or a double-layer Graphene nanoribbons 121a and 121b. The size range of the single-layer graphene nanoribbon or double-layer graphene nanoribbon 121a and 121b along the direction perpendicular to the length of the transistor channel is to

The atomic layer etching method includes dry etching and wet etching steps. In this embodiment, the dry etching gas is oxygen, the flow rate of the gas is 20 sccm, the power is 500W, the bias voltage is 200V, the frequency is 5MHz, the etching temperature is 50°C, the pressure is 200Torr, and the sputtering time for 50s. The wet etching uses hydrochloric acid as an etchant, the volume ratio of H ₂ O to HCl in the hydrochloric acid solution is 200:1, and the processing time is 100s. The dimensions of the formed single-layer graphene nanobelts 121a and 121b along the direction perpendicular to the channel length of the transistor are

Referring to Fig. 7, after forming the single-layer graphene nanoribbon or the double-layer graphene nanoribbon 121a and 121b of the source region and the drain region respectively, it is located between the source and drain regions, and is connected with the single-layer graphene nanoribbon or the double-layer graphene The single-layer graphene layer or the double-layer graphene layer 121c in the multi-layer graphene layer 120 where the nanobelts 121a and 121b are located in the same layer serves as a channel region. Due to the ballistic transport capability of single-layer graphene or double-layer graphene, the formed graphene field-effect transistor has high carrier mobility.

Referring to FIG. 8 , an electrode 161 of a source and an electrode 162 of a drain are formed.

In this embodiment, the material of the source electrode 161 and the drain electrode 162 is gold. The process steps for forming the electrodes 161 and 162 include chemical vapor deposition, electron beam lithography and deep ultraviolet lithography. First, a chemical vapor deposition method is used to deposit an electrode material layer on the source region and the drain region, and then the electrode material layer is etched to form the electrodes 161 and 162 . Specifically, when the surface of the single-layer graphene nanoribbon or double-layer graphene nanoribbon 121a and 121b away from the source region and the drain region, the electrode material layer is etched by using deep ultraviolet lithography; At the surface of single-layer graphene nanoribbons or double-layer graphene nanoribbons 121a and 121b of the drain region, electron beam lithography is used to etch the remaining electrode material layer to avoid damage to the source region and the drain region during the etching process. Damage caused by single-layer graphene nanoribbons or double-layer graphene nanoribbons 121a and 121b in the drain region.

Then, the mask layer 130 is removed.

Referring to FIG. 9 , a gate dielectric layer 150 is formed on the surface of the multi-layer graphene layer 120 ; and a gate electrode 163 is formed on the surface of the gate dielectric layer 150 .

The material of the gate dielectric layer 150 includes silicon oxide and high dielectric constant material, and the thickness range of the formed gate dielectric layer 150 is to The high dielectric constant material described in this embodiment is hafnium oxide; the process for forming the silicon oxide is chemical vapor deposition, and the thickness of the silicon oxide formed is The process of forming the hafnium oxide is atomic layer deposition, and the thickness of the hafnium oxide is

The material forming the electrode 163 of the gate is copper or gold. In this embodiment, the material for forming the electrode 163 of the gate is gold, and the process steps of forming the electrode 163 of the gate include chemical vapor deposition, electron beam lithography, and deep ultraviolet lithography. The specific formation method is the same as the aforementioned formation source. The methods for the pole electrode 161 and the drain electrode 162 are similar, and will not be repeated here.

Correspondingly, this embodiment also provides a structure of a graphene field effect transistor.

Continuing to refer to FIG. 9, the graphene field effect transistor includes: a substrate 100, the substrate 100 includes a first region 100a, a second region 100b, and a third region 100c between the first region 100a and the second region 100b; Single-layer graphene nanobelts or double-layer graphene nanobelts, including single-layer graphene nanobelts or double-layer graphene nanobelts 121a and 121b respectively located in the first region 100a and second region 100b, as source regions respectively and the drain region; the multilayer graphene layer 120 located in the third region 100c, as a channel region; the gate dielectric layer 150, located on the surface of the multilayer graphene layer 120 in the third region 100c; and the electrode 161 of the source, The drain electrode 162 and the gate electrode 163 are respectively located on the surface of the source region, the drain region, and the gate dielectric layer 150 .

The base 100 includes a substrate 101 and a liner 102 on the substrate 101 . The material of the lining layer 102 is SiO _X , wherein the value of X is between 0.5 and 3; the thickness of the SiO _X is in the range of 200 nm to 350 nm. In this embodiment, the material of the lining layer 102 is SiO ₂ , and the thickness of the SiO ₂ is 300 nm.

It should be noted that the single-layer graphene nanobelts or double-layer graphene nanobelts 121a and 121b used as the source region and the drain region are single-layer graphite particles that have undergone quantum confinement along the direction perpendicular to the channel length of the transistor. Graphene nanoribbons or double-layer graphene nanoribbons have energy gaps, so as to meet the requirements of semiconducting materials for the preparation of field effect transistors. The thickness range of the single-layer graphene nanobelt or double-layer graphene nanobelt 121a and 121b is to The size range of the single-layer graphene nanobelt or double-layer graphene nanobelt 121a and 121b along the direction perpendicular to the length of the transistor channel is to The thickness range of the multilayer graphene layer 120 is to

In one embodiment, the single-layer graphene nanobelts or double-layer graphene nanobelts 121a and 121b are single-layer graphene nanobelts with a thickness of The dimensions of the single-layer graphene nanobelts 121a and 121b along the direction perpendicular to the length of the transistor channel are The thickness of the multilayer graphene layer 120 is

The material of the gate dielectric layer 150 includes silicon oxide and high dielectric constant material, and the thickness range of the gate dielectric layer 150 is to In one embodiment, the material of the gate dielectric layer 150 is silicon oxide and hafnium oxide, and the thickness of the silicon oxide is The thickness of the hafnium oxide is

The material of the source electrode 161 and the drain electrode 162 is gold, and the material of the gate electrode 163 is copper or gold. In this embodiment, the materials of the source electrode 161 , the drain electrode 162 , and the gate electrode 163 are all gold.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (17)

1. a kind of forming method of graphene field effect transistor characterized by comprising

Substrate is provided, the substrate include first area, second area and between first area and second area the Three regions；

Graphite material is formed on the substrate；

The graphite material is handled, multiple graphene layers are formed；

A part of the multiple graphene layers of the first area and second area is removed from thickness direction, forms single-layer graphene Layer or bilayer graphene layer；

Gate dielectric layer is formed in the multi-layer graphene layer surface in third region；

The single-layer graphene layer of the first area and second area or a part of bilayer graphene layer are removed, source is respectively formed Area and drain region；

Electrode is respectively formed on source region, drain region and gate dielectric layer.

2. forming method as described in claim 1, which is characterized in that the graphite material is highly oriented pyrolytic graphite；Institute The thickness range for stating highly oriented pyrolytic graphite isExtremely

3. forming method as described in claim 1, which is characterized in that the processing graphite material forms multilayer stone The method of black alkene layer includes being performed etching using atomic layer lithographic method, and the thickness range for forming the multiple graphene layers isExtremely

4. forming method as described in claim 1, which is characterized in that remove the first area and the secondth area from thickness direction A part of the multiple graphene layers in domain, forms single-layer graphene layer or bilayer graphene layer includes:

Patterned layer is formed on the multiple graphene layers in third region, exposes first area and the secondth area to be etched The multiple graphene layers in domain；

Using the patterned layer as mask, using the multi-layer graphene of atomic layer lithographic method etching first area and second area Layer forms single-layer graphene layer or bilayer graphene layer；

Remove the patterned layer.

5. forming method as claimed in claim 4, which is characterized in that the single-layer graphene layer or bilayer graphene of the formation Layer thickness range beExtremely

6. forming method as described in claim 1, which is characterized in that the list of the removal first area and second area A part of layer graphene layer or bilayer graphene layer, the method for being respectively formed source region and drain region includes: along perpendicular to ditch road length Degree direction removes the single-layer graphene layer of the first area or a part and second area of bilayer graphene layer respectively Single-layer graphene layer or bilayer graphene layer a part, formed and be located at the single-layer graphene of first area and second area and receive Rice band or bilayer graphene nanobelt, respectively as source region and drain region.

7. forming method as claimed in claim 6, which is characterized in that the single-layer graphene nanobelt of formation or the double-deck stone Black alkene nanobelt edge is perpendicular to the size range in transistor channel length directionExtremely

8. forming method as claimed in claim 6, which is characterized in that remove the single layer stone of the first area and second area The method of a part of black alkene layer or bilayer graphene layer includes using atomic layer lithographic method.

9. the forming method as described in claim 3,4 or 8, which is characterized in that the atomic layer lithographic method includes using dry Method etching and wet etching step.

10. forming method as claimed in claim 9, which is characterized in that the etching gas of the dry etching includes using to contain Have the organic compound of any one metal ion in zinc, copper, iron, cadmium and silver plasma or nitrogen, fluorine gas, Any one gas in oxygen and chlorine.

11. forming method as claimed in claim 9, which is characterized in that the wet etching include using hydrochloric acid, hydrofluoric acid, Phosphoric acid, sulfuric acid or nitric acid perform etching.

12. the forming method as described in claim 3,4 or 8, which is characterized in that the atomic layer lithographic method is in Raman light Spectrum monitoring is lower to be carried out.

13. a kind of graphene field effect transistor characterized by comprising

Substrate, the substrate include first area, second area and the third area between first area and second area Domain；

Single-layer graphene nanobelt or bilayer graphene nanobelt positioned at first area and second area, it is described to be located at the firstth area The single-layer graphene nanobelt or bilayer graphene nanobelt of domain and second area constitute the field effect transistor source region and Drain region, the multiple graphene layers positioned at third region；

Positioned at the gate dielectric layer of the multi-layer graphene layer surface in third region；

Electrode on source region, drain region and gate dielectric layer.

14. graphene field effect transistor as claimed in claim 13, which is characterized in that the single-layer graphene nanobelt or The thickness range of bilayer graphene nanobelt isExtremelyThe single-layer graphene nanobelt or bilayer graphene are received Rice band edge is perpendicular to the size range in transistor channel length directionExtremely

15. graphene field effect transistor as claimed in claim 13, which is characterized in that the thickness of the multiple graphene layers Range isExtremely

16. graphene field effect transistor as claimed in claim 13, which is characterized in that the substrate includes substrate and position In the lining of substrate, the material of the lining is SiO_X, wherein the value of X is between 0.5 to 3.

17. graphene field effect transistor as claimed in claim 16, which is characterized in that the SiO_XThickness range be 200nm to 350nm.