CN106952915A - A kind of SOI eight-transistor static random access memory unit and its manufacturing method - Google Patents

Abstract

The present invention provides a kind of SOI eight-transistor static random access memory units and preparation method thereof, and the unit includes：First phase inverter, is made up of the first PMOS transistor and the first nmos pass transistor；Second phase inverter, is made up of the second PMOS transistor and the second nmos pass transistor；Pipe is obtained, is made up of the three, the four, the 5th and the 6th nmos pass transistor.In the present invention, the source electrode of four transistors of the first phase inverter and the second phase inverter is constituted using reinforcing source region, this reinforcing source region Box electric leakages, up and down corner electric leakage and sidewall leakage caused by it can effectively suppress the total dose effect of SOI device in the case of not increasing the area of device.And the present invention can also suppress the floater effect of transistor while total dose effect is effectively suppressed.This invention removes the shortcoming that traditional resistant to total dose ruggedized construction increase chip area and can not suppressing comprehensively leaks electricity caused by total dose effect.And the method for the present invention has the advantages that manufacturing process is simple, mutually compatible with stand CMOS.

Description

A kind of SOI eight-transistor static random access memory unit and its manufacturing method

technical field

The invention belongs to the field of memory design and manufacture, and relates to an SOI eight-transistor static random access memory unit and a manufacturing method thereof.

Background technique

In aerospace electronic systems, Static Random Access Memory (SRAM) is often widely used because of its fast working speed and compatibility with traditional CMOS technology; due to the harsh working environment of aerospace electronic systems, SRAM is often damaged by particle radiation. As a result, the performance of its cells is affected and the performance of the entire memory is degraded. Currently commonly used SRAM cells include eight-transistor types, consisting of two pull-up P-type transistors, two pull-down N-type transistors, and four transfer-gate N-type transistors. The word line controls the switches of the four transfer-gate N-type transistors. The stored data is written or read through the bit line, wherein, the eight transistors are all ordinary MOS transistors.

The most common radiation effects are total dose effects and single event effects. Compared with the bulk silicon process, SOI devices add a layer of BOX insulating layer between the top silicon and the substrate, thereby completely suppressing the single event latch-up phenomenon that is prone to occur in bulk silicon; in addition, this BOX insulating layer makes The number of charges generated by the single event effect is small, which makes the situation of SOI devices eased under the single event effect. Therefore, the total dose effect of SOI devices has received more attention than the single event effect, and it is also an urgent problem to be solved. On the other hand, the floating body effect of SOI devices is also a negative impact due to the BOX insulating layer. When the total dose effect occurs, the particles provide additional energy, which causes some electrons in the insulator material to be ionized to form electron-hole pairs. After some electrons and holes recombine, some electron-hole pairs move freely. Under the action of an electric field, due to the high electron mobility, it is not easy to be trapped by it, and it is easy to release from the insulating material, but the holes are easier to be trapped, and finally form an interface state and fix positive charges; these charges make the device (in NMOS transistors) It is more obvious) the threshold voltage and leakage of itself change, so that the performance of the unit changes.

With the development of process nodes, it is generally believed that when the thickness of the gate oxide is less than 3nm, the accumulated charge in the gate oxide caused by the total dose is not enough to cause threshold voltage and leakage changes, so it can be ignored. There are only gate oxide and field oxygen in insulating materials in SOI devices. Therefore, the impact of the total dose effect on SOI MOS devices is mainly manifested through field oxygen.

The leakage caused by the general SOI MOS device due to the total dose effect can be illustrated by Fig. 1, which shows the gate region 101, the source region 102 and the drain region 103 of the SOI MOS device, wherein the charge generated at the interface between field oxygen and Si Causes sidewall leakage and Box leakage. FIG. 1 also shows part of the leakage currents I _a and I _a ′. In order to better illustrate its leakage situation, please refer to FIG. 2, which is shown as a part of the AA' cross-sectional view of the structure shown in FIG. 1, including source region 102, gate oxide 104, shallow trench isolation structure 105 Insulation, referred to as STI) and buried oxide layer 106 (BuriedOxide, referred to as BOX); as shown in Figure 2, sidewall leakage can be roughly divided into gate oxide and shallow trench isolation structure contact part, shallow trench isolation The part where the isolation structure is in contact with the buried oxide layer and the part where the buried oxide layer is in contact with leakage is referred to as upper corner, side wall, lower corner and Box leakage for short.

In order to solve the performance degradation of memory cells caused by the total dose effect, an H-type gate structure is usually used for reinforcement. As shown in Figure 3, the heavily doped P-type regions formed at both ends of the H gate are connected to the P-type body region under the gate oxide. Because the part of the body contact region 107 at both ends of the H gate is changed to a heavily doped P-type region instead of an insulator material, the charge accumulation caused by the total dose effect is suppressed, and the leakage is reduced. Please refer to Figure 4, which is a part of the B-B' sectional view of the structure shown in Figure 3, in which the leakage corresponding to the H gate is mainly Box leakage and a small amount of bottom corner leakage. Although the H gate can solve the problem of upper corner and sidewall leakage and most of the lower corner leakage, its Box leakage and a small amount of lower corner leakage still exist; and its device area is greatly increased.

Therefore, how to provide an SOI eight-transistor SRAM unit and its manufacturing method, and effectively suppress the total dose effect of the SOI SRAM unit without increasing the chip area, has become an important technology to be solved urgently by those skilled in the art. question.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an SOI eight-transistor SRAM unit and a manufacturing method thereof, which are used to solve the leakage caused by the total dose effect of the SOI eight-transistor SRAM unit in the prior art Added questions.

To achieve the above object and other related objects, the present invention provides an SOI eight-transistor SRAM unit, the SOI eight-transistor SRAM unit comprising:

The first inverter is composed of a first PMOS transistor and a first NMOS transistor;

The second inverter is composed of a second PMOS transistor and a second NMOS transistor;

An acquisition transistor, composed of a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the source of the third NMOS transistor is connected to the output end of the first inverter and the first inverter The input end of the two inverters, the gate is connected to the write word line of the memory, and the drain is connected to the write bit line of the memory; the source of the fourth NMOS transistor is connected to the output end of the second inverter and the The input terminal of the first inverter, the gate is connected to the write word line of the memory, and the drain is connected to the write inversion bit line of the memory; the source of the fifth NMOS transistor is connected to the output of the first inverter terminal and the input terminal of the second inverter, the gate is connected to the read word line of the memory, and the drain is connected to the read bit line of the memory; the source of the sixth NMOS transistor is connected to the second inverting The output end of the device and the input end of the first inverter, the gate is connected to the read word line of the memory, and the drain is connected to the read inversion bit line of the memory;

Wherein, the sources of the first and second PMOS transistors and the first and second NMOS transistors use reinforced source regions; for NMOS transistors, the reinforced source regions include the first heavily doped N-type region, the first heavily doped Doping a P-type region and a shallow N-type region, and the first heavily doped P-type region surrounds the vertical ends and the bottom of the first heavily doped N-type region; for a PMOS transistor, the reinforced source region includes A second heavily doped P-type region, a second heavily doped N-type region, and a shallow P-type region, and the second heavily doped N-type region surrounds both longitudinal ends of the second heavily doped P-type region and bottom.

Optionally, a metal silicide is formed on the reinforced source region; for an NMOS transistor, both the first heavily doped N-type region and the first heavily doped P-type region are in contact with the metal silicide, and The lateral ends of the shallow N-type region are respectively in contact with the metal silicide and the body region of the NMOS transistor; for the PMOS transistor, the second heavily doped P-type region and the second heavily doped N-type region The regions are all in contact with the metal silicide, and the lateral ends of the shallow P-type region are respectively in contact with the metal silicide and the body region of the PMOS transistor.

Optionally, the metal silicide is selected from any one of cobalt silicide and titanium silicide.

Optionally, a metal silicide is formed on top of the drains of the first and second PMOS transistors and the first and second NMOS transistors.

Optionally, the SOI eight-transistor SRAM unit adopts an SOI substrate including a back substrate, an insulating buried layer, and a top-layer silicon from bottom to top, and the active regions where each transistor is located pass through the top-layer silicon shallow trench isolation structure.

Optionally, at least one of the sources of the third, fourth, fifth, and sixth NMOS transistors uses the reinforced source region.

Optionally, at least one of the third, fourth, fifth and sixth NMOS transistors is a common gate NMOS transistor, a T-type gate NMOS transistor or an H-type gate NMOS transistor.

The present invention also provides a method for fabricating an SOI eight-transistor SRAM unit, comprising the following steps:

S1: Provide an SOI substrate including a back substrate, an insulating buried layer, and a top layer of silicon in sequence from bottom to top, fabricate a shallow trench isolation structure in the top layer of silicon, and define an active region;

S2: Fabricate an N well, a first P well, and a second P well in the top silicon according to the position of the active region, wherein the N well is located between the first P well and the second P well ;

S3: Fabricate a first PMOS transistor and a second PMOS transistor in the N well; fabricate a first NMOS transistor, a third NMOS transistor, and a fifth NMOS transistor in the first P well; Manufacturing the second NMOS transistor, the fourth NMOS transistor and the sixth NMOS transistor; wherein, the source electrodes of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor all adopt a reinforced source region; for NMOS transistor, the reinforced source region includes a first heavily doped N-type region, a first heavily doped P-type region, and a shallow N-type region, and the first heavily doped P-type region surrounds the first heavily doped The vertical ends and the bottom of the heterogeneous N-type region; for PMOS transistors, the reinforced source region includes a second heavily doped P-type region, a second heavily doped N-type region, and a shallow P-type region, and the second heavily doped The doped N-type region surrounds the vertical ends and the bottom of the second heavily doped P-type region;

S4: Fabricate metal vias and corresponding metal connections to complete fabrication of the memory unit.

Optionally, the step S3 includes the steps of:

S3-1: forming a first gate spanning the first P well and the N well and a second gate spanning the N well and the second P well, and forming a preset position in the first P well forming a third gate, and forming a fourth gate at a preset position of the second P well; the first gate is shared by the first NMOS transistor and the first PMOS transistor; the second gate is shared by the second NMOS transistor and the second PMOS transistor;

S3-2: Perform N-type light doping at preset positions of the first and second P wells to form shallow N-type of the first, second, third, fourth, fifth and sixth NMOS transistors region; perform P-type light doping at the preset position of the N well to form shallow P-type regions of the first and second PMOS transistors;

S3-3: Form a spacer isolation structure around the first, second, third, and fourth gates, and perform P-type heavy doping at preset positions of the first and second P wells to form the The middle part of the first heavily doped P-type region in the reinforced source region of the first and second NMOS transistors; N-type heavy doping is performed at the preset position of the N well to form the first and second NMOS transistors. the middle part of said second heavily doped N-type region in the reinforced source region of two PMOS transistors;

S3-4: Perform N-type heavy doping in the first and second P wells above the first heavily doped P-type region to form reinforced source regions of the first and second NMOS transistors The first heavily doped N-type region in the N well; the region above the second heavily doped N-type region in the N well is heavily doped with P-type to form the first and second PMOS transistors The second heavily doped P-type region in the reinforced source region;

S3-5: Perform P-type heavy doping at preset positions of the first and second P wells to form the first heavily doped P-type regions in the reinforced source regions of the first and second NMOS transistors N-type heavy doping is carried out at the preset position of the N well to form the two ends of the second heavily doped N-type region in the reinforced source regions of the first and second PMOS transistors .

Optionally, in the step S3-3, a mask with an opening in the longitudinal middle section of the reinforced source region is used, and ion implantation is performed vertically through the mask to complete the P-type redoping hetero or the N-type heavily doped.

Optionally, the ion implantation concentration range is 1E15-9E15/cm ² .

Optionally, in the step S3-4, it also includes performing N-type heavy doping at preset positions of the first and second P wells to form the first, second, third, fourth, The drains of the fifth and sixth NMOS transistors and the sources of the third, fourth, fifth and sixth NMOS transistors are heavily doped with P type at the preset positions of the N wells to form the first and sixth NMOS transistors. Two PMOS transistor drain steps.

Optionally, the drain of the first NMOS transistor is shared with the source of the third NMOS transistor; the drain of the second NMOS transistor is shared with the source of the fourth NMOS transistor.

Optionally, in the step S3, a step of forming a metal silicide on the upper part of the reinforced source region is also included; for an NMOS transistor, the metal silicide and the first heavily doped N-type region, the first heavily doped P-type region, and the shallow N-type region are all in contact with each other; for a PMOS transistor, the metal silicide is connected to the second heavily doped P-type region of the reinforced source region, the second heavily doped N Both the P-type region and the shallow P-type region are in contact with each other.

Optionally, the metal silicide is formed by forming a metal layer on the reinforced source region and heat-treating the metal layer to react with the underlying Si material.

Optionally, the temperature range of the heat treatment is 700-900° C., and the time is 50-70 seconds.

Optionally, in the step S3, a step of forming a metal silicide on the drains and gates of the first and second PMOS transistors and the first and second NMOS transistors, and 3. A step of forming a metal silicide on the source, drain and upper part of the gate of the fourth, fifth and sixth NMOS transistors.

Optionally, the first NMOS transistor is interconnected with the first PMOS transistor to form a first inverter; the second NMOS transistor is interconnected with the second PMOS transistor to form a second inverter; the The source of the third NMOS transistor is connected to the output terminal of the first inverter and the input terminal of the second inverter, the gate is connected to the write word line of the memory, and the drain is connected to the write bit line of the memory; The source of the fourth NMOS transistor is connected to the output terminal of the second inverter and the input terminal of the first inverter, the gate is connected to the write word line of the memory, and the drain is connected to the write inverter of the memory. bit line; the source of the fifth NMOS transistor is connected to the output terminal of the first inverter and the input terminal of the second inverter, the gate is connected to the read word line of the memory, and the drain is connected to the The read bit line of the memory; the source of the sixth NMOS transistor is connected to the output end of the second inverter and the input end of the first inverter, the gate is connected to the read word line of the memory, and the drain The pole is connected to the read inversion bit line of the memory.

Optionally, the first, second, third and fourth gates all include a gate dielectric layer and a polysilicon layer on the gate dielectric layer.

As mentioned above, the SOI eight-transistor SRAM unit and its manufacturing method of the present invention have the following beneficial effects: in the SOI eight-transistor SRAM unit, the four The sources of the transistors all use reinforced source regions. For NMOS transistors, the reinforced source regions include a first heavily doped N-type region, a first heavily doped P-type region, and a shallow N-type region, and the first heavily doped The heterogeneous P-type region surrounds the longitudinal ends and the bottom of the first heavily doped N-type region; for a PMOS transistor, the reinforced source region includes a second heavily doped P-type region, a second heavily doped N-type region and A shallow P-type region, and the second heavily doped N-type region surrounds both vertical ends and the bottom of the second heavily doped P-type region. The reinforced source region can effectively suppress Box leakage, upper and lower corner leakage, and sidewall leakage caused by the total dose effect of the SOI device without increasing the area of the device. And the present invention can also suppress the floating body effect of the transistor while effectively suppressing the total dose effect. The invention eliminates the disadvantages of increasing the chip area of the traditional anti-total dose reinforcement structure and being unable to fully suppress the leakage caused by the total dose effect, and the invention also has the advantages of simple manufacturing process and compatibility with conventional CMOS processes.

Description of drawings

FIG. 1 shows a top view structure diagram of a common SOI MOS device in the prior art.

Fig. 2 shows the A-A' cross-sectional view of the structure shown in Fig. 1.

FIG. 3 is a top view structure diagram of an H-gate SOI MOS device in the prior art.

Fig. 4 shows a B-B' cross-sectional view of the structure shown in Fig. 3 .

FIG. 5 is a schematic diagram of the circuit principle of the SOI eight-transistor SRAM unit of the present invention.

FIG. 6 is a schematic top view of an NMOS transistor with a reinforced source region in an SOI eight-transistor SRAM cell of the present invention.

Fig. 7-Fig. 9 respectively show the C-C' direction, D-D' direction and E-E' direction sectional view of the structure shown in Fig. 6 .

10 to 12 are schematic diagrams showing the structures of NMOS transistors using ordinary gates, T-shaped gates and H-shaped gates, respectively.

13-20 are schematic top view structural diagrams of each step in the manufacturing method of the SOI eight-transistor SRAM unit of the present invention.

Component designation description

101 gate area

102 source area

103 drain area

104 gate oxide

105 shallow trench isolation structure

106 buried oxide layer

107 body contact area

201 First Inverter

2011 First PMOS transistor

2012 First NMOS transistor

202 Second Inverter

2021 Second PMOS transistor

2022 Second NMOS transistor

203 Get Tube

2031 Third NMOS transistor

2032 fourth NMOS transistor

2033 fifth NMOS transistor

2034 Sixth NMOS transistor

204 Reinforced source area

2041 The first heavily doped N-type region

2042 The first heavily doped P-type region

2043 Shallow N-type region

205 drain

206 grid

2061 gate dielectric layer

2062 polysilicon layer

207 body area

208 backing substrate

209 insulating buried layer

210 shallow trench isolation structure

211 Side wall isolation structure

212 metal silicide

213 Ordinary grid

214 T-type grid

215 H-type grid

216 source area

217 drain area

218 body contact area

20a, 20b, 20c, 20d, 20e, 20f active regions

30 Nwell

40a The first P well

40b Second P well

50a First Grid

50b Second Grid

50c third grid

50d fourth gate

60a, 60b shallow N-type region

70a, 70b shallow P-type region

80a, 80b middle part of the first heavily doped P-type region

80a', 80b' are the two ends of the first heavily doped P-type region

90a, 90b middle part of the second heavily doped N-type region

90a', 90b' are the two ends of the second heavily doped N-type region

91a, 91b the first heavily doped N-type region

92a, 92b second heavily doped P-type region

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 5 through 20. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Embodiment one

The present invention provides an SOI eight-transistor SRAM unit, please refer to FIG. 5 , which is a schematic diagram of the circuit principle of the SOI eight-transistor SRAM unit, including:

The first inverter 201 is composed of a first PMOS transistor 2011 and a first NMOS transistor 2012;

The second inverter 202 is composed of a second PMOS transistor 2021 and a second NMOS transistor 2022;

The acquisition transistor 203 is composed of a third NMOS transistor 2031, a fourth NMOS transistor 2032, a fifth NMOS transistor 2033 and a sixth NMOS transistor 2034; the source of the third NMOS transistor 2031 is connected to the first inverter The output end and the input end of the second inverter, the gate is connected to the write word line WL1 of the memory, and the drain is connected to the write bit line BL1 of the memory; the source of the fourth NMOS transistor 2032 is connected to the first The output end of the two inverters and the input end of the first inverter, the gate is connected to the write word line WL1 of the memory, and the drain is connected to the write inversion bit line BLB1 of the memory; the source of the fifth NMOS transistor 2033 The pole is connected to the output end of the first inverter and the input end of the second inverter, the gate is connected to the read word line WL2 of the memory, and the drain is connected to the read bit line BL2 of the memory; The sources of the six NMOS transistors 2034 are connected to the output terminal of the second inverter and the input terminal of the first inverter, the gate is connected to the read word line WL2 of the memory, and the drain is connected to the read inverter of the memory. bit line BLB2.

As an example, the sources of the first PMOS transistor 2011 and the second PMOS transistor 2021 are connected to the power supply terminal VDD, and the drains are respectively connected to the drains of the first NMOS transistor 2012 and the second NMOS transistor 2022, as a reverse output terminal of the phaser. The gates of the first PMOS transistor 2011 and the second PMOS transistor 2021 are respectively connected to the gates of the first NMOS transistor 2012 and the second NMOS transistor 2022, which serve as the input terminals of the inverter. The sources of the first NMOS transistor 2012 and the second NMOS transistor 2022 are both grounded to the GND, so as to realize the functions of the first inverter 201 and the second inverter 202 . FIG. 5 also shows the positions of the first storage node Q and the second storage node QB.

In particular, in the first inverter 201 and the second inverter 202, the sources of the first and second PMOS transistors 2011 and 2021 and the first and second NMOS transistors 2012 and 2022 are reinforced source region, wherein, for an NMOS transistor, the reinforced source region includes a first heavily doped N-type region, a first heavily doped P-type region, and a shallow N-type region, and the first heavily doped P-type region surrounds the first heavily doped P-type region The vertical ends and the bottom of the first heavily doped N-type region; for PMOS transistors, the reinforced source region includes a second heavily doped P-type region, a second heavily doped N-type region and a shallow P-type region, and The second heavily doped N-type region surrounds both vertical ends and the bottom of the second heavily doped P-type region.

It should be pointed out that in the present invention, parallel to the source-drain direction of the transistor is referred to as "horizontal", and vertical to the source-drain direction of the transistor is referred to as "vertical".

As an example, please refer to FIG. 6 to FIG. 9, which are schematic diagrams showing the structure of an NMOS transistor with a reinforced source region, wherein FIG. 6 is a top view, and FIG. 7 to FIG. 9 are CC' directions and D-D' and EE' sectional views. In the present invention, the SOI eight-transistor SRAM unit adopts an SOI substrate including a back substrate 208, an insulating buried layer 209, and a top layer of silicon from bottom to top, and the active regions where each transistor is located pass through the The top silicon is isolated by shallow trench isolation structures 210 .

Specifically, the back substrate 208 includes, but is not limited to, conventional semiconductor substrates such as Si and Ge, and may have a certain type of doping. In this embodiment, the back substrate 208 is a P-type Si substrate, and the buried insulating layer 209 is silicon dioxide.

As shown in FIGS. 6-9 , the NMOS transistor using a reinforced source region includes a reinforced source region 204 , a drain 205 , a gate 206 and a body region 207 located between the reinforced source region 204 and the drain 205 . The reinforced source region 204 includes a first heavily doped N-type region 2041, a first heavily doped P-type region 2042 and a shallow N-type region 2043, and the first heavily doped P-type region 2042 surrounds the first Both vertical ends and the bottom of the N-type region 2041 are heavily doped. In this embodiment, a sidewall isolation structure 211 is further provided around the gate 206 , and the sidewall isolation structure 211 partially covers the shallow N-type region 2043 . The gate 206 includes a gate dielectric layer 2061 and a polysilicon layer 2062 on the gate dielectric layer 2061 .

Further, as shown in FIG. 7-FIG. 9, a metal silicide 212 is formed on the top of the reinforced source region 204, and the first heavily doped N-type region 2041 and the first heavily doped P-type region 2042 are both compatible with The metal silicide 212 is in contact, and the lateral ends of the shallow N-type region 2043 are respectively in contact with the metal silicide 212 and the body region 207 of the NMOS transistor.

The metal silicide 212 includes but not limited to conductive silicides such as cobalt silicide and titanium silicide, which form ohmic contacts with the first heavily doped N-type region 2041 and the first heavily doped P-type region 2042 . As an example, a metal silicide 212 is also formed on the top of the drain 205 and the gate 206 for reducing the contact resistance between the drain and the gate and the lead-out electrodes.

It should be pointed out that FIGS. 6-9 are schematic structural diagrams of NMOS transistors (the first and second NMOS transistors 2012, 2022) using reinforced source regions. For PMOS transistors using reinforced source regions (the first 1. The structure of the second PMOS transistor 2011, 2021) is basically the same as that of the NMOS transistor with reinforced source region, except that the doping type of each doped region is opposite, which is not shown here.

In the SOI eight-transistor SRAM unit of the present invention, the sources of the four transistors constituting the first inverter and the second inverter all adopt reinforced source regions. For NMOS transistors, the reinforced source regions include the first heavy doped N-type region, first heavily doped P-type region and shallow N-type region, and the first heavily doped P-type region surrounds the vertical ends and the bottom of the first heavily doped N-type region; because The first heavily doped P-type region is in contact with the insulating buried layer at the bottom of the reinforced source region, and is in contact with the shallow trench isolation structure, which can effectively block the interface between BOX and Si material, the shallow trench isolation structure and the The leakage channel at the Si material interface can effectively suppress the Box leakage, upper and lower corner leakage and side wall leakage caused by the total dose effect of SOI devices, and eliminate the traditional anti-total dose reinforcement structure that increases the chip area and cannot fully suppress the total dose effect. Disadvantages of leakage. A similar effect occurs for PMOS transistors employing a reinforced source region.

In addition, in the present invention, for NMOS, strengthening the metal silicide on the upper part of the source region can not only reduce the contact resistance, but also connect the first heavily doped P-type region to a low level, because the first heavily doped The P-type region is in contact with the body region, so that holes accumulated in the body region can be released, thereby effectively suppressing the floating body effect while effectively suppressing the total dose effect, and improving the stability of the unit. A similar effect occurs for PMOS transistors employing a reinforced source region.

For the third NMOS transistor 2031 , the fourth NMOS transistor 2032 , the fifth NMOS transistor 2033 and the sixth NMOS transistor 2034 used in the acquisition transistor 203 , at least one of their sources may use the reinforced source region. The use of a reinforced source region for the NMOS transistor in the acquisition tube 203 has both advantages and disadvantages, which can be selected according to specific applications.

In another embodiment, at least one of the third NMOS transistor 2031, the fourth NMOS transistor 2032, the fifth NMOS transistor 2033 and the sixth NMOS transistor 2034 may adopt a normal gate NMOS transistor, a T-type gate NMOS transistor or a H Type gate NMOS tube. As shown in Figures 10-12, they are respectively shown as a schematic structural diagram of an NMOS transistor using a common gate 213, a T-shaped gate 214, and an H-shaped gate 215. The two sides of the gate are respectively the source region 216 and the drain region 217. For the T-shaped gate The NMOS and H-type gate NMOS transistors also have body contact regions 218 respectively. Common gate NMOS transistors, T-shaped gate NMOS transistors and H-shaped gate NMOS transistors are all well known in the art, and will not be repeated here.

Embodiment two

The present invention also provides a method for fabricating an SOI eight-transistor SRAM unit, comprising the following steps:

Step S1 is first performed: provide an SOI substrate including a back substrate, an insulating buried layer, and a top layer of silicon in sequence from bottom to top, and form a shallow trench isolation structure in the top layer of silicon to define an active region.

As an example, as shown in FIG. 13, six active regions 20a, 20b, 20c, 20d, 20e and 20f are defined, wherein the six active regions 20e, 20a, 20b, 20c, 20d and 20f are arranged in parallel in turn, each A shallow trench is formed around the active area, and the shallow trench is filled with insulating material to form a shallow trench isolation structure. In this embodiment, the insulating material is silicon dioxide.

Then perform step S2: as shown in FIG. 14 , fabricate an N well 30, a first P well 40a, and a second P well 40b in the top silicon according to the position of the active region, wherein the N well 30 is located Between the first P-well 40a and the second P-well 40b.

Specifically, the N well and the first and second P wells are formed by ion implantation. As an example, the N well is implanted with phosphorus ions, and the P well is implanted with boron ions. The N well is used to make a PMOS transistor, and part of its region is used as a body region of the PMOS transistor; the first and second P wells are used to make an NMOS transistor, and a part of its region is used as a body region of the NMOS transistor.

Then execute step S3: as shown in FIG. 15 to FIG. 20 , fabricate the first PMOS transistor 2011 and the second PMOS transistor 2021 in the N well 30; fabricate the first NMOS transistor 2012, 2021 in the first P well 40a. The third NMOS transistor 2031 and the fifth NMOS transistor 2033; the second NMOS transistor 2022, the fourth NMOS transistor 2032 and the sixth transistor 2034 are fabricated in the second P well 40b; wherein, a dotted line box is used in FIG. 16 to show The area where each transistor is located.

In particular, the sources of the first PMOS transistor 2011 , the first NMOS transistor 2012 , the second PMOS transistor 2021 and the second NMOS transistor 2023 all use reinforced source regions. For an NMOS transistor, the reinforced source region includes a first heavily doped N-type region, a first heavily doped P-type region, and a shallow N-type region, and the first heavily doped P-type region surrounds the first heavily doped P-type region. Doping the vertical ends and bottom of the N-type region; for PMOS transistors, the reinforced source region includes a second heavily doped P-type region, a second heavily doped N-type region, and a shallow P-type region, and the second The heavily doped N-type region surrounds both vertical ends and the bottom of the second heavily doped P-type region.

As an example, the step S3 includes the steps of:

S3-1: As shown in FIG. 15 , forming a first gate 50 a spanning the first P well 40 a and the N well 30 and a second gate 50 b spanning the N well 30 and the second P well 40 b , and form a third gate 50c at a preset position of the first P well 40a, and form a fourth gate 50d at a preset position of the second P well 40b; the first gate 50a is the first The NMOS transistor 2012 and the first PMOS transistor 2011 are shared; the second gate 50b is shared by the second NMOS transistor 2022 and the second PMOS transistor 2021; the third gate 50c is the The third NMOS transistor 2031 is shared by the fifth NMOS transistor 2033 ; the fourth gate 50 d is shared by the fourth NMOS transistor 2032 and the sixth NMOS transistor 2034 .

Specifically, the first, second, third, and fourth gates 50a, 50b, 50c, and 50d all include a gate dielectric layer and a polysilicon layer on the gate dielectric layer.

S3-2: As shown in FIG. 17 , perform N-type light doping at the preset positions of the first and second P wells 40a and 40b to form the first, second, third, fourth and fifth wells. , the shallow N-type regions of the sixth NMOS transistors 2012, 2022, 2031, 2032, 2033, and 2034; performing P-type light doping at the preset position of the N well 30 to form the first and second PMOS transistors 2011, Shallow P-type area in 2021.

It should be pointed out that, for the convenience of illustration, only the shallow N-type regions 60a, 60b and the first and second NMOS transistors 2012, 2022 in the regions where the reinforced source regions are located are shown in FIG. 17 . The second PMOS transistors 2011, 2021 reinforce the shallow P-type regions 70a, 70b in the regions where the source regions are located.

S3-3: As shown in FIG. 18 , form sidewall isolation structures 211 around the first, second, third, and fourth gates 50a, 50b, 50c, and 50d, and The preset positions of the P wells 40a and 40b are heavily doped with P-type to form the middle parts 80a and 80b of the first heavily doped P-type regions in the reinforced source regions of the first and second NMOS transistors 2012 and 2022 N-type heavy doping is carried out at the preset position of the N well 30 to form the middle part 90a of the second heavily doped N-type region in the reinforced source regions of the first and second PMOS transistors 2011 and 2021 , 90b.

Specifically, a mask with an opening in the longitudinal middle section of the reinforced source region is used, and ion implantation is performed vertically through the mask to complete the P-type heavy doping or the N-type heavy doping. In this embodiment, the concentration range of the ion implantation is 1E15-9E15/cm ² . By controlling the energy of ion implantation, the ion concentration peak is close to the lower part of the reinforced source region.

S3-4: As shown in FIG. 19 , perform N-type heavy doping in the regions above the first heavily doped P-type regions in the first and second P wells 40a and 40b by ion implantation, Form the first heavily doped N-type regions 91a, 91b in the reinforced source regions of the first and second NMOS transistors 2012, 2022; The region above the region is heavily P-doped to form the second heavily doped P-type region 92a, 92b in the reinforced source region of the first and second PMOS transistors 2011, 2021.

Specifically, in this step, when forming the first heavily doped N-type regions 91a, 91b, N-type heavy doping is also performed at the preset positions of the first and second P wells 40a, 40b at the same time to form the first heavily doped N-type regions 91a, 91b. 1. The drains of the second NMOS transistors 2012 and 2022 and the sources and drains of the third, fourth, fifth and sixth NMOS transistors 2031, 2032, 2033 and 2034; when forming the second heavily doped P When the region 92a, 92b is formed, the preset position of the N well 30 is heavily doped with P type at the same time to form the drains of the first and second PMOS transistors 2011, 2021.

In this embodiment, the drain of the first NMOS transistor 2012 is shared with the source of the third NMOS transistor 2031; the drain of the second NMOS transistor 2032 is shared with the source of the fourth NMOS transistor 2022 .

S3-5: As shown in FIG. 20 , perform P-type heavy doping at preset positions of the first and second P wells 91a and 91b to form reinforced source regions of the first and second NMOS transistors 2012 and 2022 The two end portions 80a', 80b' of the first heavily doped P-type region in the first heavily doped P-type region; N-type heavily doped at the preset position of the N well 30 to form the first and second PMOS transistors 2011, 2021 to strengthen the two end portions 90a', 90b' of the second heavily doped N-type region in the source region.

Further, in this step, a step (not shown) of forming a metal silicide on the upper part of the reinforced source region is also included; for NMOS transistors, the first heavily doped metal silicide and the reinforced source region The N-type region, the first heavily doped P-type region, and the shallow N-type region are all in contact with each other; for a PMOS transistor, the metal silicide is in contact with the second heavily doped P-type region and the second heavily doped region of the reinforced source region. Both the hetero N-type region and the shallow P-type region are in contact with each other.

Specifically, the metal silicide is formed by forming a metal layer on the reinforced source region and heat-treating the metal layer to react with the underlying Si material. In this embodiment, the temperature range of the heat treatment is 700-900° C., and the time is 50-70 seconds.

Specifically, while metal silicide is formed on the upper part of the reinforced source region, the drains and gates of the first and second PMOS transistors 2011 and 2021 and the first and second NMOS transistors 2012 and 2022 can also be formed. forming a metal silicide, and forming a metal silicide on the source, drain, and gate of the third, fourth, fifth, and sixth NMOS transistors 2031, 2032, 2033, and 2034 to reduce the source, drain, and gate Contact resistance with the lead-out electrode.

Finally, step S4 is executed: making metal vias and corresponding metal connections to complete the making of the memory unit.

Specifically, the first NMOS transistor 2012 is interconnected with the first PMOS transistor 2011 to form a first inverter; the second NMOS transistor 2022 is interconnected with the second PMOS transistor 2021 to form a second inverter ; The source of the third NMOS transistor 2031 is connected to the output terminal of the first inverter and the input terminal of the second inverter, the gate is connected to the write word line of the memory, and the drain is connected to the memory Write bit line; the source of the fourth NMOS transistor 2032 is connected to the output terminal of the second inverter and the input terminal of the first inverter, the gate is connected to the write word line of the memory, and the drain is connected to To the write inversion bit line of the memory; the source of the fifth NMOS transistor 2033 is connected to the output terminal of the first inverter and the input terminal of the second inverter, and the gate is connected to the read word of the memory line, the drain is connected to the read bit line of the memory; the source of the sixth NMOS transistor 2034 is connected to the output terminal of the second inverter and the input terminal of the first inverter, and the gate is connected to The read word line of the memory, the drain is connected to the read reverse bit line of the memory.

The manufacturing method of the SOI eight-transistor static random access memory unit of the invention has the advantages of simple manufacturing process, compatibility with conventional CMOS technology, and the like.

In summary, in the SOI eight-transistor SRAM unit of the present invention, the sources of the four transistors constituting the first inverter and the second inverter all use reinforced source regions. For NMOS transistors, the reinforced source regions The region includes a first heavily doped N-type region, a first heavily doped P-type region, and a shallow N-type region, and the first heavily doped P-type region surrounds two longitudinal sides of the first heavily doped N-type region. end and bottom; for a PMOS transistor, the reinforced source region includes a second heavily doped P-type region, a second heavily doped N-type region, and a shallow P-type region, and the second heavily doped N-type region surrounds the The longitudinal ends and the bottom of the second heavily doped P-type region. The reinforced source region can effectively suppress Box leakage, upper and lower corner leakage, and sidewall leakage caused by the total dose effect of the SOI device without increasing the area of the device. And the present invention can also suppress the floating body effect of the transistor while effectively suppressing the total dosage effect. The present invention eliminates the disadvantages of traditional anti-total dose reinforcement structure increasing the chip area and being unable to fully suppress the leakage caused by the total dose effect, and the manufacturing method of the SOI eight-transistor SRAM unit of the present invention also has the advantages of simple manufacturing process, which is different from the conventional CMOS process Compatibility and other advantages. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (19)

1. a kind of SOI eight-transistor static random access memory units, the SOI eight-transistor static random access memory units bag Include：

First phase inverter, is made up of the first PMOS transistor and the first nmos pass transistor；

Second phase inverter, is made up of the second PMOS transistor and the second nmos pass transistor；

Pipe is obtained, by the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor and the 6th nmos pass transistor group Into；

Wherein, the source electrode of the 3rd NMOS tube be connected to first phase inverter output end and second phase inverter it is defeated Enter end, grid is connected to the write word line of memory, and drain electrode is connected to the write bit line of memory；

The source electrode of 4th nmos pass transistor be connected to second phase inverter output end and first phase inverter it is defeated Enter end, grid is connected to the write word line of memory, what drain electrode was connected to memory writes antiposition line；

The source electrode of 5th NMOS tube is connected to the output end of first phase inverter and the input of second phase inverter, Grid is connected to the readout word line of memory, and drain electrode is connected to the sense bit line of memory；

The source electrode of 6th nmos pass transistor be connected to second phase inverter output end and first phase inverter it is defeated Enter end, grid is connected to the readout word line of memory, and drain electrode is connected to the reading antiposition line of memory；

It is characterized in that：

The source electrode of first, second PMOS transistor and first, second nmos pass transistor is using reinforcing source region；For NMOS Transistor, the reinforcing source region includes the first heavily doped N-type area, the first heavily doped P-type area and shallow n-type area, and described first Heavily doped P-type area surrounds longitudinal two ends and bottom in the first heavily doped N-type area；For PMOS transistor, the reinforcing source Area includes the second heavily doped P-type area, the second heavily doped N-type area and shallow p type island region, and the second heavily doped N-type area surrounds institute State longitudinal two ends and bottom in the second heavily doped P-type area.

2. SOI eight-transistor static random access memory units according to claim 1, it is characterised in that：The reinforcing source Area top is formed with metal silicide；For nmos pass transistor, the first heavily doped N-type area and the first heavily doped P-type area are equal Be in contact with the metal silicide, and the shallow n-type area transverse ends respectively with the metal silicide and the NMOS The body area of transistor is in contact；For PMOS transistor, the second heavily doped P-type area and the second heavily doped N-type area are and institute Metal silicide is stated to be in contact, and the shallow p type island region transverse ends respectively with the metal silicide and the PMOS crystal Guan Ti areas are in contact.

3. SOI eight-transistor static random access memory units according to claim 2, it is characterised in that：The metallic silicon Any one of compound in cobalt silicide and titanium silicide.

4. SOI eight-transistor static random access memory units according to claim 1, it is characterised in that：Described first, The drain electrode top of two PMOS transistors and first, second nmos pass transistor is each formed with metal silicide.

5. SOI eight-transistor static random access memory units according to claim 1, it is characterised in that：The SOI eight is brilliant Body pipe static random access memory cell using the SOI substrate at backing bottom, insulating buried layer and top layer silicon is included successively from bottom to top, respectively Isolated between active area where transistor by the fleet plough groove isolation structure up and down through the top layer silicon.

6. SOI eight-transistor static random access memory units according to claim 1, it is characterised in that：Described 3rd, 4th, the source electrode of the five, the 6th nmos pass transistors at least one use the reinforcing source region.

7. SOI eight-transistor static random access memory units according to claim 1, it is characterised in that：Described 3rd, 4th, at least one in the five, the 6th nmos pass transistors uses common grid NMOS tube, T-shaped grid NMOS tube or H type grid NMOS tubes.

8. a kind of preparation method of SOI eight-transistor static random access memory units, it is characterised in that comprise the following steps：

S1：There is provided one includes the SOI substrate at backing bottom, insulating buried layer and top layer silicon successively from bottom to top, in the top layer silicon Fleet plough groove isolation structure is made, active area is defined；

S2：Position according to the active area makes N traps, the first p-well and the second p-well in the top layer silicon, wherein, the N Trap is located between first p-well and the second p-well；

S3：The first PMOS transistor and the second PMOS transistor are made in the N traps；First is made in first p-well Nmos pass transistor, the 3rd nmos pass transistor and the 5th nmos pass transistor；Made in second p-well the second nmos pass transistor, 4th nmos pass transistor and the 6th nmos pass transistor；Wherein, first PMOS transistor, the first nmos pass transistor, second The source electrode of PMOS transistor and the second nmos pass transistor is using reinforcing source region；For nmos pass transistor, the reinforcing source region bag Include the first heavily doped N-type area, the first heavily doped P-type area and shallow n-type area, and the first heavily doped P-type area surrounds described the Longitudinal two ends and bottom in one heavily doped N-type area；For PMOS transistor, the reinforcing source region include the second heavily doped P-type area, Second heavily doped N-type area and shallow p type island region, and the second heavily doped N-type area surrounds the longitudinal direction in the second heavily doped P-type area Two ends and bottom；

S4：Metallic vias and respective metal line are made, to complete the making of the memory cell.

9. the preparation method of SOI eight-transistor static random access memory units according to claim 8, it is characterised in that： The step S3 includes step：

S3-1：Form the first grid across first p-well and the N traps and cross over the N traps and the second gate of the second p-well Pole, and in the first p-well predeterminated position the 3rd grid of formation, in the second p-well predeterminated position the 4th grid of formation；It is described First grid is shared by first nmos pass transistor and first PMOS transistor；The second grid is described second Nmos pass transistor and second PMOS transistor are shared；

S3-2：N-type is carried out in the first, second p-well predeterminated position to be lightly doped, formation described first, second, third, fourth, The shallow n-type area of 5th and the 6th nmos pass transistor；In the N traps predeterminated position p-type is carried out to be lightly doped, formed it is described first, the The shallow p type island region of two PMOS transistors；

S3-3：Side wall isolation structure is formed around first, second, third, fourth grid, and in first, second P Trap predeterminated position carries out p-type heavy doping, and described first formed in the reinforcing source region of first, second nmos pass transistor is heavily doped The center section of miscellaneous p type island region；N-type heavy doping is carried out in the N traps predeterminated position, first, second PMOS transistor is formed Reinforcing source region in the second heavily doped N-type area center section；

S3-4：It is located at the region above the first heavily doped P-type area in first, second p-well and carries out N-type heavy doping, The the first heavily doped N-type area formed in the reinforcing source region of first, second nmos pass transistor；It is located in the N traps Region above the second heavily doped N-type area carries out p-type heavy doping, forms the reinforcing of first, second PMOS transistor The second heavily doped P-type area in source region；

S3-5：P-type heavy doping is carried out in the first, second p-well predeterminated position, first, second nmos pass transistor is formed Reinforcing source region in the first heavily doped P-type area two end portions；N-type heavy doping, shape are carried out in the N traps predeterminated position Into the two end portions in the second heavily doped N-type area in the reinforcing source region of first, second PMOS transistor.

10. the preparation method of SOI eight-transistor static random access memory units according to claim 9, it is characterised in that： In the step S3-3, using the mask plate for being provided with opening in the longitudinal interlude of reinforcing source region together, via the mask Version vertically carries out ion implanting, completes the p-type heavy doping or the N-type heavy doping.

11. the preparation method of SOI eight-transistor static random access memory units according to claim 10, its feature exists In：The concentration range of the ion implanting is 1E15-9E15/cm²。

12. the preparation method of SOI eight-transistor static random access memory units according to claim 9, it is characterised in that： In the step S3-4, be additionally included in the first, second p-well predeterminated position carry out N-type heavy doping to form described first, Second, third, fourth, fifth, the 6th nmos transistor drain and the three, the four, the five, the 6th nmos pass transistor source Pole, carries out p-type heavy doping to form the step of first, second PMOS transistor drains in the N traps predeterminated position.

13. the preparation method of SOI eight-transistor static random access memory units according to claim 12, its feature exists In：The drain electrode of first nmos pass transistor is shared with the source electrode of the 3rd nmos pass transistor；Second nmos pass transistor Drain electrode shared with the source electrode of the 4th nmos pass transistor.

14. the preparation method of SOI eight-transistor static random access memory units according to claim 8, it is characterised in that： In the step S3, the step of metal silicide is formed at the reinforcing source region top is additionally included in；For nmos pass transistor, institute State metal silicide and the first heavily doped N-type area, the first heavily doped P-type area and shallow n-type area of the reinforcing source region are mutual Contact；For PMOS transistor, the metal silicide and the second heavily doped P-type area for reinforcing source region, the second heavy doping N Type area and shallow p type island region are contacted with each other.

15. the preparation method of SOI eight-transistor static random access memory units according to claim 14, its feature exists In：By forming metal level in the reinforcing source region, and being heat-treated makes the metal level be reacted with the Si materials under it, generation The metal silicide.

16. the preparation method of SOI eight-transistor static random access memory units according to claim 15, its feature exists In：The temperature range of the heat treatment is 700-900 DEG C, and the time is 50-70 seconds.

17. the preparation method of SOI eight-transistor static random access memory units according to claim 14, its feature exists In：In the step S3, the drain electrode of first, second PMOS transistor and first, second nmos pass transistor is additionally included in The step of metal silicide being formed with grid top, and in the source and drain of the three, the four, the five, the 6th nmos pass transistor The step of pole forms metal silicide with grid top.

18. the preparation method of SOI eight-transistor static random access memory units according to claim 8, it is characterised in that： First nmos pass transistor is interconnected and form the first phase inverter with first PMOS transistor；Second nmos pass transistor with Second PMOS transistor is interconnected and form the second phase inverter；The source electrode of 3rd NMOS tube is connected to first phase inverter Output end and second phase inverter input, grid is connected to the write word line of memory, and drain electrode is connected to memory Write bit line；The source electrode of 4th nmos pass transistor is connected to the output end and first phase inverter of second phase inverter Input, grid is connected to the write word line of memory, and what drain electrode was connected to memory writes antiposition line；The source of 5th NMOS tube Pole is connected to the output end of first phase inverter and the input of second phase inverter, and grid is connected to the reading word of memory Line, drain electrode is connected to the sense bit line of memory；The source electrode of 6th nmos pass transistor is connected to the defeated of second phase inverter Go out the input of end and first phase inverter, grid is connected to the readout word line of memory, and the reading that drain electrode is connected to memory is anti- Bit line.

19. the preparation method of SOI eight-transistor static random access memory units according to claim 8, it is characterised in that： First, second, third, fourth grid includes gate dielectric layer and the polysilicon layer on the gate dielectric layer.