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CN106946212A - A kind of surface quantum point humidity sensor chip - Google Patents

A kind of surface quantum point humidity sensor chip Download PDF

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Publication number
CN106946212A
CN106946212A CN201710316751.8A CN201710316751A CN106946212A CN 106946212 A CN106946212 A CN 106946212A CN 201710316751 A CN201710316751 A CN 201710316751A CN 106946212 A CN106946212 A CN 106946212A
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quantum dot
silicon dioxide
ingaas
passivation layer
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王国东
刘小莲
徐永豪
王昊
杨莹丽
李国政
刘志刚
杨美荣
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Henan University of Technology
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    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
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    • B81B3/0018Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
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    • G01N21/62Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light
    • G01N21/63Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light optically excited
    • G01N21/64Fluorescence; Phosphorescence
    • G01N21/6402Atomic fluorescence; Laser induced fluorescence

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Abstract

It is an object of the present invention to provide a kind of surface quantum point humidity sensor chip, including GaAs from bottom to top(GaAs)Substrate layer, N-shaped GaAs cushions, bury InGaAs quantum dot layers and InGaAs surface quantums point layer, bury and be deposited with the first silicon dioxide passivation layer on InGaAs quantum dot layer left end steps, bury and be deposited with the second silicon dioxide passivation layer on InGaAs quantum dot layer right-hand member steps, the lower right side of second silicon dioxide passivation layer is deposited with the 3rd silicon dioxide passivation layer on N-shaped GaAs cushions, Au/Ge/Ni alloy bottom electrodes are deposited with above 3rd silicon dioxide passivation layer, InGaAs surface quantums point layer has the 4th silicon dioxide passivation layer above the left side, deposition has Au/Ge/Ni alloy Top electrodes in 4th silicon dioxide passivation layer;The present invention is simple in construction, and prepared by production convenient, and low cost, effect is good, and economic and social benefit is notable.

Description

一种表面量子点湿度传感器芯片A surface quantum dot humidity sensor chip

技术领域technical field

本发明涉及半导体电子器件,特别是一种表面量子点湿度传感器芯片。The invention relates to a semiconductor electronic device, in particular to a surface quantum dot humidity sensor chip.

背景技术Background technique

量子点又称半导体纳米晶,与块体材料相比,其尺寸小、比表面积大、表面能高、表面原子比例大,当其粒径小于激子玻尔半径时,导致粒子的电子状态发生突变,从而显现出基本的小尺寸效应、表面效应、量子效应和宏观量子隧道效应;由于其独特的光电性质,如高的量子产率、长的荧光寿命、大的消光系数、强的光耐受性、窄的发射谱和较宽的激发光谱等,量子点的制备和应用引起了人们广泛的关注;尤其是在传感领域,量子点已经用于构建传感器,如离子传感器、生物传感器、荧光探针、医学成像和气敏传感器等。Quantum dots are also called semiconductor nanocrystals. Compared with bulk materials, they have small size, large specific surface area, high surface energy, and large surface atomic ratio. When the particle size is smaller than the exciton Bohr radius, the electronic state of the particle will occur. Mutation, thus showing the basic small size effect, surface effect, quantum effect and macroscopic quantum tunneling effect; due to its unique photoelectric properties, such as high quantum yield, long fluorescence lifetime, large extinction coefficient, strong light resistance Receptivity, narrow emission spectrum and wide excitation spectrum, etc., the preparation and application of quantum dots have attracted widespread attention; especially in the field of sensing, quantum dots have been used to build sensors, such as ion sensors, biosensors, Fluorescent probes, medical imaging and gas sensors, etc.

量子点的制备方法主要包括物理制备法和化学制备法两种,化学制备法主要用来合成CdSe、ZnS、CdS、CdTe、HgS等量子点材料,但是这些量子点材料在与目前的硅基和GaAs基等广泛使用的光电子器件集成方面存在巨大的挑战。相比而言,采用MOCVD、MBE等物理方法制备的III-V族量子点在系统集成方面具有天然的优势,如InGaAs、InP量子点等,已经广泛应用于激光器、红外探测器、太阳能电池等领域。The preparation methods of quantum dots mainly include two kinds of physical preparation method and chemical preparation method. The chemical preparation method is mainly used to synthesize quantum dot materials such as CdSe, ZnS, CdS, CdTe, HgS, etc., but these quantum dot materials are different from the current silicon-based and There are enormous challenges in the integration of widely used optoelectronic devices such as GaAs-based. In contrast, III-V quantum dots prepared by physical methods such as MOCVD and MBE have natural advantages in system integration, such as InGaAs and InP quantum dots, which have been widely used in lasers, infrared detectors, solar cells, etc. field.

上述量子点器件中,为了提高器件的性能,往往需要在量子点的表面覆盖一层宽禁带半导体材料(盖帽层),如在InGaAs量子点的表面覆盖一层GaAs,来抑制表面态对量子点器件光学性能和电学性能的影响;如果在量子点表面不覆盖盖帽层,就形成了表面量子点。表面量子点表面存在大量的悬挂键,形成表面态。表面态对H2O分子具有吸附作用,抑制了表面态的非辐射复合,进而影响表面量子点的光学特性和电学特性。因此,采用In(Ga)As表面量子点作为敏感材料,利用表面态对量子点光学性能、电学性能的影响,易于实现对水分子探测的系统集成和片上集成,实现对空气中湿度的感知测量。In the above-mentioned quantum dot devices, in order to improve the performance of the device, it is often necessary to cover a layer of wide-bandgap semiconductor material (capping layer) on the surface of the quantum dots, such as covering a layer of GaAs on the surface of the InGaAs quantum dots to suppress the impact of the surface state on the quantum dots. The influence of the optical performance and electrical performance of the dot device; if the cap layer is not covered on the surface of the quantum dot, the surface quantum dot is formed. There are a large number of dangling bonds on the surface of surface quantum dots, forming surface states. The surface states have an adsorption effect on H 2 O molecules, which inhibits the non-radiative recombination of the surface states, thereby affecting the optical and electrical properties of the surface quantum dots. Therefore, using In(Ga)As surface quantum dots as a sensitive material, using the influence of surface states on the optical and electrical properties of quantum dots, it is easy to realize the system integration and on-chip integration of water molecule detection, and realize the sensory measurement of humidity in the air .

但是目前的量子点传感器主要是采用单层的量子点,其应用于湿度传感还存在如下困难,(1)CdSe、ZnS、CdS、CdTe、HgS等量子点难于和目前的GaAs基光电子器件集成,不利于片上系统和集成系统的发展;(2)需要有配套的激发光源和光学探测器,这大大增加了传感器的复杂程度和成本;(3)单层量子点的性能还不够优化,如量子点尺寸均匀性较差、发光强度较弱、发光光谱带宽较大等。However, the current quantum dot sensors mainly use single-layer quantum dots, and there are still the following difficulties in their application to humidity sensing. (1) Quantum dots such as CdSe, ZnS, CdS, CdTe, and HgS are difficult to integrate with current GaAs-based optoelectronic devices , which is not conducive to the development of on-chip systems and integrated systems; (2) supporting excitation light sources and optical detectors are required, which greatly increases the complexity and cost of sensors; (3) the performance of single-layer quantum dots is not optimized enough, such as The size uniformity of quantum dots is poor, the luminous intensity is weak, and the luminous spectral bandwidth is large.

发明内容Contents of the invention

针对上述情况,为克服现有技术之缺陷,本发明之目的是提供一种表面量子点湿度传感器芯片,可有效解决现有单层量子点湿度传感器量子点尺寸均匀性差、发光强度弱、光谱带宽较大、使用复杂、效果不尽人意的问题。In view of the above situation, in order to overcome the defects of the prior art, the purpose of the present invention is to provide a surface quantum dot humidity sensor chip, which can effectively solve the problem of poor uniformity of quantum dot size, weak luminous intensity and spectral bandwidth of the existing single-layer quantum dot humidity sensor. Larger, complex to use, less-than-satisfactory issues.

本发明解决的技术方案是,本发明包括由下而上的GaAs(砷化镓)衬底层、n型GaAs缓冲层、掩埋InGaAs量子点层和InGaAs表面量子点层,掩埋InGaAs量子点层与n型GaAs缓冲层左右两端均成台阶状结构,掩埋InGaAs量子点层左端台阶上淀积有竖向的第一二氧化硅钝化层,且第一二氧化硅钝化层与n型GaAs缓冲层的端面平齐,掩埋InGaAs量子点层右端台阶上淀积有垂直的第二二氧化硅钝化层,第二二氧化硅钝化层的右侧下部在n型GaAs缓冲层上淀积有横向的第三二氧化硅钝化层,第三二氧化硅钝化层的上面淀积有与n型GaAs缓冲层连通的Au/Ge/Ni合金下电极,InGaAs表面量子点层左边上面有与第一二氧化硅钝化层相连在一起的横向的第四二氧化硅钝化层,第四二氧化硅钝化层上沉积有与InGaAs表面量子点层连通的Au/Ge/Ni合金上电极。The technical scheme solved by the present invention is that the present invention includes a bottom-up GaAs (gallium arsenide) substrate layer, an n-type GaAs buffer layer, a buried InGaAs quantum dot layer and an InGaAs surface quantum dot layer, and the buried InGaAs quantum dot layer and the n-type The left and right ends of the n-type GaAs buffer layer are all in a stepped structure, and a vertical first silicon dioxide passivation layer is deposited on the left end step of the buried InGaAs quantum dot layer, and the first silicon dioxide passivation layer is connected with the n-type GaAs buffer layer. The end face of the layer is even, and a vertical second silicon dioxide passivation layer is deposited on the right end step of the buried InGaAs quantum dot layer, and the right lower part of the second silicon dioxide passivation layer is deposited on the n-type GaAs buffer layer. The third silicon dioxide passivation layer in the lateral direction, the Au/Ge/Ni alloy lower electrode connected to the n-type GaAs buffer layer is deposited on the third silicon dioxide passivation layer, and the quantum dot layer on the left side of the InGaAs surface has a layer with The first silicon dioxide passivation layer is connected to the lateral fourth silicon dioxide passivation layer, and the Au/Ge/Ni alloy upper electrode connected to the InGaAs surface quantum dot layer is deposited on the fourth silicon dioxide passivation layer .

本发明结构简单,生产制备方便,成本低,效果好,该结构中多层掩埋量子点的存在使得湿度传感器的灵敏度更高,经济和社会效益显著。The invention has the advantages of simple structure, convenient production and preparation, low cost and good effect. The presence of multi-layer buried quantum dots in the structure makes the humidity sensor more sensitive and has remarkable economic and social benefits.

附图说明Description of drawings

图1为本发明的剖面结构主视图。Fig. 1 is the front view of the sectional structure of the present invention.

具体实施方式detailed description

以下结合附图对本发明的具体实施方式做详细说明。The specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings.

如图1所示,本发明包括由下而上的GaAs(砷化镓)衬底层1、n型GaAs缓冲层2、掩埋InGaAs量子点层3和InGaAs表面量子点层4,掩埋InGaAs量子点层3上覆盖有一层GaAs,掩埋InGaAs量子点层3与n型GaAs缓冲层2左右两端均成台阶状结构,掩埋InGaAs量子点层3左端台阶上淀积有竖向的第一二氧化硅钝化层5,且第一二氧化硅钝化层5与n型GaAs缓冲层2的端面平齐,掩埋InGaAs量子点层3右端台阶上淀积有垂直的第二二氧化硅钝化层8,第二二氧化硅钝化层8的右侧下部在n型GaAs缓冲层2上淀积有横向的第三二氧化硅钝化层7,第三二氧化硅钝化层7的上面淀积有与n型GaAs缓冲层2连通的Au/Ge/Ni合金下电极10,InGaAs表面量子点层4左边上面有与第一二氧化硅钝化层5相连在一起的横向的第四二氧化硅钝化层6,第四二氧化硅钝化层6上沉积有与InGaAs表面量子点层4连通的Au/Ge/Ni合金上电极9。As shown in Figure 1, the present invention includes a bottom-up GaAs (gallium arsenide) substrate layer 1, an n-type GaAs buffer layer 2, a buried InGaAs quantum dot layer 3 and an InGaAs surface quantum dot layer 4, and the buried InGaAs quantum dot layer 3 is covered with a layer of GaAs, the buried InGaAs quantum dot layer 3 and the left and right ends of the n-type GaAs buffer layer 2 are in a stepped structure, and the left end step of the buried InGaAs quantum dot layer 3 is deposited with a vertical first silicon dioxide passivation layer. layer 5, and the first silicon dioxide passivation layer 5 is flush with the end face of the n-type GaAs buffer layer 2, and a vertical second silicon dioxide passivation layer 8 is deposited on the right end step of the buried InGaAs quantum dot layer 3, On the lower right side of the second silicon dioxide passivation layer 8, a lateral third silicon dioxide passivation layer 7 is deposited on the n-type GaAs buffer layer 2, and a third silicon dioxide passivation layer 7 is deposited on the third silicon dioxide passivation layer 7. The Au/Ge/Ni alloy lower electrode 10 connected with the n-type GaAs buffer layer 2, the fourth silicon dioxide passivation layer connected with the first silicon dioxide passivation layer 5 on the left side of the InGaAs surface quantum dot layer 5 An Au/Ge/Ni alloy upper electrode 9 communicating with the InGaAs surface quantum dot layer 4 is deposited on the fourth silicon dioxide passivation layer 6 .

为了保证使用效果和使用方便,In order to ensure the effect and convenience of use,

所述掩埋InGaAs量子点层3为1-15层,(图中给出5层)。The buried InGaAs quantum dot layer 3 is 1-15 layers (5 layers are given in the figure).

所述掩埋InGaAs量子点层每层3的厚度不大于20nm。The thickness of each layer 3 of the buried InGaAs quantum dot layer is not greater than 20nm.

所述的芯片为圆形。The chip is circular.

本发明在具体实施中,In the specific implementation of the present invention,

1、所述的n型GaAs缓冲层使用分子束外延技术在砷化镓衬底上面生长制成;1. The n-type GaAs buffer layer is grown on a gallium arsenide substrate by molecular beam epitaxy;

2、所述的掩埋InGaAs量子点层使用分子束外延技术在n型GaAs缓冲层上面生长制成,每层掩埋InGaAs量子点层的厚度为20nm;2. The buried InGaAs quantum dot layer is grown on the n-type GaAs buffer layer by molecular beam epitaxy, and the thickness of each buried InGaAs quantum dot layer is 20nm;

3、所述的InGaAs表面量子点层使用分子束外延技术在掩埋InGaAs量子点层上生长制成;3. The InGaAs surface quantum dot layer is grown on the buried InGaAs quantum dot layer by molecular beam epitaxy;

4、所述的台阶使用湿法刻蚀工艺在n型GaAs缓冲层与掩埋InGaAs量子点层之间刻蚀而成;4. The step is etched between the n-type GaAs buffer layer and the buried InGaAs quantum dot layer using a wet etching process;

5、所述的二氧化硅钝化层在刻蚀后的台阶上淀积而成;5. The silicon dioxide passivation layer is deposited on the etched steps;

6、所述的Au/Ge/Ni合金上电极和Au/Ge/Ni合金下电极是在二氧化硅钝化层上光刻、腐蚀出引线孔,并在引线孔中蒸度Au/Ge/Ni制成;6. The upper electrode of the Au/Ge/Ni alloy and the lower electrode of the Au/Ge/Ni alloy are photoetched on the silicon dioxide passivation layer, and lead holes are etched, and the Au/Ge/Ni alloy is evaporated in the lead holes. Made of Ni;

与现有技术相比,本发明具有以下有益技术效果:Compared with the prior art, the present invention has the following beneficial technical effects:

(1)采用InGaAs表面量子点作为敏感材料,易于实现与现有的GaAs基光电子器件的集成,有利于片上系统集成度的提高,可为多功能的片上集成系统的实现奠定基础;(1) Using InGaAs surface quantum dots as a sensitive material, it is easy to realize integration with existing GaAs-based optoelectronic devices, which is conducive to improving the integration of on-chip systems, and can lay the foundation for the realization of multi-functional on-chip integrated systems;

(2)采用在多层掩埋量子点上生长一层表面InGaAs量子点,可以分别独立地控制表面量子点的密度和尺寸,并提高量子点的均匀度。例如当掩埋量子点层数为8时,表面量子点的平均高度为6.7±0.7 nm,平均直径为46±1.8nm,而当掩埋量子点层数为1时,表面量子点的平均高度为6.7±1.3 nm,平均直径为46±6nm。(2) By growing a layer of surface InGaAs quantum dots on the multi-layer buried quantum dots, the density and size of the surface quantum dots can be independently controlled, and the uniformity of the quantum dots can be improved. For example, when the number of buried quantum dot layers is 8, the average height of the surface quantum dots is 6.7±0.7 nm, and the average diameter is 46±1.8 nm, while when the number of buried quantum dot layers is 1, the average height of the surface quantum dots is 6.7 nm. ±1.3 nm, with an average diameter of 46±6nm.

(3)利用多层掩埋量子点与表面量子点之间的强耦合作用,该结构不需要配套的激发光源和光学探测器,只需要直接测量上、下电极间的电阻值,即可实现环境湿度的测量,具有结构简单、成本低的优势。成本低的具体体现为目前市场上的激发光源(如100mW的激发波长为532nm的激光器)的价格在9000元左右,光学探测器(如InGaAs探测器)的价格在15000元左右。该结构不需要配套的激发光源和光学探测器,可节约成本24000元左右。(3) Utilizing the strong coupling between multi-layer buried quantum dots and surface quantum dots, this structure does not require supporting excitation light sources and optical detectors, and only needs to directly measure the resistance value between the upper and lower electrodes to realize environmental protection. The measurement of humidity has the advantages of simple structure and low cost. The low cost is specifically reflected in the fact that the price of the excitation light source (such as a 100mW laser with an excitation wavelength of 532nm) on the market is about 9,000 yuan, and the price of an optical detector (such as an InGaAs detector) is about 15,000 yuan. This structure does not require matching excitation light sources and optical detectors, which can save about 24,000 yuan in cost.

(4)与单层表面量子点相比,该结构中多层掩埋量子点的存在使得湿度传感器的灵敏度更高,且掩埋量子点的层数越多,灵敏度越高。例如,测试结果表明,当环境湿度为30%时,只包含一层掩埋量子点结构的响应电流为2.3微安,包含五层掩埋量子点结构的响应电流为11.6微安,包含十层掩埋量子点结构的响应电流为18.7微安。(4) Compared with single-layer surface quantum dots, the existence of multi-layer buried quantum dots in this structure makes the humidity sensor more sensitive, and the more layers of buried quantum dots, the higher the sensitivity. For example, the test results show that when the ambient humidity is 30%, the response current of the structure containing only one layer of buried quantum dots is 2.3 microamps, the response current of the structure containing five layers of buried quantum dots is 11.6 microamps, and the response current of the structure containing ten layers of buried quantum dots is 11.6 microamps. The response current of the dot structure was 18.7 microamps.

Claims (4)

1.一种表面量子点湿度传感器芯片,其特征是:包括由下而上的GaAs(砷化镓)衬底层(1)、n型GaAs缓冲层(2)、掩埋InGaAs量子点层(3)和InGaAs表面量子点层(4),掩埋InGaAs量子点层(3)上覆盖有一层GaAs,掩埋InGaAs量子点层(3)与n型GaAs缓冲层(2)左右两端均成台阶状结构,掩埋InGaAs量子点层(3)左端台阶上淀积有竖向的第一二氧化硅钝化层(5),且第一二氧化硅钝化层(5)与n型GaAs缓冲层(2)的端面平齐,掩埋InGaAs量子点层(3)右端台阶上淀积有垂直的第二二氧化硅钝化层(8),第二二氧化硅钝化层(8)的右侧下部在n型GaAs缓冲层(2)上淀积有横向的第三二氧化硅钝化层(7),第三二氧化硅钝化层(7)的上面淀积有与n型GaAs缓冲层(2)连通的Au/Ge/Ni合金下电极(10),InGaAs表面量子点层(4)左边上面有与第一二氧化硅钝化层(5)相连在一起的横向的第四二氧化硅钝化层(6),第四二氧化硅钝化层(6)上沉积有与InGaAs表面量子点层(4)连通的Au/Ge/Ni合金上电极(9)。1. A surface quantum dot humidity sensor chip, characterized in that it includes a bottom-up GaAs (gallium arsenide) substrate layer (1), an n-type GaAs buffer layer (2), and a buried InGaAs quantum dot layer (3) and the InGaAs surface quantum dot layer (4), the buried InGaAs quantum dot layer (3) is covered with a layer of GaAs, and the buried InGaAs quantum dot layer (3) and the n-type GaAs buffer layer (2) both have a stepped structure at the left and right ends, A vertical first silicon dioxide passivation layer (5) is deposited on the left end step of the buried InGaAs quantum dot layer (3), and the first silicon dioxide passivation layer (5) and the n-type GaAs buffer layer (2) The end face of the second silicon dioxide passivation layer (8) is deposited vertically on the right end step of the buried InGaAs quantum dot layer (3), and the lower right side of the second silicon dioxide passivation layer (8) is at the n A third lateral silicon dioxide passivation layer (7) is deposited on the n-type GaAs buffer layer (2), and an n-type GaAs buffer layer (2) is deposited on the third silicon dioxide passivation layer (7). Connected Au/Ge/Ni alloy lower electrode (10), InGaAs surface quantum dot layer (4) has a lateral fourth silicon dioxide passivation layer connected with the first silicon dioxide passivation layer (5) on the left side layer (6), and an Au/Ge/Ni alloy upper electrode (9) communicating with the InGaAs surface quantum dot layer (4) is deposited on the fourth silicon dioxide passivation layer (6). 2.根据权利要求1所述的表面量子点湿度传感器芯片,其特征是:所述掩埋InGaAs量子点层(3)为1-15层。2. The surface quantum dot humidity sensor chip according to claim 1, characterized in that: the buried InGaAs quantum dot layer (3) is 1-15 layers. 3.根据权利要求1所述的表面量子点湿度传感器芯片,其特征是:所述掩埋InGaAs量子点层(3)每层的厚度不大于20nm。3. The surface quantum dot humidity sensor chip according to claim 1, characterized in that: the thickness of each buried InGaAs quantum dot layer (3) is not greater than 20nm. 4.根据权利要求1所述的表面量子点湿度传感器芯片,其特征是:所述的芯片为圆形。4. The surface quantum dot humidity sensor chip according to claim 1, characterized in that: the chip is circular.
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