CN106934079A - A kind of carry chain process mapping method based on fpga chip - Google Patents
A kind of carry chain process mapping method based on fpga chip Download PDFInfo
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- CN106934079A CN106934079A CN201511018760.6A CN201511018760A CN106934079A CN 106934079 A CN106934079 A CN 106934079A CN 201511018760 A CN201511018760 A CN 201511018760A CN 106934079 A CN106934079 A CN 106934079A
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- carry chain
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- 238000012367 process mapping Methods 0.000 title claims abstract description 12
- 238000013507 mapping Methods 0.000 claims abstract description 10
- 238000004364 calculation method Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000007792 addition Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
The present invention relates to a kind of carry chain process mapping method based on fpga chip, the method is comprised the following steps：Obtain whole arithmetic operator macroblocks；Consumption figures estimation is carried out respectively for whole arithmetic operator macroblocks, and whole arithmetic operator macroblocks are ranked up according to the consumption figures of each arithmetic operator macroblock；Calculate available carry chain surplus on fpga chip；The carry chain usage amount of the maximum arithmetic operator macroblock of estimation consumption figures；The carry chain usage amount of the arithmetic operator macroblock maximum with the consumption figures of available carry chain surplus on fpga chip is compared, if the carry chain usage amount of the maximum arithmetic operator macroblock of consumption figures is not more than available carry chain surplus on fpga chip, the maximum arithmetic operator macroblock of consumption figures is mapped using the mode of carry chain.The present invention can dynamically determine whether arithmetic operator macroblock carries out Technology Mapping using carry chain, better meet the design requirement of fpga chip.
Description
Technical field
The present invention relates to field programmable gate array (Field-Programmable Gate Array,
Abbreviation FPGA) technology, more particularly to a kind of carry chain process mapping method based on FPGA.
Background technology
The process mapping method of traditional fpga chip is typically that the arithmetic operator macroblock such as addition, multiplication is straight
Connect on the carry chain being mapped on fpga chip, but all have per the carry chain resource of money fpga chip
Limit.Therefore, the more arithmetic operator macroblock of carry chain, traditional Technology Mapping are used for some
Method is then existed because the excessive carry chain of production causes the actual capacity beyond fpga chip, so that
So that fpga chip cannot meet the situation of design requirement.
The content of the invention
It is an object of the present invention to the deficiency that the process mapping method for solving traditional fpga chip is present.
To achieve the above object, the invention provides a kind of carry chain Technology Mapping based on fpga chip
Method, the method is comprised the following steps：
Obtain whole arithmetic operator macroblocks；Consumption figures is carried out respectively for whole arithmetic operator macroblocks
Estimation, and according to the consumption figures of each arithmetic operator macroblock to whole arithmetic operator macroblocks
It is ranked up；Calculate available carry chain surplus on fpga chip；The maximum fortune that counts of estimation consumption figures
Calculate the carry chain usage amount of macroblock；By available carry chain surplus on fpga chip and the consumption figures
The carry chain usage amount of maximum arithmetic operator macroblock is compared, if consumption figures is maximum counted
The carry chain usage amount of computing macroblock then disappears less than available carry chain surplus on the fpga chip
The maximum arithmetic operator macroblock of consumption value is mapped using the mode of carry chain.
Preferably, if the carry chain usage amount of the maximum arithmetic operator macroblock of the consumption figures is more than
Available carry chain surplus on the fpga chip, the then maximum arithmetic operator macroblock use of consumption figures
Conventional combination logical mappings.
Preferably, on fpga chip is calculated after available carry chain surplus step, consumption figures is estimated
It is further comprising the steps of before the carry chain usage amount step of maximum arithmetic operator macroblock：To whole
Arithmetic operator macroblock is judged, if whole arithmetic operator macroblocks have all been mapped,
Terminate；If also unmapped arithmetic operator macroblock, in estimating unmapped computing macroblock
The carry chain usage amount of the maximum arithmetic operator macroblock of consumption figures.
Preferably, available carry chain surplus step includes on fpga chip is calculated:Calculate FPGA
The actual carry chain number of chip, as carry chain surplus.
Preferably, available carry chain surplus step includes on fpga chip is calculated:Calculate FPGA
The actual carry chain number of chip, takes its certain proportion as carry chain surplus.
Preferably, can be using the certain proportion of the actual carry chain number of fpga chip as more than carry chain
Amount is using the 80% of the actual carry chain number of fpga chip as carry chain surplus.
Preferably, available carry chain surplus step includes on fpga chip is calculated:Calculate FPGA
The actual carry chain number of chip, specifies any value therein as carry chain surplus.
The present invention can dynamically determine whether arithmetic operator macroblock carries out Technology Mapping using carry chain,
The design requirement of fpga chip is better met.
Brief description of the drawings
Fig. 1 is that a kind of carry chain process mapping method based on FPGA provided in an embodiment of the present invention is illustrated
Figure；
Fig. 2 is that another carry chain process mapping method based on FPGA provided in an embodiment of the present invention shows
It is intended to.
Specific embodiment
Below by drawings and Examples, technical scheme is described in further detail.
Fig. 1 is a kind of carry chain process mapping method based on fpga chip provided in an embodiment of the present invention
Schematic diagram.As shown in figure 1, the method comprising the steps of S101-S105：
Step S101, obtains whole arithmetic operator macroblocks, and arithmetic operator macroblock includes add operation
Macroblock, subtraction macroblock, comparison operation macroblock or multiplying macroblock.
Step S102 is directed to whole arithmetic operator macroblocks and carries out consumption figures estimation respectively, and according to every
The consumption figures of individual arithmetic operator macroblock is ranked up to whole arithmetic operator macroblocks.
Specifically, for obtain whole arithmetic operator macroblocks first carry out consumption figures calculating, to obtain
The consumption figures of each arithmetic operator macroblock；Again according to each arithmetic operator macroblock consumption figures it is big
It is small that arithmetic operator macroblock is ranked up (as shown in table 1).
Table 1
| Title | Consumption figures | Sequence |
| Add operation macroblock | 40 | 1 |
| Subtraction macroblock | 30 | 2 |
| Comparison operation macroblock | 20 | 3 |
| Multiplying macroblock | 10 | 4 |
Step S103, calculates available carry chain surplus on fpga chip
Specifically, available carry chain surplus on fpga chip is calculated, is calculating FPGA cores
On piece during available carry chain surplus, can be using the actual carry chain number of fpga chip as carry chain
Surplus；Or the actual carry chain number of fpga chip is calculated, then take its certain proportion (for example, 80%)
As carry chain surplus；Or the actual carry chain number of fpga chip is calculated, specify therein any
Value is used as carry chain surplus.
Step S104, the carry chain usage amount of the maximum arithmetic operator macroblock of estimation consumption figures；
Step S105, by available carry chain surplus on fpga chip and the maximum fortune that counts of consumption figures
The carry chain usage amount for calculating macroblock is compared, if the maximum arithmetic operator macroblock of consumption figures
Carry chain usage amount is not more than available carry chain surplus on fpga chip, then consumption figures is maximum counts
Computing macroblock is mapped using the mode of carry chain；Or, the maximum arithmetic operator of consumption figures is grand
More than available carry chain surplus on the fpga chip, then consumption figures is most for the carry chain usage amount of module
Big arithmetic operator macroblock is using conventional combination logical mappings (for example, display look-up table
(Look-Up-Table, referred to as LUT)).
Preferably, also step S106 is included (such as between above-mentioned steps S103 and above-mentioned steps S104
Shown in Fig. 2)：
In step S106, whole arithmetic operator macroblocks are judged, if whole arithmetic operators are grand
Module has all been mapped, then go to step S107, and execution terminates；If also unmapped calculation
Number computing macroblock, then estimate the grand mould of arithmetic operator of consumption figures maximum in unmapped computing macroblock
The carry chain usage amount of block.
It is described in detail below by way of a specific design implementation：
It is now assumed that certain design includes the add operation macroblock of 50 20,50 10 additions fortune
Calculate macroblock, and some combinational logics (about taking 1000 LUT4 resources).Chip uses HR3
Model, it includes 3000 resources of LUT4, wherein 1000 LUT4 include carry chain structure.
According to traditional process mapping method, 100 whole add operation macroblocks can all be mapped to
On carry chain, then 1500 carry chain resources are needed, its carry chain number far beyond chip HR3
Amount (HR3 model chips only have 1000 LUT4 to include carry chain structure).
However, the process mapping method for providing according to embodiments of the present invention only needs to take 1000 carries
Chain.Process is as follows：
Assuming that using carry chain occupancy as the valuation of consumption figures, then 20 add operation macroblocks disappear
Consumption value is that 20,10 consumption figures of add operation macroblock are 10.The addition of so 50 20
Computing macroblock can be mapped by the way of carry chain (to be taken 1000 LUT4 and 1000 to enter
Position chain), now the carry chain of chip HR3 has all been used, then the addition of 50 10 in addition
Computing macroblock then can be so final using combinational logic mapping (assuming that having used 700 LUT4)
2700 LUT4 and 1000 carry chains have been used, chip capacity requirement has been met.
The embodiment of the present invention can dynamically determine whether arithmetic operator macroblock carries out technique using carry chain
Mapping, has better met the design requirement of fpga chip.
Professional should further appreciate that, be described with reference to the embodiments described herein
The unit and algorithm steps of each example, can be come with electronic hardware, computer software or the combination of the two
Realize, in order to clearly demonstrate the interchangeability of hardware and software, in the above description according to function
Generally describe the composition and step of each example.These functions are come with hardware or software mode actually
Perform, depending on the application-specific and design constraint of technical scheme.Professional and technical personnel can be to every
Described function is realized in individual specific application using distinct methods, but it is this realize it is not considered that
It is beyond the scope of this invention.
Above-described specific embodiment, is carried out to the purpose of the present invention, technical scheme and beneficial effect
Further describe, should be understood that the foregoing is only specific embodiment of the invention and
, the protection domain being not intended to limit the present invention, it is all within the spirit and principles in the present invention, done
Any modification, equivalent substitution and improvements etc., should be included within the scope of the present invention.
Claims (8)
1. a kind of carry chain process mapping method based on fpga chip, it is characterised in that including with
Lower step：
Obtain whole arithmetic operator macroblocks；
Consumption figures estimation is carried out respectively for whole arithmetic operator macroblocks, and according to each calculation
The consumption figures of number computing macroblock is ranked up to whole arithmetic operator macroblocks；
Calculate available carry chain surplus on fpga chip；
The carry chain usage amount of the maximum arithmetic operator macroblock of estimation consumption figures；
By the arithmetic operator that available carry chain surplus on the fpga chip is maximum with the consumption figures
The carry chain usage amount of macroblock is compared, if the maximum arithmetic operator macroblock of the consumption figures
Carry chain usage amount be not more than available carry chain surplus on the fpga chip, then the consumption figures
Maximum arithmetic operator macroblock is mapped using the mode of carry chain.
2. method according to claim 1, it is characterised in that if the consumption figures is maximum
The carry chain usage amount of arithmetic operator macroblock is more than available carry chain surplus on the fpga chip,
Then the maximum arithmetic operator macroblock of the consumption figures uses conventional combination logical mappings.
3. method according to claim 1, it is characterised in that in the calculating fpga chip
After upper available carry chain surplus step, the carry of the maximum arithmetic operator macroblock of estimation consumption figures
It is further comprising the steps of before chain usage amount step：
Whole arithmetic operator macroblocks are judged, if whole arithmetic operator macroblocks
All mapped, then terminated；If also unmapped arithmetic operator macroblock, estimates not
The carry chain usage amount of the maximum arithmetic operator macroblock of consumption figures in the computing macroblock of mapping.
4. method according to claim 1, it is characterised in that on the calculating fpga chip
Available carry chain surplus step includes:
The actual carry chain number of fpga chip is calculated, as carry chain surplus.
5. method according to claim 1, it is characterised in that on the calculating fpga chip
Available carry chain surplus step includes:
The actual carry chain number of fpga chip is calculated, its certain proportion is taken as carry chain surplus.
6. method according to claim 5, it is characterised in that enter fpga chip is actual
The 80% of position chain number is used as carry chain surplus.
7. method according to claim 1, it is characterised in that on the calculating fpga chip
Available carry chain surplus step includes:
The actual carry chain number of fpga chip is calculated, any value therein is specified as more than carry chain
Amount.
8. method according to claim 1, it is characterised in that the arithmetic operator macroblock bag
Include add operation macroblock, subtraction macroblock, comparison operation macroblock and multiplying macroblock
In one or more.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511018760.6A CN106934079B (en) | 2015-12-29 | 2015-12-29 | Carry chain process mapping method based on FPGA chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201511018760.6A CN106934079B (en) | 2015-12-29 | 2015-12-29 | Carry chain process mapping method based on FPGA chip |
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| CN106934079B CN106934079B (en) | 2020-04-07 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103259523A (en) * | 2012-02-17 | 2013-08-21 | 京微雅格（北京）科技有限公司 | Optimization method of addition chain and integrated circuit adopting addition chain |
| CN103259530A (en) * | 2012-02-17 | 2013-08-21 | 京微雅格（北京）科技有限公司 | Method for restraining carry chain |
| US8793629B1 (en) * | 2007-11-23 | 2014-07-29 | Altera Corporation | Method and apparatus for implementing carry chains on FPGA devices |
-
2015
- 2015-12-29 CN CN201511018760.6A patent/CN106934079B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8793629B1 (en) * | 2007-11-23 | 2014-07-29 | Altera Corporation | Method and apparatus for implementing carry chains on FPGA devices |
| CN103259523A (en) * | 2012-02-17 | 2013-08-21 | 京微雅格（北京）科技有限公司 | Optimization method of addition chain and integrated circuit adopting addition chain |
| CN103259530A (en) * | 2012-02-17 | 2013-08-21 | 京微雅格（北京）科技有限公司 | Method for restraining carry chain |
Non-Patent Citations (2)
| Title |
|---|
| F.CAPONIO等: "A high-precision wave union TDC implementation in FPGA", 《2013 NSS/MIC》 * |
| 张惠国等: "FPGA快速进位链设计", 《常熟理工学院学报(自然科学版)》 * |
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