CN106898644A - High-breakdown-voltage field-effect transistor and preparation method thereof - Google Patents

Abstract

The invention discloses a kind of high-breakdown-voltage field-effect transistor and preparation method thereof, it includes substrate (1), Ga from bottom to top₂O₃Epitaxial layer (2) and low-doped n-type Ga₂O₃Film (3), film is provided with doped n-type Si ion implantation area (4) and insulation gate medium (7), ion implanted region is provided with source electrode (5) and drain electrode (6), insulation gate medium is provided with the thick organic insulation media (8) of 300~500nm, organic insulation medium is by P (VDF TrFE), Ag nano particles doping P (VDF TrFE), ZnS nano particles doping P (VDF TrFE) and CCTO nano particles doping P (VDF TrFE) are constituted, and it is provided with grid field plate (9) that length is 1~3 μm, gate electrode is provided with the grid field plate.Breakdown voltage of the present invention is high, is used as power device and High-tension Switch Devices.

Description

High breakdown voltage field effect transistor and manufacturing method thereof

technical field

The invention belongs to semiconductor new material devices, in particular to a field effect transistor, which can be used as a power device and a high-voltage switch device.

Background technique

With the continuous reduction of the size of MOSFET devices, traditional silicon MOS devices have encountered many challenges, among which the breakdown voltage is difficult to meet the increasing demand, which has become one of the key factors affecting the further improvement of device performance. Compared with the third-generation semiconductor materials represented by SiC and GaN, Ga ₂ O ₃ has a wider forbidden band width, and the breakdown field strength is equivalent to more than 20 times that of Si, and more than twice that of SiC and GaN. As mentioned above, when manufacturing metal-oxide-semiconductor field effect transistor MOSFET power devices with the same withstand voltage, the on-resistance of the device can be reduced to 1/10 of SiC, 1/3 of GaN, and 1/3 of Ga ₂ O ₃ material. The Liga figure of merit is 18 times that of SiC and more than 4 times that of GaN materials, so Ga ₂ O ₃ is a wide bandgap semiconductor material with excellent performance suitable for the preparation of power devices and high-voltage switching devices.

In order to improve the performance of Ga ₂ O ₃ metal-oxide-semiconductor field-effect transistor MOSFET power devices, it is necessary to improve the breakdown voltage of the device in the depletion state, and Ga ₂ O ₃ metal-oxide-semiconductor field-effect transistor MOSFET The breakdown of the device mainly occurs at the gate-to-drain end. Therefore, to increase the breakdown voltage of the device, the electric field in the gate-drain region must be redistributed, especially to reduce the electric field at the gate-to-drain end. The method increases the breakdown voltage of the device from 415V to 755V, while the switching ratio of the device is still greater than 10 ⁹ .

The existing metal-oxide-semiconductor field effect transistor MOSFET power device is shown in Fig. 1 .

In this device, an oxide layer and a metal gate are made on a semiconductor substrate, implanted on both sides to form a channel, and SiO ₂ is deposited on both sides of the source and drain to form a metal-oxide-semiconductor field effect transistor MOSFET device. The disadvantage of this metal-oxide-semiconductor field effect transistor device is that the withstand voltage is not high, usually lower than 200V. Electric field, so that the electrons in the electric field are continuously accelerated to obtain energy. Because electrons will collide with the crystal lattice when they move in the semiconductor, when the energy obtained by the electrons is large enough, it will cause damage to the crystal lattice, form a large current, and break down the device.

Contents of the invention

The object of the present invention is to address the shortcomings of the above-mentioned prior art, and propose a high breakdown voltage field effect transistor and its manufacturing method, so as to reduce the electric field at the drain end and increase the breakdown voltage of the device.

In order to achieve the above object, the high breakdown voltage field effect transistor of the present invention comprises a substrate, a Ga ₂ O ₃ epitaxial layer and a low-doped n-type Ga ₂ O ₃ film from bottom to top, and a high-doped n-type Ga 2 O 3 film is provided on the film. Type silicon ion implantation area and insulating gate dielectric, respectively provided with source electrode and drain electrode on the ion implantation area, it is characterized in that:

The insulating gate dielectric is provided with an organic insulating medium with a thickness of 300nm to 500nm. The organic insulating medium is made of P (VDF-TrFE), Ag nanoparticles doped P (VDF-TrFE), ZnS nanoparticles doped P ( VDF-TrFE) and CCTO nanoparticles doped P (VDF-TrFE) film dielectric material;

A grid field plate with a length of 1 μm to 3 μm is arranged in the organic insulating medium, and a gate electrode is arranged on the grid field plate.

In order to achieve the above object, the method for making a high breakdown voltage field effect transistor of the present invention comprises the following steps:

1) Organically clean the sample with Ga ₂ O ₃ film epitaxially grown on the substrate, after cleaning with flowing deionized water, put it into the solution of HF:H ₂ O = 1:1 and etch for 30s~60s, Then wash with flowing deionized water, and dry with high-purity nitrogen;

2) Put the cleaned sample into PECVD equipment to deposit a _SiO2 mask with a thickness of 50nm to 70nm;

3) Perform photolithography on the sample that has completed SiO ₂ mask deposition to form an ion implantation area, and perform Si ion implantation. After implantation, the sample is subjected to thermal annealing at 1000°C for 30 minutes in a nitrogen atmosphere to activate the implanted silicon ions ;

4) Put the sample that has been activated by silicon ion implantation into the plasma reaction chamber, feed in oxygen with a flow rate of 200 sccm, set the pressure of the reaction chamber to 30Pa-40Pa, and the radio frequency power to 300W, and etch the sample for 10 minutes to remove Photoresist mask on the sample surface;

5) Put the sample whose surface mask has been removed into the BOE solution, etch for 5 minutes, and remove the _SiO2 mask on the surface;

6) Perform photolithography on the corroded sample to form the source electrode and drain electrode area, then put it into the electron beam evaporation table to evaporate metal Ti/Au, and perform metal stripping and rapid thermal annealing in sequence to form an ohmic contact electrode;

7) Clean the sample forming the ohmic contact electrode, and then put it into the atomic layer deposition equipment. Under the process conditions of the temperature of 300 ° C, the pressure of 2000 Pa, the flow rate of H ₂ O and TMAl are both 150 sccm, the deposition thickness is 5nm-20nm Al ₂ O ₃ insulating gate dielectric;

8) Perform photolithography on the sample that has completed the Al ₂ O ₃ insulating gate dielectric deposition to form the deposition area of the organic insulating dielectric P (VDF-TrFE), and then put it into the BOE solution to etch for 10s to remove the deposition area of Al ₂ O ₃ ;

9) Spin-coat the prepared P(VDF-TrFE) solution onto the sample at a speed of 3000rpm, and then put it in an oven to bake the sample at 130°C for 24 hours;

10) Perform photolithography on the sample prepared by the P(VDF-TrFE) ferrodielectric to form the gate electrode area and the grid field plate area, and then put it into the electron beam evaporation table to evaporate the thickness of Ni to 20nm-50nm, and the thickness of metal Au to be 100nm ~ 200nm, Ni/Au metal, and then lift off to complete the fabrication of the entire device.

The present invention has the following advantages:

1. The present invention uses an organic ferrodielectric to replace the medium below the field plate, which not only makes the field plate have the effect of adjusting the electric field at the drain end of the gate, but also when the gate-drain reverse bias and the negative bias voltage applied by the gate electrode continue to increase At the same time, a dipole with a positive charge on the upper surface and a negative charge on the lower surface is formed inside the organic ferrodielectric, thereby repelling the electrons in the semiconductor material, reducing the carrier concentration at the drain end of the gate, and the electric field also decreases with The reduction further increases the breakdown voltage of the device;

2. The present invention can obtain the organic ferrodielectric only by spin coating and baking, and the preparation process is simple compared with the prior art.

Description of drawings

Fig. 1 is the structural schematic diagram of existing MOSFET device;

Fig. 2 is a device top view of the present invention;

Fig. 3 is the sectional structure schematic diagram of the present invention;

Fig. 4 is a schematic diagram of the process flow of the device of the present invention.

Specific implementation

The present invention will be described in detail below in conjunction with the accompanying drawings. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

2 and 3, the device of the present invention includes a substrate 1, a Ga ₂ O ₃ epitaxial layer 2, a low-doped n-type Ga ₂ O ₃ thin film 3, an ion implantation region 4, a source electrode 5, a drain electrode 6, an insulated gate Medium 7, organic insulating medium 8, gate electrode and gate field plate 9; wherein substrate 1, Ga ₂ O ₃ epitaxial layer 2 and low-doped n-type Ga ₂ O ₃ thin film 3 are arranged from bottom to top, and ion implantation region 4 and the insulating gate dielectric 7 are located on the low-doped n-type Ga ₂ O ₃ film 3, the source electrode 5 and the drain electrode 6 are located on the ion implantation region 4, the organic insulating medium 8 is located on the insulating gate dielectric 7, the gate electrode and the gate field plate 9 is located on the organic insulating medium. in:

The organic insulating medium 8 is composed of P (VDF-TrFE), Ag nanoparticles doped P (VDF-TrFE), ZnS nanoparticles doped P (VDF-TrFE) and CCTO nanoparticles doped P (VDF-TrFE). Thin film dielectric material, the thickness of which is 300nm~500nm;

The length of the grid field plate 9 is 1 μm to 3 μm;

The substrate 1 is made of sapphire or MgO or MgAl ₂ O ₄ or Ga ₂ O ₃ ;

The Ga ₂ O ₃ epitaxial layer 2 has an electron concentration of 10 ¹⁴ cm ^-3 to 10 ¹⁶ cm ^-3 and a thickness greater than 1 μm;

The carrier concentration of the low-doped n-type Ga ₂ O ₃ thin film 3 is 10 ¹⁷ cm ^-3 to 10 ¹⁸ cm ^-3 , and the thickness is greater than 100 nm;

The elements implanted in the ion implantation area 4 are one or more of Si, Ge or Sn, and the implantation concentration is greater than 2×10 ¹⁹ cm ^-3 ;

The insulating gate dielectric 7 includes one or more of Si ₃ N ₄ , Al ₂ O ₃ , HfO ₂ and HfSiO, and its thickness is 20nm˜30nm.

With reference to Fig. 4, the present invention makes high breakdown voltage field-effect transistor method and provides following three kinds of embodiments:

In Example 1, the substrate is sapphire, implanted with Si ions, and the insulating gate dielectric is Si ₃ N ₄ high breakdown voltage field effect transistor.

Step 1: Wash the sample, as shown in Figure 4(a).

First organically clean the sample with Ga ₂ O ₃ epitaxially grown on the substrate, wash it with flowing deionized water, and put it into a solution of HF:H ₂ O = 1:1 for etching for 60 seconds;

Then rinse with flowing deionized water and blow dry with high-purity nitrogen.

Step 2: Deposit SiO ₂ mask, as shown in Figure 4(b).

Put the cleaned sample into the PECVD equipment, set the reaction chamber pressure to 2Pa, and the radio frequency power to 40W. At the same time, feed _SiH4 with a flow rate of 40sccm and _N2O with a flow rate of 10sccm. _On the n-type _Ga2O3 film Deposit a _SiO2 mask with a thickness of 50 nm.

Step 3: Fabricate the ion implantation area, as shown in Fig. 4(c).

3a) performing photolithography on the sample where the _SiO2 mask deposition is completed to form an ion implantation region;

3b) Put the photoetched sample into the ion implantation reaction chamber and perform Si ion implantation twice. The first implantation energy is 60keV, and the implantation dose is 3.2×10 ¹⁴ cm ^-2 ; The dose is 9.3×10 ¹³ cm ^-2 ;

3c) Put the Si ion-implanted sample into an annealing furnace, and perform thermal annealing at 1000° C. for 30 min in a nitrogen atmosphere to activate the implanted Si ions.

Step 4: Remove glue, as shown in Figure 4(d).

Put the sample that has been activated by Si ion implantation into the plasma reaction chamber, set the pressure of the reaction chamber to 40Pa, the radio frequency power to 300W, and the flow rate of 200sccm oxygen, and etch for 10min to remove the photoresist on the surface of the sample.

Step 5: Remove the SiO ₂ mask, as shown in Figure 4(e).

Put the sample after removing the photoresist into the BOE solution, etch for 5min, and remove the SiO ₂ mask on the surface.

Step 6: Fabricate source-drain electrodes, as shown in Figure 4(f).

Perform photolithography on the corroded sample to form the source electrode and drain electrode area, and then put it into the electron beam evaporation table to evaporate the metal Ti/Au and peel it off. The thickness of the metal Ti is 50nm, and the thickness of the metal Au is 200nm , and finally perform rapid thermal annealing at a temperature of 550°C for 60s in a nitrogen environment to form an ohmic contact electrode.

Step 7: Deposit insulating gate dielectric, as shown in FIG. 4(g).

After cleaning the sample forming the ohmic contact electrode, put it into the atomic layer deposition equipment, and deposit _20nm Thick Si ₃ N ₄ insulating gate dielectric.

Step 8: Etching the insulating gate dielectric, as shown in FIG. 4(h).

Perform photolithography on the sample that has completed the deposition of the Si ₃ N ₄ insulating gate dielectric to form the deposition area of the organic insulating dielectric P (VDF-TrFE), and then put it in the BOE solution for 10 seconds to etch away the area where the organic insulating layer will be made Si ₃ N ₄ .

Step 9: Fabricate an organic insulating layer, as shown in FIG. 4(i).

The prepared ferrodielectric P(VDF-TrFE) solution was spin-coated onto the sample at a speed of 3000 rpm, and baked in an oven at 130° C. for 24 hours.

Step 10: making grid field plates and grid electrodes, as shown in Fig. 4(j).

Photolithography is carried out on the sample prepared by the ferrodielectric P(VDF-TrFE) insulating layer to form the gate electrode area and the grid field plate area, and then put into the electron beam evaporation table to evaporate Ni/Au, wherein the thickness of metal Ni is 50nm, and the thickness of metal Ni is 50nm. The thickness of the Au is 200nm, and then it is lifted off to form a gate electrode and a gate field plate to complete the preparation of the whole device.

In Example 2, the substrate is Ga ₂ O ₃ , Sn ions are implanted, and the insulating gate dielectric is HfO ₂ .

Step 1: cleaning the sample, as shown in Figure 4(a).

This step is the same as Step 1 of Example 1.

Step 2: Deposit SiO ₂ mask, as shown in Figure 4(b).

This step is the same as Step 2 of Example 1.

Step 3: making an ion implantation area, as shown in FIG. 4(c).

3.1) Perform photolithography on the sample that has completed the _SiO2 mask deposition to form an ion implantation region;

3.2) Put the photoetched sample into the ion implantation reaction chamber to perform Sn ion implantation twice. The first implantation energy is 60keV, and the implantation dose is 3.2×10 ¹⁴ cm ^-2 ; The dose is 9.3×10 ¹³ cm ^-2 ;

3.3) Put the sample implanted with Sn ions into an annealing furnace, and perform thermal annealing at 1000° C. for 30 min in a nitrogen atmosphere to activate the implanted Sn ions.

Step 4: Remove glue, as shown in Figure 4(d).

This step is the same as Step 4 of Example 1.

Step five: remove the SiO ₂ mask, as shown in Figure 4(e).

This step is the same as Step 5 of Example 1.

Step 6: Make source-drain electrodes, as shown in FIG. 4(f).

Perform photolithography on the corroded sample to form the source electrode and drain electrode area, put it into the electron beam evaporation table to evaporate the metal Ti/Au and lift it off. The thickness of the metal Ti is 20nm, and the thickness of the metal Au is 100nm. Perform rapid thermal annealing at 550°C for 60s in the environment to form ohmic contact electrodes.

Step 7: Deposit insulating gate dielectric, as shown in FIG. 4(g).

After cleaning the sample forming the ohmic contact electrode, put it into the atomic layer deposition equipment, and deposit _20nm thick HfO ₂ insulating gate dielectric.

Step 8: Etching the insulating gate dielectric, as shown in FIG. 4(h).

Perform photolithography on the sample that has completed the deposition of the HfO ₂ insulating gate dielectric to form the deposition area of the organic insulating dielectric P (VDF-TrFE), and then put it in the BOE solution for 10 seconds to etch away the HfO in the area where the organic insulating layer will be made ₂ .

Step 9: Fabricate an organic insulating layer, as shown in FIG. 4(i).

This step is the same as Step 9 of Example 1.

Step 10: Fabricate grid field plates and gate electrodes, as shown in FIG. 4(j).

Photolithography is carried out on the sample prepared by the ferrodielectric P(VDF-TrFE) insulating layer to form the gate electrode area and the grid field plate area, and then put into the electron beam evaporation table to evaporate Ni/Au, wherein the thickness of metal Ni is 20nm, and the metal The thickness of the Au is 100nm, and then it is lifted off to form a gate electrode and a gate field plate to complete the preparation of the whole device.

In Example 3, the substrate is MgAl ₂ O ₄ , Ge ions are implanted, and the insulating gate dielectric is Al ₂ O ₃ high breakdown voltage field effect transistor.

Step A: wash the sample, as shown in Figure 4(a).

This step is the same as Step 1 of Example 1.

Step B: Deposit SiO ₂ mask, as shown in Figure 4(b).

This step is the same as Step 2 of Example 1.

Step C: making an ion implantation region, as shown in FIG. 4(c).

C1) carry out photolithography to the sample that finishes _SiO2 mask deposition, form ion implantation area;

C2) Put the photoetched sample into the ion implantation reaction chamber for two Ge ion implantations, the first implantation energy is 60keV, and the implantation dose is 3.2×10 ¹⁴ cm ^-2 ; the second implantation energy is 30keV, and the implantation The dose is 9.3×10 ¹³ cm ^-2 ;

C3) Put the Ge ion-implanted sample into an annealing furnace, and perform thermal annealing at 1000° C. for 30 min in a nitrogen atmosphere to activate the implanted Ge ions.

Step D: Degumming, as shown in Figure 4(d).

This step is the same as Step 4 of Example 1.

Step E: Remove the SiO ₂ mask, as shown in Figure 4(e).

This step is the same as Step 5 of Example 1.

Step F: making source-drain electrodes, as shown in FIG. 4(f).

Perform photolithography on the corroded sample to form the source electrode and drain electrode area, and then put it into the electron beam evaporation table to evaporate the metal Ti/Au and peel it off. The thickness of the metal Ti is 40nm, and the thickness of the metal Au is 150nm , and finally perform rapid thermal annealing at a temperature of 550°C for 60s in a nitrogen environment to form an ohmic contact electrode.

Step G: Depositing an insulating gate dielectric, as shown in FIG. 4(g).

After cleaning the sample forming the ohmic contact electrode, put it into the atomic layer deposition equipment, and deposit _20nm thick Al ₂ O ₃ insulating gate dielectric.

Step H: Etching the insulating gate dielectric, as shown in FIG. 4(h).

Perform photolithography on the sample that has completed the Al ₂ O ₃ insulating gate dielectric deposition to form the deposition area of the organic insulating dielectric P (VDF-TrFE), and then put it in the BOE solution for 10 seconds to etch away the area where the organic insulating layer will be made Al ₂ O ₃ .

Step I: Fabricate an organic insulating layer, as shown in FIG. 4(i).

This step is the same as Step 9 of Example 1.

Step J: Fabricate a gate field plate and a gate electrode, as shown in FIG. 4(j).

Photolithography is carried out on the sample prepared by the ferrodielectric P(VDF-TrFE) insulating layer to form the gate electrode area and the grid field plate area, and then put into the electron beam evaporation table to evaporate Ni/Au, wherein the thickness of metal Ni is 40nm, and the metal The thickness of the Au is 150nm, and then it is lifted off to form a gate electrode and a gate field plate to complete the preparation of the whole device.

The preparation method of a high breakdown voltage field effect transistor proposed by the present invention has been described in detail above through preferred examples. Those skilled in the art should understand that the above description is only a preferred example of the present invention without departing from the essence of the present invention. Within the scope of the present invention, certain denaturation or modification can be made to the device structure of the present invention, for example, the source and drain can also adopt a raised or recessed source and drain structure, or other new structures such as double gate, FinFET, Ω gate, triple gate or surrounding gate; The preparation method is not limited to the content disclosed in the examples, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

1. A high breakdown voltage field effect transistor, comprising a substrate (1), a Ga ₂ O ₃ epitaxial layer (2) and a low-doped n-type Ga ₂ O ₃ film (3) from bottom to top. There is a highly doped n-type ion implantation region (4) and an insulating gate dielectric (7), and a source electrode (5) and a drain electrode (6) are respectively arranged on the ion implantation region, and is characterized in that: The insulating gate dielectric (7) is provided with an organic insulating medium (8) with a thickness of 300nm to 500nm, and the organic insulating medium (8) is made of P(VDF-TrFE), Ag nanoparticles doped P(VDF-TrFE ), ZnS nanoparticle-doped P(VDF-TrFE) and CCTO nanoparticle-doped P(VDF-TrFE) film dielectric materials; A grid field plate (9) with a length of 1 μm to 3 μm is arranged in the organic insulating medium (8), and a gate electrode is arranged on the grid field plate. 2. The transistor according to claim 1, characterized in that: the material of the substrate (1) is sapphire or MgO or MgAl ₂ O ₄ or Ga ₂ O ₃ . 3. The transistor according to claim 1, characterized in that the Ga ₂ O ₃ epitaxial layer (2) has an electron concentration of 10 ¹⁴ cm ^-3 to 10 ¹⁶ cm ^-3 and a thickness greater than 1 μm. 4. The transistor according to claim 1, characterized in that the low-doped n-type Ga ₂ O ₃ thin film (3) has a carrier concentration of 10 ¹⁷ cm ^-3 to 10 ¹⁸ cm ^-3 and a thickness greater than 100 nm. 5. The transistor according to claim 1, characterized in that the elements implanted in the ion implantation region (4) are one or more of Si, Ge or Sn, and the implantation concentration is greater than 2×10 ¹⁹ cm ^-3 . 6. The transistor according to claim 1, characterized in that: the insulating gate dielectric (7) includes one or more of Si ₃ N ₄ , Al ₂ O ₃ , HfO ₂ and HfSiO, and its thickness is 20 nm to 30nm. 7. A method for manufacturing a high breakdown voltage field effect transistor, comprising the steps of: 1) Organically clean the sample with Ga ₂ O ₃ epitaxially grown on the substrate. After cleaning with flowing deionized water, put it into the solution of HF:H ₂ O = 1:1 to etch for 30s~60s, and then Rinse with flowing deionized water and blow dry with high-purity nitrogen; 2) Put the cleaned sample into PECVD equipment to deposit a _SiO2 mask with a thickness of 50nm to 70nm; 3) Perform photolithography on the sample that has completed SiO ₂ mask deposition to form an ion implantation area, and perform Si ion implantation. After implantation, the sample is subjected to thermal annealing at 1000°C for 30 minutes in a nitrogen atmosphere to activate the implanted silicon ions ; 4) Put the sample that has been activated by Si ion implantation into the plasma reaction chamber, feed in oxygen with a flow rate of 200 sccm, set the pressure of the reaction chamber to 30Pa-40Pa, and the radio frequency power to 300W, and etch the sample for 10min to remove Photoresist mask on the sample surface; 5) Put the sample whose surface mask has been removed into the BOE solution, etch for 5 minutes, and remove the _SiO2 mask on the surface; 6) Perform photolithography on the corroded sample to form the source electrode and drain electrode area, then put it into the electron beam evaporation table to evaporate metal Ti/Au, and perform metal stripping and rapid thermal annealing accordingly to form an ohmic contact electrode; 7) Clean the sample forming the ohmic contact electrode, and then put it into the atomic layer deposition equipment. Under the process conditions of the temperature of 300 ° C, the pressure of 2000 Pa, the flow rate of H ₂ O and TMAl are both 150 sccm, the deposition thickness is 5nm-20nm Al ₂ O ₃ insulating gate dielectric; 8) Perform photolithography on the sample that has completed the Al ₂ O ₃ insulating gate dielectric deposition to form the deposition area of the organic insulating dielectric P (VDF-TrFE), and then put it into the BOE solution to etch for 10s to remove the deposition area of Al ₂ O ₃ ; 9) Spin-coat the prepared P(VDF-TrFE) solution onto the sample at a speed of 3000rpm, and then put it in an oven to bake the sample at 130°C for 24 hours; 10) Perform photolithography on the sample prepared by the P(VDF-TrFE) ferrodielectric to form the gate electrode area and the grid field plate area, and then put it into the electron beam evaporation table to evaporate the thickness of Ni to 20nm-50nm, and the thickness of metal Au to be 100nm ~ 200nm, Ni/Au metal, and then lift off to complete the fabrication of the entire device. 8. The method according to claim 7, wherein step ₂ ) deposits SiO in the process conditions of the mask: the flow of SiH is ₄₀ sccm, the flow of N ₂ O is 10 sccm, and the pressure in the reaction chamber is 1Pa～2Pa, The RF power is 40W. 9. The method according to claim 7, wherein the Si ion implantation in step 3) adopts two implants, the first implantation energy and implantation dose are: 60keV, 3.2×10 ¹⁴ cm ^-2 ; the second implantation The energy and implant dose are: 30keV, 9.3×10 ¹³ cm ^-2 . 10. The method according to claim 7, wherein the thickness of metal Ti steamed in step 5) is 20nm to 50nm, and the thickness of metal Au is 100nm-200nm, then the sample is stripped of metal, and finally carried out in a nitrogen atmosphere environment for 550 ℃, 60s rapid thermal annealing.