CN106887465B - manufacturing method of trench type double-layer gate MOSFET - Google Patents

Abstract

The invention discloses a method for manufacturing a trench-type double-layer gate MOSFET. The steps include: 1) etching the trench, and growing a trench layer bonding film with an ONO structure; 2) growing source polysilicon, and performing reverse etching to the trench Upper surface; 3) Protect the lead-out end of the source polysilicon with photoresist, and reverse-etch the source polysilicon in the dense area; 4) Remove part of the outer silicon oxide film, photoresist, and groove in the trench layer contact film in sequence 5) growing the oxide layer between polysilicon; 6) removing the silicon nitride film and the inner silicon oxide film in the trench layer bonding film; 7) growing the gate oxide layer in sequence , gate polysilicon, and reverse etching the gate polysilicon to complete the fabrication of the device. The invention improves the morphology of the IPO layer at the lead-out end of the source polysilicon by optimizing the removal process of the trench layer film and reducing the oxidation amount of the source polysilicon, and solves the problem of gate polysilicon residue, thereby eliminating the gap between the gate and the source. Leakage hazard.

Description

Fabrication method of trench double-layer gate MOSFET

technical field

The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing a trench type double-layer gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

Background technique

The structure and appearance of the dense area (Cell area) and source polysilicon linkup area (Source poly linkup area) of the existing 100V trench type double-layer gate (Split Gate) MOSFET device are shown in Figure 1, and the lower layer of the trench is The source polysilicon, the upper layer is the gate polysilicon, the trench sidewall is the trench layer junction film (TCH liner), and the trench layer junction film is an ONO (silicon oxide film-silicon nitride film-silicon oxide film) structure, Between the gate polysilicon and the source polysilicon is an IPO layer (inter-polysilicon oxide, an oxide layer between polysilicons), and the IPO layer is formed by oxidizing the source polysilicon.

Due to the thickness requirements of the trench layer junction film in the conventional trench type double-layer gate MOSFET device structure That is, the oxidation thickness of the IPO layer is required to be thick enough, which leads to uncontrollable morphology of the source polysilicon, as shown in (b) of Figure 1, the top of the source polysilicon is relatively steep, and the curvature on both sides of the top of the IPO layer is relatively large. Large (the part circled by the dotted line in the figure), the source polysilicon terminal often has gate polysilicon residue, which causes leakage from the gate to the source, resulting in the hidden danger of current short circuit.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for manufacturing a trench-type double-layer gate MOSFET, which can improve the morphology of the IPO layer at the lead-out end of the source polysilicon, and prevent the gate polysilicon from remaining at the lead-out end of the source polysilicon. In order to solve the above-mentioned technical problems, the fabrication method of the trench type double-layer gate MOSFET of the present invention comprises the following steps:

1) Etching a groove on the silicon substrate, and growing a trench layer bonding film in the groove; the film layer structure of the trench layer bonding film is silicon oxide-silicon nitride-silicon oxide;

2) growing source polysilicon, and back etching the source polysilicon to the upper surface of the trench;

3) Protect the source polysilicon terminal with photoresist, and perform reverse etching on the source polysilicon in the dense area;

4) sequentially removing part of the outer silicon oxide film in the trench layer bonding film, the photoresist protecting the lead-out end of the source polysilicon, and the remaining outer layer silicon oxide film in the trench layer bonding film;

5) growing an oxide layer between polysilicons above the source polysilicon;

6) removing the silicon nitride film and the inner layer silicon oxide film in the trench layer bonding film;

7) Grow the gate oxide layer and gate polysilicon in sequence, and perform reverse etching on the gate polysilicon; follow up with the traditional process to complete the fabrication of the trench type double-layer gate MOSFET.

Step 1), in the trench layer bonding film, the thickness of the inner silicon oxide film is The thickness of the silicon nitride film in the middle layer is The thickness of the outer silicon oxide film is

In step 2), the etching end point can be detected by wavelength.

In step 3), the etching amount of the reverse etching can be controlled by controlling the etching time. Preferably, after the reverse etching is completed, the height of the remaining source polysilicon is 1 micron lower than the height of the single crystal silicon substrate on the upper surface of the trench.

Step 4), the thickness of the part of the outer silicon oxide film is

Step 5), a thermal oxidation method can be used. The thickness of the oxide layer between the polysilicon is

Step 7), the thickness of gate oxide layer is Etch back to the single crystal silicon surface.

The invention improves the manufacturing process flow of the trench-type double-layer gate MOSFET, optimizes the removal process of the trench layer contact film, and reduces the oxidation amount of the source polysilicon, improves the morphology of the IPO layer at the lead-out end of the source polysilicon, and solves the problem of gate The problem of extremely polysilicon residue is avoided, thereby avoiding the leakage from the gate to the source, and eliminating the hidden danger of the current short circuit of the MOSFET device.

Description of drawings

Fig. 1 is a scanning electron microscope diagram of the structure and morphology of the dense region and the source polysilicon lead-out end of the existing trench-type double-layer gate MOSFET. Among them, (a) is the dense area, and (b) is the source polysilicon terminal.

FIG. 2 is a schematic diagram of the device structure obtained after step 3 of the embodiment of the present invention is completed.

Fig. 3 is a scanning electron microscope image of the device structure and morphology obtained after step 3 of the embodiment of the present invention is completed.

Fig. 4 is a scanning electron microscope image of the device structure and morphology obtained after step 7 of the embodiment of the present invention is completed. Among them, (a) is the dense area, and (b) is the source polysilicon terminal.

Fig. 5 is a scanning electron microscope image of the device structure and morphology obtained after step 11 of the embodiment of the present invention is completed. Among them, (a) is the dense area, and (b) is the source polysilicon terminal.

Fig. 6 is a scanning electron microscope image of the final structure and morphology of the trench type double-layer gate MOSFET device according to the embodiment of the present invention.

The reference signs in the figure are explained as follows

1: Source polysilicon

2: Gate polysilicon

3: Oxide layer between polysilicon (IPO)

4: Groove layer bonding film

5: Gate polysilicon residue

6: Gate oxide layer

7: Contact hole

Detailed ways

In order to have a more specific understanding of the technical content, features and effects of the present invention, the technical solutions of the present invention will be further described in detail in conjunction with the accompanying drawings and specific embodiments.

The manufacturing method of the trench type double-layer gate MOSFET of the present invention, its specific manufacturing process flow comprises the following steps:

In step 1, trenches are formed on the silicon substrate by etching.

Step 2, growing a trench layer film of ONO (silicon oxide-silicon nitride-silicon oxide) structure in the furnace tube in the trench. In this trench layer bonding film, the thickness of the inner silicon oxide film is The thickness of the silicon nitride film in the middle layer is The thickness of the outer silicon oxide film is

Step 3, grow the source polysilicon, and reverse etch (dry etching) the source polysilicon to the upper surface of the trench, and use the wavelength to detect the etching end point (EPD), as shown in Figs. 2 and 3 .

In step 4, the source polysilicon terminal is protected with photoresist, and the source polysilicon in the dense area is reverse-etched (dry etching), and the etching amount is controlled by controlling the etching time. In this embodiment, after the reverse etching is completed, the height of the remaining source polysilicon is 1 micron lower than the height of the single crystal silicon substrate on the upper surface of the trench.

Step 5, removing part of the outer layer oxide film in the trench layer junction film (that is, the layer of silicon oxide film away from the sidewall of the trench). The thickness of the outer oxide film removed in this step is about

Step 6, dry or wet removal of the photoresist protecting the lead-out end of the source polysilicon.

Step 7, wet etching to remove the remaining outer oxide film in the trench layer contact film. After this step is completed, the structure shown in FIG. 4 is obtained.

Step 8, forming a thickness above the source polysilicon by thermal oxidation interpolysilicon oxide (IPO).

Step 9, wet etching to remove the silicon nitride film and the inner layer silicon oxide film (ie the silicon oxide film on the trench wall) in the trench layer contact film.

Step 10, the growth thickness is gate oxide layer. The source polysilicon lead-out end Since the height of the source polysilicon and the IPO layer exceeds the depth of the trench, the gate oxide layer only grows on the single crystal silicon on the trench surface.

Step 11, grow gate polysilicon, and reverse etch to the surface of single crystal silicon (dry etching, automatically control the etching end point through End point). After this step is completed, the structure shown in FIG. 5 is obtained.

Comparing Fig. 5 with Fig. 1, it can be seen that the trench-type double-layer gate MOSFET manufactured by the present invention has a gentle top of the source polysilicon, better depth control, and no gate polysilicon remains at the lead-out end of the source polysilicon.

Subsequent processes such as etching of the contact hole are completed according to the traditional manufacturing process of MOSFET (including base implantation, source implantation, contact hole, metal connection layer, surface passivation layer, etc.), and finally the structure shown in Figure 6 is formed. .

Claims (9)

1. The manufacture method of trench type double-layer gate MOSFET is characterized in that, comprises the following steps: 1) Etching a groove on the silicon substrate, and growing a trench layer bonding film in the groove; the film layer structure of the trench layer bonding film is silicon oxide-silicon nitride-silicon oxide; 2) growing source polysilicon, and back etching the source polysilicon to the upper surface of the trench; 3) Protect the source polysilicon terminal with photoresist, and perform reverse etching on the source polysilicon in the dense area; 4) sequentially removing part of the outer silicon oxide film in the trench layer bonding film, the photoresist protecting the lead-out end of the source polysilicon, and the remaining outer layer silicon oxide film in the trench layer bonding film; 5) growing an oxide layer between polysilicons above the source polysilicon; 6) removing the silicon nitride film and the inner layer silicon oxide film in the trench layer bonding film; 7) Grow the gate oxide layer and gate polysilicon in sequence, and perform reverse etching on the gate polysilicon; follow up with the traditional process to complete the fabrication of the trench type double-layer gate MOSFET. 2. The method according to claim 1, characterized in that, in the step 1), in the trench layer bonding film, the thickness of the inner silicon oxide film is The thickness of the silicon nitride film in the middle layer is The thickness of the outer silicon oxide film is 3 . The method according to claim 1 , wherein in the step 2), the etching end point is detected by wavelength. 4 . 4. The method according to claim 1, characterized in that, in said step 3), after the reverse etching is completed, the height of the remaining source polysilicon is 1 micron lower than the height of the single crystal silicon substrate on the upper surface of the trench . 5. The method according to claim 1, characterized in that, in the step 4), the thickness of the part of the outer silicon oxide film is 6. The method according to claim 1, characterized in that, in the step 5), a thermal oxidation method is used. 7. The method according to claim 1, characterized in that, in the step 5), the thickness of the oxide layer between the polysilicon is 8. The method according to claim 1, characterized in that, in the step 7), the gate oxide layer has a thickness of 9. The method according to claim 1, characterized in that, in the step 7), reverse etching is carried out to the surface of the single crystal silicon substrate.