CN106877641B - A kind of soft starting circuit for DC-DC converter - Google Patents

Abstract

A kind of soft starting circuit for DC-DC converter belongs to electronic circuit technology field.Ramp voltage V is utilized in the soft start stage_{SS_OUT}With the partial pressure V of output voltage_FBIt compares, realizes output soft start, ramp voltage V_{SS_OUT}Risen first with higher slope k 1, to shorten the time of soft start foundation, when the first capacitance C1 both end voltages reach the threshold voltage of the first NMOS tube M1, the ramp voltage Vss_out rates of rise are reduced to k2, prevent inductive current from overshooting；After soft start, i.e. ramp voltage V_{SS_OUT}More than reference voltage V_REF, additional charging paths are opened, by the grid voltage V of the 4th NMOS tube M4_SSIt is pulled to close to power supply potential, ramp voltage V rapidly_{SS_OUT}It exits, comparator positive input terminal input reference voltage V_REF.The present invention ensure that the slow rising of output in the soft start stage, and ramp voltage Vss_out has just begun to ramp up that slope is larger, shortens the time of soft start foundation, then the rate of rise becomes smaller, it is suppressed that the generation of surge current.

Description

A Soft Start Circuit for DC-DC Converter

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to a soft start circuit for a DC-DC converter.

Background technique

With the widespread application of handheld devices and portable electronic products, the demand for power management ICs continues to rise. DC-DC switching power supply is widely used due to the advantages of high conversion efficiency, large output current, small quiescent current, and wide output load range. The switching power supply works by converting the error signal into a duty cycle control signal to drive the switch. In the start-up phase, the error amplifier is in an unbalanced state, making the loop work at 100% duty cycle, so after the power transistor is turned on, a large surge current will be generated to charge the capacitor. It is possible to damage the switch tube and other components, resulting in abnormalities in the system circuit system. In addition, in practical applications, most of the power sources of portable electronic products are batteries. Due to problems such as internal resistance and heat generation, the batteries may be burned if a large current flows instantaneously. For this reason, a soft-start circuit came into being. Its design idea is to eliminate the inrush current and avoid the output voltage overshoot by limiting the duty cycle or limiting the switching current. The soft-start voltage in the traditional soft-start circuit maintains a constant slope when it rises.

For a BUCK circuit controlled by a constant on-time (Constant On-timer, COT), when the divided voltage V _FB of the output voltage V _OUT is less than the reference voltage V _REF , the output level of the PWM comparator triggers the upper transistor to turn on for a constant period of time. During this period, the divided voltage V _FB of the output voltage V _OUT rises with the output voltage V _OUT to be greater than the reference voltage V _REF , and the voltage value of V _{FB drops after} the upper transistor is turned off. Controls open the top tube. In the start-up phase, since the output voltage is much lower than the set value, V _FB is much lower than V _REF . At this time, the upper power transistor will always be turned on with the maximum duty cycle (limited by the minimum off-time of the system) until V _FB When V _REF is reached, a large surge current will be introduced into the output capacitor, which will cause a large overshoot in the output, which may damage the switch tube and other devices, and cause abnormalities in the system circuit system.

Contents of the invention

The purpose of the present invention is to use the bias current to charge the soft-start capacitors in series, that is, the first capacitor C1 and the second capacitor C2, to provide a stable ramp voltage V _{SS_OUT} to participate in and divide the output voltage during the soft-start phase of the system. Compared with V _FB , the rising slope of the slope voltage V _{SS_OUT} is relatively large at the beginning, which shortens the soft-start establishment time, and then the slope becomes smaller, so as to realize the slow rise of the output and avoid the inrush current.

Technical scheme of the present invention is:

A soft start circuit for a DC-DC converter, comprising a first capacitor C1, a second capacitor C2, a third capacitor C3, a transistor Q1, a first NMOS transistor M1, a second NMOS transistor M2, and a third NMOS transistor M3 , the fourth NMOS transistor M4, the first PMOS transistor M5, the first inverter D1, the second inverter D2, the comparator and the bias current I _B ;

The emitter of the triode Q1 is connected to the power supply voltage VDD after passing the bias current _IB , its collector is grounded to GND, and its base is connected to one end of the second capacitor C2, the gate of the fourth NMOS transistor M4, the third NMOS transistor M3 and the third NMOS transistor M3. A drain of the PMOS transistor M5;

The other end of the second capacitor C2 is connected to one end of the first capacitor C1, the gate and drain of the first NMOS transistor M1, the gates of the second NMOS transistor M2 and the third NMOS transistor M3, the first NMOS transistor M1 and the second The source of the NMOS transistor M2 and the other end of the first capacitor C1 are grounded to GND, and the drain of the second NMOS transistor M2 is connected to the source of the third NMOS transistor M3;

The drain of the fourth NMOS transistor M4 is connected to the power supply voltage VDD, and its source is grounded to GND after passing through the third capacitor C3; the positive input terminal of the comparator is connected to the source electrode of the fourth NMOS transistor M4, and its negative input terminal is connected to the reference voltage V _REF , the output terminal of the comparator outputs the control signal Ctrl after passing through the first inverter D1 and inputs it to the gate of the first PMOS transistor M5, and the source of the first PMOS transistor M5 is connected to the power supply voltage VDD; the second inverter D2 The input terminal is connected to the output terminal of the first inverter D1, and its output terminal outputs the soft start flag signal SS_Flag, which controls the soft start circuit to output the voltage to the positive input terminal of the PWM comparator during the soft start establishment process as the ramp voltage Vss_out, and establishes After completion, the voltage output to the positive input terminal of the PWM comparator switches to the reference voltage V _REF .

The beneficial effect of the present invention is that a soft start circuit suitable for DC-DC converters is provided, which ensures the slow rise of the output in the soft start stage, and the soft start voltage, that is, the slope voltage Vss_out, has a relatively large rising slope at the beginning, shortening the Soft-start establishment time; when the voltage across the first capacitor C1 reaches the threshold voltage of the first NMOS transistor M1, the first NMOS transistor M1, the second NMOS transistor M2 and the third NMOS transistor M3 will be turned on, and the rising slope becomes small, suppressing the occurrence of inrush current.

Description of drawings

Fig. 1 is a schematic diagram of the principle of the present invention;

FIG. 2 is a schematic diagram of a soft-start waveform for a DC-DC converter provided by the present invention;

Fig. 3 is a kind of structure diagram of the soft start circuit for DC-DC converter provided by the present invention;

FIG. 4 is a schematic diagram of a soft-start output waveform for a DC-DC converter provided by the present invention.

Detailed ways

In order to eliminate the inrush current in the start-up phase, the ramp voltage V _{SS_OUT} is used to compare with the divided voltage V _FB of the output voltage in the soft-start phase to realize the output soft-start. After the soft start is over (V _{SS_OUT} exceeds V _REF ), the extra charging branch is turned on, which quickly pulls the gate voltage V _SS of the fourth NMOS transistor M4 to close to the power supply potential, the slope voltage V _{SS_OUT} exits, and the positive input terminal of the comparator Input reference voltage V _REF . In the following, the present invention will be described in detail by taking a COT-controlled BUCK converter as an embodiment and in conjunction with the accompanying drawings.

The principle schematic diagram of the present invention is shown in Figure 1. At the beginning, the switch S is turned on, the charging current I ₂ =I _charge of the soft-start capacitor C _SS , and the slope voltage V _{SS_OUT rises} with a relatively high slope k1, so as to shorten the time for soft-start establishment . After a period of time, the switch S is closed. At this time, the charging current of the capacitor becomes I ₂ = I _charge - I ₁ , and the rising slope of the slope voltage Vss_out is reduced to k2 to prevent the inductor current from overshooting. After the soft start is completed, the slope voltage V _{SS_OUT} exits and the positive input of the PWM comparator switches to the reference voltage V _REF .

The schematic diagram of the soft start waveform of the present invention is shown in FIG. 2 . After the system establishes the bias at time t1, V _FB will quickly rise to a voltage of tens of millivolts; the ramp voltage Vss_out starts at time t2, and begins to rise with a larger slope to shorten the time for soft-start establishment; at time t3 Turn off the switch S in Figure 1, Where V _TH is the threshold voltage of the first NMOS transistor M1, that is, when the voltage across the first capacitor C1 reaches the threshold voltage of the first NMOS transistor M1, the switch S is turned off, and the slope voltage Vss_out starts to increase at a lower rate due to the reduction of the capacitor charging current. small ramp up to prevent inrush current. In the present invention, t3≤t4 is required, and t4 is the time point when V _FB and the slope voltage Vss_out are initially equal, otherwise, the inductor current overshoots due to the relatively large rising slope of the first stage of the slope voltage Vss_out.

The specific circuit structure diagram of the present invention is shown in Figure 3, including a first capacitor C1, a second capacitor C2, a third capacitor C3, a triode Q1, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, The fourth NMOS transistor M4, the first PMOS transistor M5, the first inverter D1, the second inverter D2, the comparator and the bias current I _B ; the emitter of the triode Q1 is connected to the power supply voltage after passing the bias current I _B VDD, its collector is grounded to GND, its base is connected to one end of the second capacitor C2, the gate of the fourth NMOS transistor M4, the third NMOS transistor M3 and the drain of the first PMOS transistor M5; the other end of the second capacitor C2 Connect one end of the first capacitor C1, the gate and drain of the first NMOS transistor M1, the gates of the second NMOS transistor M2 and the third NMOS transistor M3, the sources of the first NMOS transistor M1 and the second NMOS transistor M2, and The other end of the first capacitor C1 is grounded to GND, the drain of the second NMOS transistor M2 is connected to the source of the third NMOS transistor M3; the drain of the fourth NMOS transistor M4 is connected to the power supply voltage VDD, and its source passes through the third capacitor C3 Ground GND; the positive input terminal of the comparator is connected to the source of the fourth NMOS transistor M4, the negative input terminal is connected to the reference voltage V _REF , the output terminal of the comparator passes through the first inverter D1 and then outputs the control signal Ctrl and is input to the second inverter D1 The gate of a PMOS transistor M5, the source of the first PMOS transistor M5 is connected to the power supply voltage VDD; the input terminal of the second inverter D2 is connected to the output terminal of the first inverter D1, and its output terminal outputs the soft start flag signal SS_Flag , control the soft start circuit to output the voltage to the positive input terminal of the PWM comparator during the soft start establishment process as the slope voltage Vss_out, and switch the voltage output to the positive input terminal of the PWM comparator to the reference voltage V _REF after the establishment is completed.

Wherein I _B is a fixed bias current. In order to reduce the rising slope of the slope voltage Vss_out, the base current I _charge of the transistor Q1 is used here to charge the capacitor.

Among them, β refers to the amplification factor of the transistor Q1, and IB is the emitter current of the transistor Q1. When the system is just powered on, the slope voltage Vss_out is much lower than V _REF , the control signal Ctrl is at high level, the soft start flag signal _{SS_Flag} is at low level, and the first PMOS tube M5 is turned off. Capacitors C1 and C2 are charged to generate a slope voltage Vss_out with a rising slope of k1 (a gate-source voltage Vgs lower than Vss by a fourth NMOS transistor M4), so as to shorten the soft-start settling time, and obtain:

The voltage across the first capacitor C1

Among them, t indicates that from time t1 to t3, when V1 rises to the threshold voltage _VTH of the first NMOS transistor M1, the first NMOS transistor M1, the second NMOS transistor M2 and the third NMOS transistor M3 will be turned on, generating two currents I2 and I3, V1 will be clamped at a relatively stable voltage VA by the diode-connected first NMOS transistor M1, because the current of I2 is very small, VA≈VTH. Next, the current charging the second capacitor C2 is reduced to I _charge - I2 - I3, and the rising slope of the gate voltage Vss of the fourth NMOS transistor is reduced to generate a stable slope voltage V _{SS_OUT} with a slope of k2;

When the slope voltage Vss_out rises to exceed the reference voltage V _REF , the comparator is reversed, the control signal Ctrl is reversed from high level to low level, the first PMOS transistor M5 is turned on, and a large pull-up current is generated to turn the first PMOS transistor M5 on. The gate voltage Vss of the four NMOS transistors is raised to the power supply voltage VDD, and the soft start flag signal SS_Flag is turned from low level to high level at the same time, indicating that the soft start is completed.

The whole process of the soft start circuit can be shown in Figure 4. After the system is powered on, the bias is established at time t1, and the gate voltage V _SS of the fourth NMOS transistor starts to rise with a larger slope k1, because the slope voltage Vss_out is higher than the fourth The gate voltage Vss of the NMOS transistor is lower than the gate-source voltage Vgs of the fourth NMOS transistor, so the slope voltage Vss_out rises with a slope k1 at time t2. At time t3, since the first NMOS transistor M1, the second NMOS transistor M2, and the third NMOS transistor M3 are turned on to draw a part of the current, the gate voltage Vss and the slope voltage Vss_out of the fourth NMOS transistor start to rise with a small slope k2 . At time t4, when the slope voltage Vss_out rises to exceed the reference voltage V _REF , the control signal Ctrl turns from high to low, and the first PMOS transistor M5 is turned on to quickly pull the gate voltage Vss of the fourth NMOS transistor to the power supply voltage VDD, and soft start at the same time The flag signal SS_Flag turns from low to high, marking the end of the soft start process.

The beneficial effect of the present invention is to eliminate the surge current in the start-up stage of the switching power supply circuit, and use the slope voltage V _{SS_OUT} to compare with the divided voltage V _FB of the output voltage in the soft-start stage to realize the output soft-start. After the soft-start ends (V _{SS_OUT} exceeds V _REF ), an additional charging branch is turned on to quickly pull the ramp voltage V _{SS_OUT} close to the supply potential. In addition, since the rising slope of the slope voltage Vss_out is relatively large at the beginning, the time for establishing the soft start is shortened, and then the rising slope becomes smaller, which suppresses the occurrence of surge current.

Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (1)

1. a kind of soft starting circuit for DC-DC converter, which is characterized in that including the first capacitance (C1), the second capacitance (C2), third capacitance (C3), triode (Q1), the first NMOS tube (M1), the second NMOS tube (M2), third NMOS tube (M3), Four NMOS tubes (M4), the first PMOS tube (M5), the first phase inverter (D1), the second phase inverter (D2), comparator and bias current (I_B)；

The emitter of triode (Q1) passes through bias current (I_B) it is followed by supply voltage (VDD), grounded collector (GND), base Pole connects one end of the second capacitance (C2), the grid of the 4th NMOS tube (M4), third NMOS tube (M3) and the first PMOS tube (M5) Drain electrode；

The other end of second capacitance (C2) connects one end of the first capacitance (C1), the grid of the first NMOS tube (M1) and drain electrode, the The source electrode of the grid of two NMOS tubes (M2) and third NMOS tube (M3), the first NMOS tube (M1) and the second NMOS tube (M2) and The other end ground connection (GND) of one capacitance (C1), the drain electrode of the second NMOS tube (M2) connect the source electrode of third NMOS tube (M3)；

The drain electrode of 4th NMOS tube (M4) connects supply voltage (VDD), and source electrode is grounded (GND) afterwards by third capacitance (C3)；Than Compared with the source electrode that the positive input of device terminates the 4th NMOS tube (M4), negative input terminates reference voltage (V_REF), the output end of comparator Control signal (Ctrl) is exported afterwards by the first phase inverter (D1) and is input to the grid of the first PMOS tube (M5), the first PMOS tube (M5) source electrode connects supply voltage (VDD)；

The input terminal of second phase inverter (D2) connects the output end of the first phase inverter (D1), and output end exports soft start mark letter Number (SS_Flag).