CN106876445A - A kind of high-power planar grid D MOSFET structures design - Google Patents

Abstract

The present invention provides a high-power planar gate D-MOSFET structure design, the planar gate D-MOSFET is an N-MOS structure or a P-MOS structure, and the corner area of the P-well structure of the N-MOS structure is composed of sub-steps a ladder-like structure; the corner region of the N-well structure of the P-MOS structure is a ladder-like structure composed of sub-ladders. The stepped structure reduces the equivalent interface curvature of the P-well structure and the corner region of the N-well structure, thereby reducing the maximum electric field strength in this region, reducing the possibility of avalanche breakdown inside the D-MOSFET, and improving the D-MOSFET reliability and improve the overall availability of the D‑MOSFET.

Description

Structure design of a high-power planar gate D-MOSFET

technical field

The invention belongs to the technical field of high-power semiconductors, and in particular relates to a structure design for high-power planar gate D-MOSFETs made of wide-bandgap materials.

Background technique

New wide-bandgap semiconductor materials such as silicon carbide and gallium nitride can greatly improve the performance of semiconductor devices, but at the same time, they also bring many challenges in device design and process. Wide bandgap material MOSFET (such as silicon carbide MOSFET) is a high-performance high-power controllable switching power semiconductor device, which has small leakage current in the off state, low conduction loss in the on state, fast switching speed, high operating frequency, High maximum operating temperature and other advantages. The use of wide-bandgap material MOSFET can increase the switching frequency of the inverter, reduce the overall loss, and reduce the demand for energy storage components such as capacitors, achieving the advantages of reducing the cost of the inverter and improving performance.

At present, high-power MOSFETs with wide bandgap materials mainly have two gate-level structures: planar gate D-MOS structure of planar gate level, corresponding to D-MOSFET devices, and vertical gate level trench gate T-MOS structure, corresponding to T-MOSFET. Under the current technical conditions, the manufacturing process of the D-MOS structure is simpler and more mature than the manufacturing process of the T-MOS structure, the manufacturing cost is relatively lower, and the yield rate of the final device is higher.

The high-performance wide-bandgap material MOSFET will generate a high-intensity electric field in the high-voltage blocking state, and the strongest electric field is in the reverse-biased P-N junction interface region inside the device. MOSFET has N-MOS structure with N-type channel and P-MOS structure with P-type channel. For the N-MOS structure of the N-type channel, this interface is a reverse-biased N-drift region/P-well junction, and for the P-MOS structure of the P-type channel, this interface is a reverse-biased N- Well/P-drift region junction.

The commonly used high-power semiconductor is an N-MOS structure. Due to the limitation of the diffusion of dopant atoms in the wide bandgap material, the existing design and manufacturing process realizes that the corner region of the P-well structure has a large curvature when forming the P-well region. This large curvature corner will further increase the electric field strength in the P-well corner region when the D-MOSFET blocks high voltage, and the maximum electric field in the entire device will be generated in this region. The excessively high electric field strength inside the device makes the possibility of avalanche breakdown inside the device higher, which will have a negative impact on the reliability of the D-MOSFET.

The traditional solution is to reduce the distance between adjacent P-wells, but this solution will have a negative impact on the on-state performance of the D-MOSFET, which will increase the on-resistance of the D-MOSFET, increase heat generation and reduce reliability. If the same on-resistance needs to be achieved, the chip area of the D-MOSFET needs to be increased, and the chip cost of the same voltage and current level will increase. Similarly, such problems also exist for P-MOS.

Another theoretical solution is to reduce the depth (or thickness) of the P-well, but reducing the depth is not practical. The reason is that the depth of the P-well is limited by the N+ source region, and reducing the depth of the P-well will make it easier for the electrons in the N+ source region to diffuse to the depletion region in the high-voltage blocking state, increasing the possibility of punch-through breakdown and affecting the device. reliability has a fatal negative impact.

Contents of the invention

In order to solve the problem of reducing the maximum electric field intensity in the P-well or N-well corner region under the same blocking voltage without affecting the conduction performance of the D-MOSFET, the present invention provides a high-power planar gate D-MOSFET structure design .

In order to solve the above problems, the present invention adopts the following technical solutions:

A high-power planar gate D-MOSFET structure design, the planar gate D-MOSFET is an N-MOS structure or a P-MOS structure, and the corner area of the P-well structure of the N-MOS structure is a ladder-like structure composed of sub-steps Structure; the corner region of the N-well structure of the P-MOS structure is a ladder-like structure composed of sub-steps.

Preferably, the stepped structure includes at least 2 sub-steps.

Preferably, the corner curvatures of each sub-step are the same or different.

Preferably, the lowermost sub-step of the sub-steps has the smallest arc curvature.

Preferably, the outer contour shapes of the sub-steps are the same or different.

Preferably, the outer contour of the sub-step is arc, curve, broken line or any combination of these three types of shapes.

Preferably, the number k of the sub-steps needs to satisfy [0.5μm*(k-1)]<W _min ; the W _min is the total depth W _y of the P-well structure or the N-well structure and The smaller value of the total width W _x .

Preferably, the sub-step is a single sub-step with a depth and a width of 0.5 μm.

Preferably, the depth and/or width of each sub-step is different, the depth does not exceed W _y /k, and the width does not exceed W _x /k.

Preferably, the ladder-like structure is formed by performing ion implantation through at least two ion implantation windows formed by masks and/or protective layers, and the implantation energy of each ion implantation is different, and a larger ion implantation window is matched with a smaller energy ion implantation.

The beneficial effects of the present invention are: high-power planar gate D-MOSFET structure design, the planar gate D-MOSFET is an N-MOS structure or a P-MOS structure, and the corner area of the P-well structure of the N-MOS structure is Ladder structure; the corner area of the N-well structure of the P-MOS structure is a ladder structure. The stepped structure reduces the equivalent interface curvature of the corner region of the P-well structure and the N-well structure, thereby reducing the maximum electric field strength in this region, reducing the possibility of avalanche breakdown inside the D-MOSFET, and improving the D-MOSFET reliability and improve the overall availability of the D-MOSFET.

Further, the high-power planar gate D-MOSFET structure design adopted in the present invention does not need to reduce the distance between adjacent P-wells when reducing the electric field intensity in the corner area, and will not increase the conduction resistance of the adjacent regions of the P-well, and will not It has an adverse effect on the on-state performance of the D-MOSFET; it can further reduce the electronic path length of the P-well region in the on-state to reduce the on-resistance, and improve the available on-state current density and wave current density of the D-MOSFET at the same voltage level. inrush current performance and improve wafer utilization.

Description of drawings

FIG. 1 is a schematic structural diagram of a D-MOSFET in the prior art according to Embodiment 1 of the present invention.

Fig. 2 is a schematic diagram of the structure design of the high-power planar gate D-MOSFET according to Embodiment 1 of the present invention.

Fig. 3-1 is a schematic diagram of another high-power planar gate D-MOSFET structure design according to Embodiment 1 of the present invention.

Fig. 3-2 is a schematic diagram of another high-power planar gate D-MOSFET structure design in Embodiment 1 of the present invention.

FIG. 4 is a structural schematic diagram of the structural design of the high-power planar gate D-MOSFET according to Embodiment 2 of the present invention.

FIG. 5 is a structural schematic diagram of the structural design of the high-power planar gate D-MOSFET according to Embodiment 3 of the present invention.

FIG. 6-1 is a structural schematic diagram of a high-power planar gate D-MOSFET according to Embodiment 4 of the present invention.

FIG. 6-2 is a structural schematic diagram of yet another high-power planar gate D-MOSFET according to Embodiment 4 of the present invention.

Among them, 1-P-well, 2-P-well corner region, 3-N+ source region, 4-source level, 5-gate level, 6-insulation layer, 7-N-drift region, 8-drain level, 9- 1, 9-2, 9-3, 9-4, and 9-5 are all masks, and 10—the angle during ion implantation.

detailed description

The present invention will be described in detail below through specific embodiments in conjunction with the accompanying drawings, so as to better understand the present invention, but the following embodiments do not limit the scope of the present invention. In addition, it should be noted that the diagrams provided in the following embodiments are only schematically illustrating the basic concept of the present invention, and only the components related to the present invention are shown in the drawings rather than the number of components, Shape and size drawing, the shape, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the layout of the components may also be more complex.

Example 1

As shown in FIG. 1 , it is a D-MOSFET structure in the prior art. In this embodiment, the planar gate D-MOSFET shown in Figure 1 is an N-MOS structure, in which 1-P-well, 2-P-well corner region, 3-N+ source region, 4-source level, 5-gate level , 6-insulation layer, 7-N-drift region, 8-drain level. When the D-MOSFET device blocks high voltage, the P-N junction formed by the N-drift region/P-well shown in Figure 1 is reverse biased, and a very high intensity is generated near the N-drift region/P-well interface the electric field. This electric field increases in the area where the curvature of the P-N junction interface is large, and the maximum intensity electric field appears in the P-well corner region 2 of the N-drift region/P-well interface in the D-MOSFET.

In the widely used wide bandgap material D-MOSFET design at present, the P-well 1 region is implanted with ions through a single mask. Due to the limited diffusion rate of the dopant atoms used in the wide bandgap material, the finally formed P-well corner region 2 will have a local large curvature. When the D-MOSFET blocks the voltage, the large curvature corner area will form a very high-intensity electric field. This electric field is more likely to form an avalanche breakdown, especially under high temperature conditions, and has a negative impact on the reliability of the D-MOSFET.

As shown in FIG. 2, it is the structure design of the high-power planar gate D-MOSFET of this embodiment. The basic structure is the same N-MOS structure as that in Fig. 1, the difference is that the P-well corner region 2 is a ladder structure composed of three arcs. The core idea of the present invention is to complete the transformation of the P-well corner region 2 from the vertical direction to the horizontal direction by a multi-step structure, and the step-shaped P-well 1 is formed by ion implantation through multiple masks. The equivalent curvature of the stepped P-well 1 structure shown in Figure 2 is significantly reduced compared with the type of P-well 1 described in Figure 1, thereby greatly reducing the maximum electric field intensity of the P-well corner region 2, so that the reliability of the device can be improved. boost, especially in high-temperature operating environments.

In a modified embodiment of this embodiment, when the planar gate D-MOSFET has a P-MOS structure, the N-well corner region can also adopt the same stepped structure as above to replace the existing structure, which can also reduce the N-well under the same conditions. The curvature of the interface in the corner area of the well structure reduces the maximum electric field strength in this area, reduces the possibility of avalanche breakdown inside the D-MOSFET, improves the reliability of the D-MOSFET, and increases the overall usability of the D-MOSFET.

The invention reduces the electric field strength in the corner area of the P-well or N-well by using the ladder structure, thereby improving the reliability of the D-MOSFET and increasing the overall usability of the D-MOSFET.

The above structure does not need to reduce the distance between adjacent P-wells 1 when reducing the electric field intensity in the corner area, does not increase the on-resistance in the vicinity of P-well 1, and does not adversely affect the on-state performance of the D-MOSFET. .

At the same time, this structural design can further reduce the electronic path length in the on-state of the P-well 1 region compared with the traditional scheme, thereby reducing the on-resistance, and improving the available on-current density and surge current of the D-MOSFET at the same voltage level performance and improve wafer utilization.

As shown in Figure 3-1, the ion implantation to form the P-well is realized by three batches of implantation. Each batch of ion implantation is completed in accordance with the ion implantation window formed by adjusting the mask and/or protective layer. The adjustment of the mask and/or protective layer can be formed by both positive photoresist and reflective photoresist. Through different exposure and cleaning methods, the ion implantation window can be gradually increased by corroding the photoresist, or the ion implantation window can be gradually reduced by accumulating the photoresist.

Ion implantation needs to be carried out with different ion energies after each mask adjustment. A larger mask window cooperates with a lower energy ion implantation to reduce the ion implantation depth, and finally forms the desired ladder-shaped P-well. The corner area of the 3-step P-well structure composed of three arcs can be added with a mask in the order of 9-1, 9-2, 9-3, or use the reverse order, from 9-3, 9-2, 9 Order of -1 to remove the mask. Figure 3-1 shows a typical 3-step layout, using ion implantation windows of 3 different widths for 3 batches of ion implantation.

In other flexible embodiments of this embodiment, the number of times of mask adjustment and batch ion implantation, that is, the number k (natural number) of small sub-steps, has no fixed value, and can be adjusted according to the total depth W _y and total width of the P-well required by the device. W _x is adjusted, and k=1 is the current technical level. According to the wide bandgap material and corresponding process characteristics, a reasonable way to determine the number k (natural number) of small sub-steps is: set W _min = min(W _y , W _x ), the number k of small sub-steps needs to satisfy ( 0.5μm*k)≥W _min , and [0.5μm*(k-1)]<W _min ; the depth and width of a single small sub-step are both 0.5μm. Limited by the process and other conditions in the actual device manufacturing, k can only satisfy [0.5μm*(k-1)]<W _min ; at the same time, the shape of a single small sub-step can also be independent, with different depths and/or widths, and the depth should not exceed W _y /k, the width does not exceed W _x /k.

In other alternative embodiments of this embodiment, the small sub-step outer contour of the P corner region or the N-well corner region includes, but is not limited to, an arc, a curve, a broken line, or any combination of these three types of shapes. The depth and width of the sub-step are respectively the projection (depth) of the arc, curve, broken line or any combination of these three types of shapes in the direction perpendicular to the D-MOSFET insulating layer/oxide layer plane and in D -Projection (width) on the plane direction of the insulating layer/oxide layer of the MOSFET; if the sub-step is other irregular shapes, the projection of the step edge shape in the direction perpendicular to the plane of the insulating layer/oxide layer of the D-MOSFET is taken according to the specific situation is the depth, and the projection on the plane direction of the D-MOSFET insulating layer/oxide layer is the width. Other methods for calculating depth and width in the prior art are also included in the above-mentioned scope.

As shown in Figure 3-2, the P-well corner area in the N-MOS structure is a 5-step layout, and 9-1, 9-2, 9-3, 9-4, and 9-5 are all masks. The method and process are similar to the above-mentioned 3-step N-MOS structure, and the sub-step is a single sub-step with a depth and a width of 0.5 μm.

In other alternative embodiments of this embodiment, each small sub-step may use its own independent outer profile; the corner curvature of each sub-step may be the same or different; and the outer profile shapes of the sub-steps may be the same or different.

Example 2

As shown in Fig. 4, a structural diagram of a high-power planar gate D-MOSFET structure design. The corner area is a ladder structure composed of three arcs, but the angle 10 of each batch of ion implantation can be adjusted to produce small sub-steps with different corner curvatures. Each sub-step can use its own independent corner curvature. A small sub-step with a smaller curvature or a larger corner radius can be placed in the deepest part of the P-well as the first corner to further reduce the maximum electric field intensity at the P-well/N-drift region interface, as shown in the figure The radian radius of the bottom sub-step is 1.5 times that of the remaining two steps.

In a modified embodiment of this embodiment, the arc radius of the lowest sub-step may be any multiple of the remaining steps.

Example 3

As shown in Fig. 5, the structural diagram of the structural design of the high-power planar gate D-MOSFET. Small sub-steps with different spatial distribution can be produced by adjusting the basic energy of each ion implantation batch, the angle 10 during ion implantation, and the width of the ion implantation window of the corresponding mask, that is, each sub-step can use its own independent depth and width. Figure 2 shows the linear spatial distribution, and the aforementioned methods can produce nonlinear distributions, such as arc-shaped distributions. As shown in FIG. 5 , there is an incremental area generated by a circular arc distribution in the step of the corner area, and the hatched area is the incremental groove grid area formed after the convex circular arc distribution is formed. The curvature of the equivalent P-well/N-drift region interface can be reduced by adopting a circular arc or curved distribution, thereby reducing the maximum electric field intensity of the P-well/N-drift region interface.

Example 4

As shown in Figure 6-1, the structure design of the high-power planar gate D-MOSFET in which the P-well corner area in the N-MOS structure is a 2-step layout. There are two corner regions of the P-well. Compared with the corner of the P-well region composed of an arc in the prior art, the maximum electric field intensity of the corner region of the P-well can still be reduced and the safety can be improved.

As shown in Figure 6-2, the P-well corner region 2 in the N-MOS structure is a structural design of a high-power planar gate D-MOSFET with a stepped layout composed of three different shapes. The three steps are respectively broken lines and two Different curves, as shown in the figure, the arc-shaped dotted lines near the three small sub-steps represent the original arc-shaped sub-steps in Figure 2 to show the distinction.

In the modified embodiment of this embodiment, the stepped structure formed by other shapes in the high-power planar gate D-MOSFET belongs to the scope of protection of the present invention; similarly, the above-mentioned stepped structure is applicable to large-scale P-MOS structures. Power planar gate D-MOSFET.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art to which the present invention belongs, several equivalent substitutions or obvious modifications can be made without departing from the concept of the present invention, and those with the same performance or use should be deemed to belong to the protection scope of the present invention.

Claims (10)

1. A high-power planar gate D-MOSFET structure design, said planar gate D-MOSFET is N-MOS structure or P-MOS structure, it is characterized in that, the P-well structure corner region of said N-MOS structure is A ladder-shaped structure composed of sub-steps; the corner region of the N-well structure of the P-MOS structure is a ladder-shaped structure composed of sub-steps. 2. The high-power planar gate D-MOSFET structure design according to claim 1, characterized in that the ladder-like structure includes at least two sub-steps. 3. The high-power planar gate D-MOSFET structure design according to claim 1, wherein the corner curvatures of each sub-step are the same or different. 4. The high-power planar gate D-MOSFET structure design according to claim 1, wherein the sub-step at the bottom of the sub-steps has the smallest arc curvature. 5. The high-power planar gate D-MOSFET structure design according to claim 1, characterized in that the outer contour shapes of the sub-steps are the same or different. 6. The high-power planar gate D-MOSFET structure design according to claim 1, characterized in that, the outer contour of the sub-step is arc, curve, broken line or any combination of these three types of shapes. 7. The high-power planar gate D-MOSFET structure design as claimed in claim 1, wherein the number k of the sub-steps needs to satisfy [0.5 μm*(k-1)]<W _min ; the W _min is the smaller value of the total depth W _y and the total width W _x of the P-well structure or the N-well structure. 8. The high-power planar gate D-MOSFET structure design according to claim 7, wherein the sub-step is a single sub-step with a depth and a width of 0.5 μm. 9. The high-power planar gate D-MOSFET structure design according to claim 7, wherein the depth and/or width of each sub-step is different, the depth does not exceed W _y /k, and the width does not exceed W _x / k. 10. The high-power planar gate D-MOSFET structure design according to any one of claims 1-9, wherein the ladder-like structure conducts ion implantation through at least two ion implantation windows formed by masks and/or protective layers. The implantation is formed, and the implantation energy of each ion implantation is different, and a larger ion implantation window is matched with a smaller energy ion implantation.