CN106876350A - Power module and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a power module and a manufacturing method thereof, wherein the power module comprises a carrier substrate, an internal wiring layer, a first chip, a second chip, a ceramic bonding plate, a top internal wiring layer and a lead frame. The internal wiring layer is located on the carrier substrate. The first chip and the second chip are located on the internal wiring layer, wherein the first chip and the second chip are electrically connected to the internal wiring layer. The ceramic bonding plate is located on the internal wiring layer and is arranged between the first chip and the second chip to isolate the first chip from the second chip. The top internal wiring layer is located on the ceramic bonding plate and covers the first chip and the second chip. The top internal wiring layer is electrically connected to the first chip and the second chip. The lead frame is located on the top internal wiring layer and is electrically connected to the top internal wiring layer.

Description

Power module and manufacturing method thereof

technical field

The present invention relates to a power module and its manufacturing method, and in particular to a power module with small volume and good heat dissipation and its manufacturing method.

Background technique

In recent years, the manufacturing technology of integrated circuits (ICs) has developed rapidly, which greatly improves the functions of electronic components. Along with the improvement of processing speed and performance of electronic components, the heat generated by electronic components also increases accordingly. If the waste heat cannot be effectively removed, electronic components may fail or fail to achieve optimal performance. The structure of traditional small power modules such as integrated intelligent power modules (Intelligent Power Module, IPM) is manufactured in the form of wire bonding and lead frame combined molding, and is directly bonded on the copper (Direct Bond Copper, DBC) substrate. Bare copper structure for heat dissipation. However, traditional power modules still have disadvantages such as large volume and poor heat dissipation of components. Therefore, how to improve the design of the existing power module to make it thinner and improve its heat dissipation capability is the subject of current research.

Contents of the invention

The object of the present invention is to provide a power module and a manufacturing method thereof, which can make the power module thinner and have good heat dissipation capability at the same time.

To achieve the above purpose, the power module proposed by the present invention includes a carrier substrate, an interconnection layer, a first chip, a second chip, a ceramic bonding board, a top interconnection layer, and a lead frame. The interconnect layer is located on the carrier substrate. The first chip and the second chip are located on the interconnect layer, wherein the first chip and the second chip are electrically connected to the interconnect layer. A ceramic bonding substrate is located on the interconnect layer and disposed between the first chip and the second chip to isolate the first chip from the second chip. The top interconnection layer is on the ceramic bonding board and covers the first chip and the second chip. The top interconnect layer is electrically connected to the first chip and the second chip. The lead frame is located on the top interconnection layer and is electrically connected to the top interconnection layer. The molding material layer is on the lead frame.

The manufacturing method of the power module proposed by the present invention includes forming an interconnection layer on the carrier substrate. The first chip and the second chip are arranged on the interconnect layer, wherein the first chip and the second chip are electrically connected to the interconnect layer. A ceramic bonding substrate is formed on the interconnect layer, wherein the ceramic bonding substrate is disposed between the first chip and the second chip to isolate the first chip from the second chip. A top interconnection layer is formed on the ceramic bonding board and covers the first chip and the second chip, wherein the top interconnection layer is electrically connected to the first chip and the second chip. A lead frame is formed on the top interconnect layer, wherein the conductive frame is electrically connected to the top interconnect layer. Finally, a molding material is formed on the lead frame as a layer of molding material, and the molding material is molded and cut to form a power module.

Based on the above, the power module and its manufacturing method of the present invention use the ceramic bonding board to isolate the chip insulation voltage, and spread the heat of the chip through the better heat transfer characteristics of the ceramic material, and use the interconnection layer to transmit electrical signals, so The power module can be made thinner, thereby shortening the heat and electrical transmission distance, and improving the heat dissipation capability of the power module.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

1A to 1F are schematic cross-sectional views of the manufacturing process of a power module according to an embodiment of the present invention;

2A to 2C are schematic cross-sectional views of the manufacturing process of a power module according to another embodiment of the present invention;

3A to 3B are schematic cross-sectional views of the manufacturing process of a power module according to another embodiment of the present invention;

4A to 4B are schematic cross-sectional views of the structure and manufacturing process of a power module according to another embodiment of the present invention.

Symbol Description

10A, 10B: power module

100: Carrier substrate

110: metal base substrate

111: metal core layer

112: insulating dielectric layer

200: Inner layer

210, 410, 510: insulating layer

220, 420, 520: wire structure

230, 530: Metal bonding pattern

300A, 300B: Ceramic bonding plate

300X: resin material

301, 302: metal bonding layer

400: top interconnect layer

500: first interconnect layer

610: Conductive frame

620: heat dissipation metal layer

700: molding material layer

CP1: first chip

CP2: second chip

CP3, CP4: chip

GP: Gap

TS1, TS2: temperature sensor

CND1, CND2: conductive structure

detailed description

1A to 1F are schematic cross-sectional views of the manufacturing process of a power module according to an embodiment of the present invention. First, please refer to FIG. 1A , the manufacturing method of the power module of this embodiment includes providing a carrier substrate 100 , the material of the carrier substrate 100 includes ceramics, quartz, glass, diamond-like or other materials with insulating properties, but is not limited thereto. The ceramic material includes aluminum oxide (Al ₂ O ₃ ), gallium nitride (GaN), silicon carbide (SiC), aluminum nitride (AlN) or beryllium oxide (BeO). Next, an interconnection layer 200 is formed on the carrier substrate 100 . The interconnection layer 200 includes an insulating layer 210 and a wire structure 220 inside the insulating layer 210 , wherein the wire structure 220 is, for example, copper, tungsten or other metals or alloys with good electrical and thermal conductivity. In addition, in this embodiment, the surface of the interconnection layer 200 is further provided with a metal bonding pattern 230 . More specifically, the formation method of the interconnection layer 200 is, for example, performing at least one metal interconnection fabrication process, which includes the deposition fabrication process of insulating material, exposure and development, etching or laser drilling to form a patterned insulating material and patterned The metal material is filled into the insulating material, and the required interconnection structure (the interconnection layer 200 shown in FIG. 1 ) can be formed by repeating the metal interconnection manufacturing process many times. However, the metal bonding pattern 230 of this embodiment can be defined during the aforementioned metal interconnection manufacturing process.

Next, please refer to FIG. 1B , a first chip CP1 and a second chip CP2 are disposed on the interconnect layer 200 , wherein the first chip CP1 and the second chip CP2 are electrically connected to the interconnect layer 200 . In particular, the wiring structure 220 of the interconnection layer 200 extends from where the first chip CP1 and the second chip CP2 are located to a place where the first chip CP1 and the second chip CP2 are not overlapped, that is, the wiring structure 220 extends to the first chip CP1 and the second chip CP2. The chip footprints of the first chip CP1 and the second chip CP2 are outside, so that the interconnection layer 200 serves as a redistribution layer. Therefore, the structure formed by the chip and the interconnection layer of this embodiment can also be called a fan-out (Fan Out) structure, which can provide a structure for making external electrode contacts, improve assembly yield and reduce the risk of chip electrode contacts being too close to each other. lead short circuit problem.

The first chip CP1 and the second chip CP2 are, for example, chips containing power elements such as diodes (Diodes), insulated gate bipolar transistors (IGBTs), and metal oxide half field effect transistors (MOSFETs), so there are electrodes on the upper and lower sides of the chips, But not limited to this. In addition, in this embodiment, the temperature sensor TS1 or other driving chips required by the power module can be selectively disposed on the interconnection layer 200 according to requirements.

Next, please refer to FIG. 1C , a ceramic bonding substrate 300A (ceramic bonding substrate) is provided, and the ceramic bonding substrate 300A has a specific opening pattern, and the specific opening pattern is a predetermined arrangement of chips, sensors or other structures. The material of the ceramic joint plate 300A includes aluminum oxide (Al ₂ O ₃ ), gallium nitride (GaN), silicon carbide (SiC), aluminum nitride (AlN) or beryllium oxide (BeO) and other high thermal conductivity electrical insulating materials, But not limited to this. In addition, the bottom of the ceramic bonding plate 300A is partially provided with a metal bonding layer 301 . The material of the metal bonding layer 301 is, for example, a material that can be bonded to the metal bonding pattern 230 . For example, if the metal bonding pattern 230 is made of copper, then the metal bonding layer 301 can also be copper.

Referring to FIG. 1D , the ceramic bonding board 300A is disposed on the interconnection layer 200 , and the metal bonding layer 301 of the ceramic bonding board 300A is bonded to the metal bonding pattern 230 of the interconnection layer 200 . After the ceramic bonding board 300A is bonded to the interconnection layer 200 , the ceramic bonding board 300A is disposed between the first chip CP1 and the second chip CP2 to isolate the first chip CP1 from the second chip CP2 . In this embodiment, there are gaps GP between the first chip CP1 and the ceramic bonding plate 300A and between the second chip CP2 and the ceramic bonding plate 300A.

Next, referring to FIG. 1E, a top interconnection layer 400 is formed on the ceramic bonding board 300A, and the top interconnection layer 400 covers the first chip CP1 and the second chip CP2, wherein the top interconnection layer 400 is connected to the first chip CP1 and the second chip CP2. The second chip CP2 is electrically connected. The top interconnect layer 400 includes an insulating layer 410 and a wire structure 420 inside the insulating layer 410 . The method for forming the top interconnection layer 400 is, for example, performing at least one metal interconnection fabrication process, which includes filling metal material on the ceramic bonding board 300A, deposition fabrication process of insulating material, exposure and development, etching or laser drilling to form a pattern Insulation material is patterned and metal material is filled in the patterned insulation material, and the required interconnection structure (top interconnection layer 400 as shown in FIG. 1 ) can be formed by repeating the metal interconnection manufacturing process several times.

In this embodiment, since there are gaps GP between the first chip CP1 and the ceramic bonding board 300A and between the second chip CP2 and the ceramic bonding board 300A, during the process of forming the top interconnection layer 400, the The insulating layer 410 will fill in the gap GP. Specifically, in order to reduce the thermal stress caused by the mismatch of thermal expansion coefficients, the material of the insulating layer 410 can be selected to be elastic, and injected into each chip (CP1, CP2) during the build-up process of forming the top interconnection layer 400. ) gap GP between the edge and the sidewall of the opening of the ceramic bonding plate 300A. In addition, in this embodiment, the process of forming the top interconnection layer 400 also includes forming a conductive structure CND1 in the ceramic bonding board 300A, wherein the conductive structure CND1 is electrically connected to the interconnection layer 200 and the top interconnection layer 200 respectively. Wire layer 400.

Finally, referring to FIG. 1F , a lead frame 610 is formed on the top interconnection layer 400 , and the conductive frame 610 is electrically connected to the top interconnection layer 400 . After the above manufacturing process is completed, a molding material is formed on the lead frame 610 as the membrane material layer 700 , and the mold material is finally molded and cut to form the power module of this embodiment. In addition, in this embodiment, the heat dissipation metal layer 620 (such as copper) can be further coated on the bottom surface of the carrier substrate 100 to further increase the heat dissipation effect of the power module.

In this embodiment, since the first chip CP1 and the second chip CP2 are fixed in the opening of the ceramic bonding board 300A, and the gap GP is filled with the insulating layer 410, therefore, the chip position can be prevented from shifting during the manufacturing process. Moreover, the wire-free structure can make the power module thinner, shorten the heat and electrical transmission distance and improve the heat dissipation performance of the power module.

Accordingly, the structure of a power module 10A according to an embodiment of the present invention can be achieved through the steps in FIG. 1A to FIG. 1F . In short, as shown in FIG. 1F, the power module 10A of this embodiment includes a carrier substrate 100, an interconnection layer 200, a first chip CP1, a second chip CP2, a ceramic bonding board 300A, and a top interconnection layer. 400 , lead frame 610 , heat dissipation metal layer 620 and molding material layer 700 . In particular, the interconnect layer 200 is located on the carrier substrate 100 . The first chip CP1 and the second chip CP2 are located on the interconnect layer 200 , wherein the first chip CP1 and the second chip CP2 are electrically connected to the interconnect layer 200 . The ceramic bonding board 300A is located on the interconnect layer 200 and disposed between the first chip CP1 and the second chip CP2 to isolate the first chip CP1 from the second chip CP2 . The top interconnection layer 400 is located on the ceramic bonding board 300A and covers the first chip CP1 and the second chip CP2 , wherein the top interconnection layer 400 is electrically connected to the first chip CP1 and the second chip CP2 . The lead frame 610 is located on the top interconnect layer 400 and is electrically connected to the top interconnect layer 400 . The molding material layer 700 is located on the lead frame 610 . In addition, the above-mentioned structures can be stacked to form a 3D structure through the same manufacturing process as required.

In the above-mentioned embodiment, after the first chip CP1 and the second chip CP2 are disposed on the interconnection layer 200 , the ceramic bond plate 300A is formed on the interconnection layer 200 , but the present invention is not limited thereto. For example, FIG. 2A to FIG. 2C are cross-sectional schematic diagrams of the manufacturing process of a power module according to another embodiment of the present invention. This embodiment is similar to FIG. 1A to FIG. To repeat, the differences are explained below. Referring to FIG. 2A , a ceramic bonding pad 300A having a plurality of openings is formed on the interconnection layer 200 . A metal bonding layer 301 is partially provided on the bottom of the ceramic bonding plate 300A. The ceramic bonding board 300A is disposed on the interconnect layer 200 and bonded to the interconnect layer 200 through the metal bonding layer 301 . Next, referring to FIG. 2B to FIG. 2C , the first chip CP1 and the second chip CP2 are disposed on the interconnection layer 200, wherein the first chip CP1 and the second chip CP2 are embedded in the ceramic bonding board 300A and the interconnection layer Inside the opening formed by layer 200. In other words, in the embodiment of FIG. 2A to FIG. 2C , the first chip CP1 and the second chip CP2 are disposed on the interconnection layer 200 after the ceramic bonding plate 300A is formed on the interconnection layer 200 . Subsequently, the method of forming the power module can also refer to the steps in FIG. 1E to FIG. 1F to form the power module 10A of the embodiment of the present invention.

3A to 3B are schematic cross-sectional views of the manufacturing process of a power module according to another embodiment of the present invention. This embodiment is similar to FIG. 1A to FIG. 1F , so the same elements are denoted by the same symbols, and will not be described again, and the differences are described as follows. As shown in FIG. 3A , an adhesive semi-dry state B stage (B stage) resin material 300X is first formed on the interconnection layer 200 . The B stage (B stage) resin material 300X is formed in a region where no chip is intended to be placed. Next, in the step of FIG. 3B , the ceramic bonding plate 300A is formed on the B stage (B stage) resin material 300X, and the steps of thermocompression bonding and curing are performed, so that the ceramic bonding plate 300A passes through the B stage (B stage) resin material. Material 300X is bonded to interconnect layer 200 . After that, the first chip CP1 and the second chip CP2 are disposed in the opening formed by the ceramic bonding board 300A and the interconnection layer 200 . Even, the temperature sensor TS1 or other driving chips required by the power module can be further set. Subsequently, the method of forming the power module can also refer to the steps in FIG. 1E to FIG. 1F to form the power module of the embodiment of the present invention. The bonding of the ceramic bonding board 300A in this embodiment is directly formed on the interconnection layer 200 through pressing and curing steps, so the bonding does not need to be performed through a metal bonding pattern and a metal bonding layer.

4A to 4B are schematic cross-sectional views of the structure and manufacturing process of a power module according to another embodiment of the present invention. Referring to FIG. 4A , the carrier substrate 100 of this embodiment is a metal-based substrate 110 (MCPCB, Metal core PCB). Specifically, the metal-based substrate 110 includes a metal core layer 111 and an insulating dielectric layer 112, and is based on the metal core layer 111. The material of the metal core layer is a metal material with high heat transfer characteristics such as copper and aluminum. The upper layer of the core layer 111 is layered with dielectric (insulating) material, insulating heat-conducting glue, ABF and other materials by means of lamination or coating to form the insulating dielectric layer 112, and then the carrier substrate is applied in the same manner as in the aforementioned embodiment 1A. An interconnection layer 200 is formed on top of 100 . In detail, the interconnection layer 200 can be used as a bottom interconnection layer and includes an insulating layer 210 and a wire structure 220 inside the insulating layer 210 , wherein the wire structure 220 is made of a material with high thermal conductivity such as copper. In addition, the surface of the interconnection layer 200 (bottom interconnection layer) has a metal bonding pattern 230 .

In addition, a first chip CP1 (first bottom chip) and a second chip CP2 (second bottom chip) are disposed on the interconnection layer 200 (bottom interconnection layer), wherein the first chip CP1 and the second chip CP2 are connected to The interconnection layer 200 (bottom interconnection layer) is electrically connected. In particular, the wiring structure 220 of the interconnection layer 200 extends from where the first chip CP1 and the second chip CP2 are located to a place where the first chip CP1 and the second chip CP2 are not overlapped, that is, the wiring structure 220 extends to the first chip CP1 and the second chip CP2. The chip footprints of the first chip CP1 and the second chip CP2 are outside, so that the interconnection 200 serves as a redistribution layer. The first chip CP1 and the second chip CP2 are, for example, chips containing power elements such as diodes (Diodes), insulated gate bipolar transistors (IGBTs), metal oxide half field effect transistors (MOSFETs), or other power modules required for driving chip, but not limited to this. In this embodiment, the wire structure 220 extends from the place where the first chip CP1 and the second chip CP2 are located to the place where the first chip CP1 and the second chip CP2 are not overlapped, and this structure can also be called fan out (Fan Out). )structure. In addition, in this embodiment, a related sensor, such as a temperature sensor TS1 , may be selectively disposed on the interconnection layer 200 , but not limited thereto.

In the embodiment of FIG. 4A, a ceramic bonding substrate 300A (ceramic bonding substrate) can be used as a bottom ceramic bonding substrate, and is located on the interconnection layer 200 and disposed between the first chip CP1 and the second chip CP2 so that The first chip CP1 is isolated from the second chip CP2. The material of the ceramic bonding plate 300A includes, but is not limited to, electrical insulating materials such as aluminum oxide (Al ₂ O ₃ ), gallium nitride (GaN), silicon carbide (SiC), aluminum nitride (AlN) and beryllium oxide (BeO). . In this embodiment, the metal bonding layer 301 is partially provided on the bottom of the ceramic bonding plate 300A. The ceramic bonding board 300A is bonded to the metal bonding pattern 230 on the interconnection layer 200 through the metal bonding layer 301 .

In addition, the first interconnection layer 500 is located on the ceramic bond pad 300A, the first chip CP1 (first bottom chip), and the second chip CP2 (second bottom chip). In other words, the first interconnect layer 500 is formed over the interconnect layer 200 (bottom interconnect layer) and the ceramic bond pad 300A (bottom ceramic bond pad). In particular, there are gaps GP between the first chip CP1 and the ceramic bonding plate 300A and between the second chip CP2 and the ceramic bonding plate 300A. The first interconnect layer 500 includes an insulating layer 510 and a wire structure 520 inside the insulating layer 510 , wherein the insulating layer 510 fills the gap GP. In addition, the manufacturing method of the power module of this embodiment further includes forming a conductive structure CND1 in the ceramic bonding board 300A, wherein the conductive structure CND1 is electrically connected to the interconnection layer 200 and the first interconnection layer 500 respectively. The material, structure, and arrangement relationship of the first interconnection layer 500 may be the same as those defined for the interconnection layer 200 above, so details will not be repeated here. Next, as shown in the steps of Embodiment 1C to 1F, the ceramic bonding board 300B, chip CP3 (same as the first chip CP1), chip CP4 (same as the second chip CP2) and the top interconnection 400 are formed in the first interconnection. above the wiring layer 500 . It should be noted that, in this embodiment, the interconnection layer 200 can be used as the bottom interconnection layer, and only one layer of the first interconnection layer is included between the interconnection layer 200 and the top interconnection layer 400. The wire layer 500, however, the present invention is not limited thereto. For example, in other embodiments, multiple interconnection layers can be provided between the interconnection layer 200 (bottom interconnection layer) and the top interconnection layer 400 according to requirements.

Finally, referring to FIG. 4B , a lead frame 610 is formed on the top interconnection layer 400 , wherein the conductive frame 610 is electrically connected to the top interconnection layer 400 . After the above manufacturing process is completed, a molding material is formed on the lead frame 610 as the molding material layer 700 , and the molding material is finally molded and cut to form the power module of this embodiment. Since the present embodiment adopts the thicker metal-based substrate 110 as the carrier substrate, this structure can further increase the heat dissipation effect of the power module. Through the above method, a power module 10B according to another embodiment of the present invention as shown in FIG. 4B can be formed. Similarly, the structural design of the power module 10B can enhance the heat dissipation of the power module, shorten the heat transmission distance, and achieve a better heat dissipation effect.

To sum up, the power module and its manufacturing method of the present invention use the opening structure made by the ceramic bonding board and the interconnection layer to fix the position of each chip, and the interconnection layer includes an insulating layer and an insulating layer located on the insulating layer. The internal wire structure is used to transmit electrical signals, so the power module can be made thinner and the heat and electrical transmission distance can be shortened.

In addition, because the wiring structure of the interconnection layer extends from the place where the first chip and the second chip are located to the place where the first chip and the second chip are not overlapped, that is, the wiring structure extends to the space between the first chip and the second chip. Outside the chip footprint, therefore, enabling the interconnect layer to act as a redistribution layer. Similarly, in another embodiment, since the wiring structure of the bottom interconnection layer extends from the place where the first bottom chip and the second bottom chip are located to a place that does not overlap with the first bottom chip and the second bottom chip, That is, the wire structure extends outside the chip footprints of the first bottom chip and the second bottom chip, so that the bottom interconnection layer can be used as a redistribution layer. The design of this structure can improve the assembly yield and reduce the problem of chip contact short circuit in the interconnection layer.

Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (23)

1. a kind of power model, including：

Bearing substrate；

Internal connecting layer, on the bearing substrate；

First chip and the second chip, in the internal connecting layer, wherein first chip with this second Chip is electrically connected with the internal connecting layer；

Ceramic joint plate, in the internal connecting layer and be arranged at first chip and second chip it Between, so that first chip is kept apart with second chip；

Top internal connecting layer, in the ceramic joint plate and covers first chip and second chip, The top internal connecting layer is electrically connected with first chip and second chip；

Lead frame, electrically connects in the top internal connecting layer and with the top internal connecting layer；

Molding material layer, on the lead frame.

2. power model as claimed in claim 1, also including conductive structure, through the ceramic joint plate, Wherein the conductive structure is electrically connected the internal connecting layer and the top internal connecting layer.

3. power model as claimed in claim 1, wherein：

Between first chip and the ceramic joint plate and between second chip and the ceramic joint plate There is a gap respectively, and the top internal connecting layer includes an insulating barrier and in the insulating barrier one Conductor structure, the insulating barrier is inserted in those gaps.

4. power model as claimed in claim 1, the wherein internal connecting layer include insulating barrier and are located at Conductor structure in the insulating barrier, the conductor structure prolongs from first chip with the second chip whereabouts Part not Chong Die with first chip and second chip is extended, so that the internal connecting layer is divided as one again With layer.

5. power model as claimed in claim 1, also includes：

Bottom internal connecting layer, on the bearing substrate；

First bottom chip and the second bottom chip, in the bottom internal connecting layer, wherein this first Bottom chip is electrically connected with second bottom chip with the bottom internal connecting layer；And

Bottom ceramics joint plate, in the bottom internal connecting layer and be arranged at first bottom chip with should So that first bottom chip is kept apart with second bottom chip between second bottom chip, wherein

Also include the first internal connecting layer, positioned at the bottom ceramics joint plate, first bottom chip and should In second bottom chip.

6. power model as claimed in claim 5, the wherein bearing substrate are a Metal base substrate, and The Metal base substrate includes metal core layer and insulation dielectric layer.

7. power model as claimed in claim 5, also including conductive structure, connects through the bottom ceramics Plywood, the wherein conductive structure are electrically connected the bottom internal connecting layer and first internal connecting layer.

8. power model as claimed in claim 5, wherein：

Between first bottom chip and bottom ceramics joint plate and second bottom chip and bottom There is a gap respectively between portion's ceramics joint plate, and

First internal connecting layer includes an insulating barrier and the conductor structure in the insulating barrier, and this is exhausted Edge layer is inserted in those gaps.

9. power model as claimed in claim 1, also including a heat radiating metallic layer, positioned at the carrying base On one basal surface of plate.

10. a kind of manufacture method of power model, including：

An internal connecting layer is formed on a bearing substrate；

In the internal connecting layer set one first chip and one second chip, wherein first chip with should Second chip is electrically connected with the internal connecting layer；

A ceramic joint plate is formed in the internal connecting layer, the wherein ceramic joint plate is arranged at first core So that first chip is kept apart with second chip between piece and second chip；

A top internal connecting layer is formed in the ceramic joint plate, and covers first chip and second core Piece, wherein the top internal connecting layer are electrically connected with first chip and second chip；

A lead frame is formed in internal connecting layer at the top of this, the conduction rack is electrically connected with the top internal connecting layer Connect；And

A molding material is formed on the lead frame as a molding material layer, and the molding material is carried out Molding cuts to form the power model.

The manufacture method of 11. power models as claimed in claim 10, wherein being set in the internal connecting layer Put after first chip and second chip, the ceramic joint plate is formed in the internal connecting layer.

The manufacture method of 12. power models as claimed in claim 10, wherein in shape in the internal connecting layer Into after the ceramic joint plate, first chip and second chip are set in the internal connecting layer.

The manufacture method of 13. power models as claimed in claim 10, wherein forming the ceramic joint plate Method include：

A ceramic substrate is provided, the ceramic substrate bottom is partly provided with a metallic bond layer；And

The ceramic substrate is arranged in the internal connecting layer, and by the metallic bond layer and the internal connecting layer It is bonded together.

The manufacture method of 14. power models as claimed in claim 13, the wherein surface of the internal connecting layer With a metal bond pattern, the metal bond pattern is joined together with the metallic bond layer.

The manufacture method of 15. power models as claimed in claim 10, wherein forming the ceramic joint plate Method include：

One B-stage resin material is coated into being not provided with first chip and being somebody's turn to do in the internal connecting layer The region of the second chip；And

The ceramic joint plate is formed on the B-stage resin material, and carries out a pressing curing schedule, So that the ceramic joint plate is engaged by the B-stage resin material with the internal connecting layer.

The manufacture method of 16. power models as claimed in claim 10, is also included in the ceramic joint plate One conductive structure of interior formation, the conductive structure is electrically connected the internal connecting layer and the top intraconnections Layer.

The manufacture method of 17. power models as claimed in claim 10, wherein：

Between first chip and the ceramic joint plate and between second chip and the ceramic joint plate There is a gap respectively, and

The top internal connecting layer includes an insulating barrier and the conductor structure in the insulating barrier, and this is exhausted Edge layer is inserted in those gaps.

The manufacture method of 18. power models as claimed in claim 10, the wherein internal connecting layer include one Insulating barrier and the conductor structure in the insulating barrier, the conductor structure from first chip and this Two chip whereabouts extend to part not Chong Die with first chip and second chip, so that this is interior Connecting line layer reassigns layer as one.

The manufacture method of 19. power models as claimed in claim 10, also includes：

A bottom internal connecting layer is formed on the bearing substrate；

One first bottom chip and one second bottom chip are set in the bottom internal connecting layer, wherein should First bottom chip is electrically connected with second bottom chip with the bottom internal connecting layer；And

Bottom ceramics joint plate is formed in the bottom internal connecting layer, bottom ceramics joint plate is arranged at Between first bottom chip and second bottom chip so that first bottom chip and second bottom Chip is kept apart, wherein

Also include that one first internal connecting layer is located at the ceramic joint plate in the bottom, first bottom chip and is somebody's turn to do In second bottom chip.

The manufacture method of 20. power models as claimed in claim 19, the wherein bearing substrate are a gold medal Category base substrate, and the forming method of the Metal base substrate includes that with a metal core layer be substrate, and at this An insulation dielectric layer is formed on metal core layer.

The manufacture method of 21. power models as claimed in claim 19, is also included in the bottom ceramics and connects A conductive structure is formed in plywood, the wherein conductive structure is electrically connected the bottom internal connecting layer and is somebody's turn to do First internal connecting layer.

The manufacture method of 22. power models as claimed in claim 19, wherein：

Between first bottom chip and bottom ceramics joint plate and the second bottom chip and bottom There is a gap respectively between ceramic joint plate, and

First internal connecting layer includes an insulating barrier and the conductor structure in the insulating barrier, and this is exhausted Edge layer is inserted in those gaps.

The manufacture method of 23. power models as claimed in claim 10, is also included in the bearing substrate A heat radiating metallic layer is formed on one basal surface.