CN106876330A - A kind of array base palte and preparation method thereof, display panel and display device - Google Patents

Abstract

Embodiments of the present invention provide an array substrate and its preparation method, a display panel, and a display device. By arranging the drain, the source, the data line, and the touch wiring on the same layer, it is avoided to separately arrange the film where the touch wiring is located. layer, so that there is no need to use a separate mask to make the touch wiring layer through the corresponding patterning process; and, by directly electrically connecting the pixel electrode and the drain without passing through the via The patterning process of the stencil is used to carry out hole engraving; thus eliminating the need for two mask patterning processes. Therefore, the technical solution provided by the embodiments of the present invention can simplify the manufacturing process of the array substrate, reduce the complexity of the process flow, reduce the number of masks used, and reduce the production cost.

Description

A kind of array substrate and its preparation method, display panel and display device

【Technical field】

The present invention relates to the field of touch technology, in particular to an array substrate and a preparation method thereof, a display panel and a display device.

【Background technique】

With the development of the field of touch technology, display panels with touch functions have increasingly become mainstream display products. The existing integration methods of display panels and touch panels are generally divided into two methods: in-cell (embedded) and on-cell (outside the box). Compared with on-cell touch screens, in-cell touch screens are more For thin and light. At present, the array substrate of the in-cell touch screen in the prior art at least includes a gate metal layer, a semiconductor layer, a source-drain metal layer, a first silicon nitride layer, a pixel electrode, a touch metal layer, and a second silicon nitride layer. and common electrodes.

The inventor finds that there are at least the following problems in the prior art:

In the preparation process of the array substrate in the prior art, when forming the above-mentioned gate metal layer, semiconductor layer, source-drain metal layer, first insulating layer, pixel electrode, touch metal layer, second insulating layer and common electrode, Each layer needs to be produced by using a separate mask plate through a corresponding patterning process, the process flow is relatively complicated, a large number of mask plates are required, and the production cost is high.

【Content of invention】

In view of this, embodiments of the present invention provide an array substrate and a manufacturing method thereof, a display panel and a display device, which can reduce the number of masks used and simplify the manufacturing process of the array substrate.

In one aspect, an embodiment of the present invention provides an array substrate, including:

Substrate substrate;

a first metal layer on the base substrate, the first metal layer includes a gate and a gate line;

an active layer on the first metal layer;

a pixel electrode located on the film layer where the gate and gate line are located;

a second metal layer located on the active layer and the pixel electrode, the second metal layer includes a drain electrode, a source electrode and a data line, wherein the drain electrode is electrically connected to the pixel electrode;

A common electrode layer located on the second metal layer, the common electrode layer includes a plurality of common electrode blocks arranged in an array, and the common electrode blocks are multiplexed as touch electrodes; the array substrate further includes:

The touch wiring is located on the second metal layer; the touch wiring is electrically insulated from the drain, source, data line and pixel electrode, and is connected to the common electrode of the common electrode layer through a via hole block electrical connections.

Specifically, the array substrate also includes:

The first insulating layer is located between the first metal layer and the active layer.

Specifically, the array substrate also includes:

The second insulating layer is located between the common electrode layer and the second metal layer; the second insulating layer is provided with via holes.

Specifically, the drain is directly electrically connected to the pixel electrode.

Specifically, the touch wiring is arranged adjacent to the data line, and the touch wiring is parallel to the data line.

On the other hand, an embodiment of the present invention provides a display panel, including: the above-mentioned array substrate.

On the other hand, an embodiment of the present invention provides a display device, including: the above-mentioned display panel.

On the other hand, an embodiment of the present invention provides a method for manufacturing an array substrate, including:

forming a first metal layer on the base substrate, the first metal layer including a gate and a gate line;

forming an active layer on the first metal layer;

forming a pixel electrode on the film layer where the gate and the gate line are located;

Forming a second metal layer and a touch control line on the active layer and the pixel electrode, wherein the second metal layer and the second metal layer including the drain electrode, the source electrode and the data line are located, Wherein, the drain is electrically connected to the pixel electrode;

forming a second insulating layer covering the second metal layer, forming via holes on the second insulating layer; forming a common electrode layer on the second metal layer, wherein the common electrode layer includes a plurality of The provided common electrode block is multiplexed as a touch electrode, and the common electrode block is electrically connected to the touch trace through the via hole.

Specifically, the method also includes:

A first insulating layer is formed between the first metal layer and the active layer.

Specifically, the method also includes:

A second insulating layer is formed between the common electrode layer and the second metal layer, and a via hole is formed on the second insulating layer.

Specifically, the drain is directly electrically connected to the pixel electrode.

Specifically, the touch wiring is arranged adjacent to the data line, and the touch wiring is parallel to the data line.

One of the above technical solutions has the following beneficial effects:

Embodiments of the present invention provide an array substrate and its preparation method, a display panel, and a display device. By arranging drains, sources, data lines, and touch lines on the same layer, it is avoided to separately set the film layer where the touch lines are located. , so there is no need to use a separate mask and use a corresponding patterning process to manufacture the touch wiring layer, which can simplify the manufacturing process of the array substrate, reduce the complexity of the process flow, reduce the number of masks used, and reduce the production cost.

【Description of drawings】

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. Those of ordinary skill in the art can also obtain other drawings based on these drawings without paying creative labor.

FIG. 1 is a schematic structural diagram of a pixel unit on an array substrate provided by an embodiment of the present invention;

Fig. 2 is the schematic diagram of the sectional structure of AA' direction in Fig. 1;

3 is a schematic structural diagram of another pixel unit on an array substrate provided by an embodiment of the present invention;

4 is a schematic diagram of the steps of a method for preparing an array substrate provided by an embodiment of the present invention;

5 is a schematic diagram of the steps of a method for preparing an array substrate provided by an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a display device provided by an embodiment of the present invention.

【detailed description】

In order to better understand the technical solutions of the present invention, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

It should be clear that the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. As used in the embodiments of the present invention and the appended claims, the singular forms "a", "said" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

It should be understood that although the terms first, second, third, etc. may be used to describe insulating layers in the embodiments of the present invention, these insulating layers should not be limited to these terms. These terms are only used to distinguish insulating layers from one another. For example, without departing from the scope of the embodiments of the present invention, a first insulating layer may also be called a second insulating layer, and similarly, a second insulating layer may also be called a first insulating layer.

As shown in Figures 1 and 2, Figure 1 is a schematic structural view of a pixel unit on an array substrate provided by an embodiment of the present invention; The embodiment provides a schematic structural diagram of another pixel unit on an array substrate. The present invention provides an array substrate, including: a base substrate 1; a first metal layer 2 located on the base substrate 1, the first metal Layers include gate 21 and gate line 22; active layer 3 on the first metal layer 2; pixel electrode 4 on the film layer where gate 21 and gate line 22 are located; active layer 3 and pixel electrode 4 The second metal layer 5, the second metal layer 5 includes a drain 51, a source 52 and a data line 53, wherein the drain 51 is electrically connected to the pixel electrode 4; the common electrode layer 6 on the second metal layer 5 The common electrode layer 6 includes a plurality of common electrode blocks arranged in an array, and the common electrode blocks are multiplexed as touch electrodes; the touch trace 7 is located on the second metal layer 5; the touch trace 7 is connected to the drain 51, The source electrode 52 , the data line 53 and the pixel electrode 4 are electrically insulated, and are electrically connected to the common electrode block of the common electrode layer 6 through the via hole 91 . Wherein, the array substrate includes a plurality of sub-pixel units defined by intersections of multiple rows of gate lines and multiple columns of data lines. In each sub-pixel unit, the source and drain are respectively located on both sides of the active layer, and the gate and the active layer The channel regions of the array substrates are arranged oppositely, and the source, drain, active layer and gate form a thin film transistor (Thin Film Transistor, TFT) in the array substrate.

It should be noted that each common electrode in Figure 1 and Figure 3 corresponds to a touch trace. In the actual process, the requirements for touch accuracy are far less than the display accuracy, so one common electrode corresponds to how many sub-pixels, and each common electrode is electrically connected to a touch trace through a via hole. In the embodiment shown in FIG. 1 , two adjacent data lines 53 and two adjacent gate lines 22 intersect to form a sub-pixel. Adjacent sub-pixel units of different colors can form a pixel unit, for example, a red sub-pixel, a green sub-pixel and a blue sub-pixel adjacent in the row direction can form a pixel, and multiple Each sub-pixel can display different colors according to different gray levels. In production, the number of common electrodes can be adjusted according to different design requirements. In the same situation, the more the number of common electrodes, the fewer the number of sub-pixels corresponding to each common electrode. Since each common electrode still corresponds to one contact Control wiring, so the number of touch wiring and vias will increase accordingly.

Referring to FIG. 1 and FIG. 3, it can be seen that, under the condition that other structures are the same, in the embodiment of FIG. 1, each sub-pixel is correspondingly provided with a common electrode, while in FIG. Correspondingly, one common electrode is provided, and the number of common electrodes in the embodiment shown in FIG. 1 is greater than that in the embodiment shown in FIG. 3 . Correspondingly, the number of touch traces and vias in the embodiment shown in FIG. Number of touch traces and vias. Each pixel unit in Figure 3 corresponds to a touch trace. Correspondingly, each pixel unit corresponds to a via hole used to connect the touch trace and the common electrode block. The pixel unit includes three different colors in the row direction. Sub-pixels reduce the number of via holes to simplify the complexity of the array substrate manufacturing process.

It should be noted that this embodiment is only a schematic illustration. In an actual implementation process, an array substrate may include block-shaped common electrodes arranged in a matrix of m*n, where m>2, n>2, In addition, both m and n are natural numbers, and the block-shaped common electrode is preferably rectangular. Each block-shaped common electrode can cover i*j sub-pixel areas correspondingly, where i>2, j>2, and both i and j are natural numbers. Since in the display phase, each common electrode needs to form an electric field with the pixel electrode, therefore, each common electrode needs to cover the opening area of each sub-pixel, that is, the slit formed between two adjacent common electrodes, in the vertical In the direction of the plane where the array substrate is located, it overlaps with the scanning line or the data line. Each common electrode block is connected to the driver chip through a touch wire. In the display stage, the driver chip inputs a common electrode signal to each common electrode to form an electric field with each pixel electrode. In the touch stage, the driver chip inputs touch signals to each common electrode at the same time or time-divisionally, and detects the touch position by detecting the self-capacitance change on each common electrode, that is, the touch electrode. Since each common electrode is arranged in a matrix, and each common electrode is connected to the driving chip through a corresponding touch trace, the self-capacitance change on each common electrode can be detected simultaneously, thereby realizing multi-touch detection.

In the array substrate in this embodiment, the drain, source, data lines, and touch wiring are arranged on the same layer, and the drain, source, data line, and touch wiring can be formed through a mask patterning process. The second metal layer of the wiring avoids separately setting the film layer where the touch wiring is located, and does not need to use a separate mask to make the touch wiring layer through the corresponding patterning process, which can simplify the manufacturing process of the array substrate and reduce the process flow The degree of complexity reduces the number of masks used, and the production cost is low.

Optionally, as shown in FIGS. 1-3 , the above-mentioned array substrate further includes: a first insulating layer 8 located between the first metal layer 2 and the active layer 3 . The first insulating layer is used to isolate the gate, the semiconductor layer and the second metal layer. The first insulating layer in the embodiment of the present invention does not need to use a patterning process of a mask to form a pattern. In the actual process, if necessary, the first insulating layer The corresponding pattern of the layer formation can also be patterned through an additional mask, and the above does not limit the protection scope of the present invention.

Wherein, since the first insulating layer of the array substrate in this embodiment is not provided with via holes, it is not necessary to carry out the hole engraving through the patterning process of the mask plate, thereby reducing one patterning process, which can simplify the manufacturing process of the array substrate and reduce the process cost. The complexity of the process reduces the number of masks used and the production cost is low.

Optionally, as shown in FIGS. 1-3 , the above-mentioned array substrate further includes: a second insulating layer 9 located between the common electrode layer 6 and the second metal layer 5 ; There are vias 91 . The second insulating layer is used to isolate the second metal layer and the common electrode layer. The touch traces of the second metal layer need to be connected to the common electrode block of the common electrode layer. The second insulating layer is provided with via holes, so the second insulating layer It is necessary to carry out the hole carving through the patterning process of the mask plate.

In the actual production process, various traces are often provided in the peripheral area surrounding the display area, such as gate drive circuit traces, signal traces connecting the driver chip and data lines, and touch traces and driver chips. the routing. When wiring in the non-display area, the first metal layer and the second metal layer are often switched and electrically connected to realize different signal transmission functions. Since the first insulating layer is not etched via holes after coating, at this time, if the first metal layer and the second metal layer are to be connected, it can be realized by adding a patterning process. It is also possible to jointly form a deep via hole through the first insulating layer 8 and the second insulating layer 9 in the step of patterning the via hole 91 on the second insulating layer 9. At this time, the exposed part of the deep via hole needs to be To realize the first metal layer for changing the line, form a shallow via hole on the same layer as the via hole 91 in the second insulating layer, so as to expose the second metal layer that needs to realize the line changing, deposit and deposit in the deep via hole and the shallow via hole The common electrode is connected to the connecting electrode on the same layer, and the first metal layer and the second metal layer are electrically connected through the connecting electrodes passing through the deep via hole and the shallow via hole. At this time, the patterning process is not increased, and the process time is not increased.

It should be noted that the material of the first insulating layer and/or the second insulating layer is any one of silicon nitride (SiNx) and silicon oxide (SiOx).

Optionally, the drain 51 is directly electrically connected to the pixel electrode 4 . Specifically, as shown in Figures 1-3, the pixel electrode is located above the film layer where the gate and gate line are located, and the pixel electrode and the drain are directly electrically connected by overlapping, without the need to set up additional via holes to The wire connection can simplify the manufacturing process of the array substrate and reduce the complexity of the process flow.

The implementation manner of the position of the touch wiring in the embodiment of the present invention will be described below through the relative positional relationship between the touch wiring and the data line.

Optionally, the touch wiring 7 is arranged adjacent to the data line 53 , and the touch wiring 7 is parallel to the data line 53 . Specifically, as shown in FIGS. 1-3 , the touch wires 7 and the data wires 53 are arranged adjacent to each other and parallel to each other, and they are located in the same film layer, which simplifies the complexity of the manufacturing process of the array substrate. And because the two are arranged in parallel, a light-shielding structure covering both the data lines and the touch wiring can be formed on the opposite substrate of the array substrate, so as to minimize the influence of the touch wiring on the display transmittance.

In the array substrate in the embodiment of the present invention, by arranging the drain, the source, the data line and the touch line on the same layer, it is avoided to separately set the film layer where the touch line is located, so there is no need to use a separate mask and pass the corresponding The patterning process is used to make the touch wiring layer, which reduces the patterning process of a mask plate; at the same time, by directly electrically connecting the pixel electrode and the drain without passing through the via hole, there is no need to pass through the patterning process of the mask plate. Carrying out hole engraving reduces one mask patterning process again; thus, the manufacturing process of the array substrate can be simplified, the complexity of the process flow can be reduced, the number of masks used can be reduced, and the production cost is low.

On the other hand, as shown in FIG. 4, based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing an array substrate, including:

Step 410 , forming a first metal layer on the substrate, the first metal layer including gates and gate lines.

Specifically, in step 410, the first metal layer is formed on the base substrate through the first mask patterning process, and then the first metal layer is covered with the first insulating layer. Since the first insulating layer does not need to be etched, there is no need to use In the mask patterning process, the first insulating layer is located between the first metal layer and the active layer to ensure electrical insulation between the gate and the source and drain.

Step 420, forming an active layer on the first metal layer.

Specifically, in step 420, an active layer is formed on the first metal layer through the second mask patterning process, and the active layer is a semiconductor layer, which is located on the first metal layer and also on the first insulating layer. The source layer selectively turns on or turns off the source and drain based on the magnitude of the corresponding gate voltage.

Step 430 , forming pixel electrodes on the film layer where the gates and gate lines are located.

Specifically, in step 430, a pixel electrode is formed on the film layer where the gate and the gate line are located through a third mask patterning process, and the pixel electrode is located on the first insulating layer. Step 440, forming a second metal layer and a touch wire on the active layer and the pixel electrode, wherein the second metal layer includes a drain, a source, and a data line, and the drain and the The pixel electrodes are electrically connected.

Specifically, in step 440, a second metal layer and touch wiring are formed on the active layer and the pixel electrode through the fourth mask patterning process, and the touch wiring is connected with the drain, source, and data lines. It is electrically insulated from the pixel electrode, and the touch trace is arranged on the same layer as the second metal layer, so a mask patterning process is omitted, and the drain electrode and the pixel electrode are directly electrically connected in an overlapping manner. In addition, the touch traces are arranged adjacent to the data lines, and the touch traces are parallel to the data lines.

Step 450 , forming a second insulating layer covering the second metal layer, and forming via holes on the second insulating layer.

Specifically, the film layer where the second metal layer and the touch traces are located is covered with a second insulating layer. In step 450, vias are etched on the second insulating layer through the fifth mask patterning process. The via holes Located above the touch trace.

Step 460, forming a common electrode layer on the second metal layer, wherein the common electrode layer includes a plurality of common electrode blocks arranged in an array, the common electrode blocks are multiplexed as touch electrodes, and the common electrode blocks are multiplexed as touch electrodes. The electrode block is electrically connected with the touch trace through the via hole. Specifically, a second insulating layer is disposed between the common electrode layer and the second metal layer, and the common electrode block is electrically connected to the touch wiring through a via hole in the second insulating layer.

On the basis of the above-mentioned method for preparing the array substrate, the method for preparing the array substrate will be described in detail below. Specifically as shown in Figure 5, the detailed steps of the above preparation method are as follows:

Step 1, forming a first metal layer 2 including gates and gate lines on the base substrate 1;

Wherein, through the first mask patterning process, the first metal layer 2 including the gate and the gate line is formed on the base substrate 1, and the gate and the gate line are electrically connected. The process of forming the first metal layer can be to first deposit a layer of the first metal material layer on the base substrate, the deposition method of the first metal material layer can be methods such as sputtering, which can be compared with the method of depositing the metal layer in the prior art Same, no more details here. Then coat a photoresist on the first metal material layer, and use a first mask to expose the photoresist. After the exposure is finished, a developing process is carried out. During the developing process, the photoresist in the exposed part is washed away, and the photoresist in the unexposed part remains on the first metal material layer. After developing, perform wet etching on the exposed first metal material layer, and the unetched part is the part protected by the photoresist, and the first metal layer is patterned on this part. Finally, the photoresist is stripped, and the patterning process of the first metal layer is completed.

Step 2, forming a first insulating layer 8 on the first metal layer 2 where the gate and gate lines are located;

Wherein, the first insulating layer 8 is not provided with a via hole, so there is no need to perform hole engraving through a mask patterning process.

Step 3, forming an active layer 3 on the first insulating layer 8;

Wherein, the active layer 3 is formed on the first insulating layer 8 through the second mask patterning process. Similarly, the formation of the active layer also needs to go through processes such as coating a semiconductor material layer, such as photoresist, exposing and developing the photoresist, etching, and stripping the photoresist. Different from forming the first metal layer, the etching of the semiconductor material layer generally adopts dry etching. The etching process and etching materials are the same as those in the prior art, and will not be repeated here.

Step 4, forming a pixel electrode 4 on the first metal layer 2 where the gate and the gate line are located;

Wherein, through the third mask patterning process, the pixel electrodes 4 are formed on the first metal layer 2 where the gates and gate lines are located. Both the pixel electrode 4 and the active layer 3 are located above the first insulating layer 8 , and the formation process of the pixel electrode is similar to the formation process of the first metal layer, which will not be repeated here.

Step 5, forming a second metal layer 5 and a touch wire 7 on the active layer 3 and the pixel electrode 4, the second metal layer 5 includes a drain 51, a source 52 and a data line;

Wherein, through the fourth mask patterning process, the second metal layer 5 and the touch wire 7 are formed on the active layer 3 and the pixel electrode 4, and the second metal layer 5 includes the drain electrode 51, the source electrode 52 and the data line, the touch line is arranged adjacent to the data line, and the touch line is parallel to the data line, and the second metal layer 5 and the touch line 7 are set on the same layer, which can reduce the number of times a mask is used; The electrodes 51 and the pixel electrodes 4 are directly electrically connected by overlapping, thereby reducing the number of times of using a mask. The formation process of the second metal layer and the touch wiring is similar to the formation process of the first metal layer, and will not be repeated here.

Optionally, the touch wiring 7 is arranged adjacent to the data line 53 , and the touch wiring 7 is parallel to the data line 53 . Specifically, as shown in FIGS. 1-3 , the touch wires 7 and the data wires 53 are arranged adjacent to each other and parallel to each other, and they are located in the same film layer, which simplifies the complexity of the manufacturing process of the array substrate. And because the two are arranged in parallel, a light-shielding structure covering both the data lines and the touch wiring can be formed on the opposite substrate of the array substrate, so as to minimize the influence of the touch wiring on the display transmittance. Step 6, forming a second insulating layer 9 including a via hole 91 leaking out of the touch wiring 7 on the second metal layer 5 and the touch wiring 7;

Wherein, through the fifth mask patterning process, a via hole 91 for leaking the touch trace 7 is formed in the second insulating layer 9 . The method for forming the second insulating layer 9 is the same as the method for forming the active layer, and will not be repeated here.

In the actual production process, various traces are often provided in the peripheral area surrounding the display area, such as gate drive circuit traces, signal traces connecting the driver chip and data lines, and touch traces and driver chips. the routing. When wiring in the non-display area, the first metal layer and the second metal layer are often switched and electrically connected to realize different signal transmission functions. Since the first insulating layer is not etched via holes after coating, at this time, if the first metal layer and the second metal layer are to be connected, it can be realized by adding a patterning process. It is also possible to jointly form a deep via hole through the first insulating layer 8 and the second insulating layer 9 in the step of patterning the via hole 91 on the second insulating layer 9. At this time, the exposed part of the deep via hole needs to be To realize the first metal layer for changing the line, form a shallow via hole on the same layer as the via hole 91 in the second insulating layer, so as to expose the second metal layer that needs to realize the line changing, deposit and deposit in the deep via hole and the shallow via hole The common electrode is connected to the connecting electrode on the same layer, and the first metal layer and the second metal layer are electrically connected through the connecting electrodes passing through the deep via hole and the shallow via hole. At this time, the patterning process is not increased, and the process time is not increased.

Step 7, forming a common electrode layer 6 on the second metal layer 5;

Among them, through the sixth mask patterning process, a common electrode layer 6 is formed on the second metal layer 5. The common electrode layer includes a plurality of common electrode blocks arranged in an array, and the common electrode blocks are multiplexed as touch electrodes. The common electrode block of the common electrode layer 6 is electrically connected to the touch wire 7 through the via hole 91 .

To sum up, in the method for preparing the array substrate in the embodiment of the present invention, only 6 mask patterning processes are needed, which reduces the number of mask patterning processes compared with 8-10 mask patterning processes in the prior art preparation method. The number of stencils used simplifies the manufacturing process of the array substrate and reduces the complexity of the process flow.

As shown in FIG. 6 , an embodiment of the present invention also provides a liquid crystal display panel, including the above-mentioned array substrate 610 , a color filter substrate 620 and a liquid crystal layer 630 .

Wherein, the specific structure and principle of the array substrate 610 are the same as those of the above-mentioned embodiments, and will not be repeated here.

In the liquid crystal display panel in this embodiment, the drain electrode, the source electrode, the data line and the touch wiring line of the array substrate are arranged on the same layer in the liquid crystal display panel, so as to avoid separately setting the film layer where the touch wiring line is located; and, the pixel The electrode and the drain are directly electrically connected without passing through holes, so that there is no need to go through the patterning process of the mask plate for hole engraving; thus eliminating the need for two patterning processes of the mask plate, thus simplifying the fabrication of the array substrate process, reduce the complexity of the process, reduce the number of masks used, and reduce production costs.

As shown in FIG. 7 , an embodiment of the present invention further provides a display device, including the above-mentioned liquid crystal display panel 700 .

Wherein, the specific structure and principle of the liquid crystal display panel 700 are the same as those of the above-mentioned embodiments, and will not be repeated here. The display device may be any electronic device with a liquid crystal display function such as a touch screen, a mobile phone, a tablet computer, a notebook computer, an electronic paper book, or a television.

In the display device in this embodiment, the drain electrode, the source electrode, the data line and the touch wiring line of the array substrate are arranged on the same layer in the liquid crystal display panel, so as to avoid separately setting the film layer where the touch wiring line is located; and the pixel electrode It is directly electrically connected to the drain without passing through holes, so that there is no need to go through the patterning process of the mask plate to carry out the hole engraving; thus eliminating the need for two patterning processes of the mask plate, so the manufacturing process of the array substrate can be simplified , reduce the complexity of the process flow, reduce the number of masks used, and reduce the production cost.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.

Claims (12)

1. a kind of array base palte, it is characterised in that including：

Underlay substrate；

The first metal layer on the underlay substrate, the first metal layer includes grid and grid line；

Active layer on the first metal layer；

Pixel electrode in film layer where the grid and grid line；

Second metal layer on the active layer and the pixel electrode, the second metal layer include drain electrode, source electrode and Data wire, wherein, the drain electrode is electrically connected with the pixel electrode；

Common electrode layer in the second metal layer, the common electrode layer includes multiple public affairs set with array way Common electrode block, the public electrode block is multiplexed with touch control electrode；The array base palte also includes：

Touch-control cabling, positioned at the second metal layer；The touch-control cabling and the drain electrode, source electrode, data wire and pixel electrode It is electrically insulated, and is electrically connected with the public electrode block of the common electrode layer by via.

2. array base palte as claimed in claim 1, it is characterised in that the array base palte also includes：

First insulating barrier, between the first metal layer and the active layer.

3. array base palte as claimed in claim 1, it is characterised in that the array base palte also includes：

Second insulating barrier, between the common electrode layer and the second metal layer；Second insulating barrier was provided with Hole.

4. array base palte as claimed in claim 1, it is characterised in that the drain electrode directly electrically connects with the pixel electrode Connect.

5. array base palte as claimed in claim 1, it is characterised in that the touch-control cabling is disposed adjacent with the data wire, And the touch-control cabling is parallel with the data wire.

6. a kind of display panel, it is characterised in that including the array base palte as described in any one of Claims 1 to 5.

7. a kind of display device, it is characterised in that including display panel as claimed in claim 6.

8. a kind of preparation method of array base palte as claimed in claim 1, it is characterised in that including：

The first metal layer is formed on underlay substrate, the first metal layer includes grid and grid line；

Active layer is formed on the first metal layer；

Pixel electrode is formed in film layer where the grid and grid line；

Second metal layer and touch-control cabling are formed on the active layer and the pixel electrode, wherein, the second metal layer Including drain electrode, source electrode and data wire, the drain electrode is electrically connected with the pixel electrode；

The second insulating barrier of the covering second metal layer is formed, via is formed on second insulating barrier；

Common electrode layer is formed in the second metal layer, wherein, the common electrode layer includes that multiple is set with array way The public electrode block put, the public electrode block is multiplexed with touch control electrode, the public electrode block by the via with it is described Touch-control cabling is electrically connected with.

9. the preparation method of array base palte as claimed in claim 8, it is characterised in that methods described also includes：

The first insulating barrier is formed between the first metal layer and the active layer.

10. the preparation method of array base palte as claimed in claim 8, it is characterised in that methods described also includes：

The second insulating barrier, and the shape on second insulating barrier are formed between the common electrode layer and the second metal layer Into via.

The preparation method of 11. array base paltes as claimed in claim 8, it is characterised in that the drain electrode and the pixel electrode Directly it is electrically connected with.

The preparation method of 12. array base paltes as claimed in claim 8, it is characterised in that the touch-control cabling and the data Line is disposed adjacent, and the touch-control cabling is parallel with the data wire.