CN106875913A - Shift register cell and its driving method, gate driving circuit - Google Patents
Shift register cell and its driving method, gate driving circuit Download PDFInfo
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- CN106875913A CN106875913A CN201710266015.6A CN201710266015A CN106875913A CN 106875913 A CN106875913 A CN 106875913A CN 201710266015 A CN201710266015 A CN 201710266015A CN 106875913 A CN106875913 A CN 106875913A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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Abstract
This disclosure relates to a kind of shift register cell and its driving method, gate driving circuit.The shift register cell includes：Input module, transmits to pull-up node for responding input signal with by the first power supply signal；Pull-up module, for responding the first reference signal with by the first reference signal transmission to pull-down node, and response pull-up node voltage signal with by the second reference signal transmission to pull-down node；Drop-down module, pull-up node and signal output part are transmitted separately to for responding the voltage signal of pull-down node with by the second reference signal；Reseting module, for responding reset signal with by second source signal transmission to pull-up node；Output module, for responding the voltage signal of pull-up node with by clock signal transmission to signal output part；Compensating module, the output signal for response signal output end applies to signal output part with by thermal compensation signal.The disclosure can reduce the signal delay of shift register cell, so as to improve raster data model effect.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a driving method thereof, and a gate driving circuit.
Background
With the development of optical technology and semiconductor technology, flat panel displays represented by Liquid Crystal Displays (LCDs) have the characteristics of lightness, thinness, low energy consumption, fast response speed, good color purity, high contrast ratio and the like, and occupy a leading position in the Display field. Display devices have been developed to have high integration and low cost in recent years. By taking a Gate Driver on Array (GOA) technology as a representative, and integrating a Gate driving circuit in a peripheral area of an Array substrate by using the GOA technology, a narrow frame design can be realized, and at the same time, a module process yield can be effectively improved, a product yield can be improved, and a cost can be saved.
The output signal of the GOA circuit is a key factor for achieving normal display. Ideally, the output signal of the GOA circuit should be a square wave signal, i.e., the rising time Tr (the time when the output signal increases from 10% to 90%) and the falling time Tf (the time when the output signal decreases from 90% to 10%) of the output waveform are both 0. Based on the cascade structure of the GOA circuits, the input signals of the GOA units of the other stages are all output signals of the higher-stage GOA unit, except that the input signal of the first-stage GOA unit is a start signal. Referring to the waveform diagram of the output signal shown in fig. 1, since the input signal flows through a long trace and a large number of TFTs during the step-by-step downward transmission process, and the RC delay inevitably causes gradual attenuation of the input signal, the closer to the end of the GOA circuit, the more serious the signal delay, the larger the waveform delay of the output signal, which is represented by the gradual slope of the rising edge and the larger time Tr of the rising edge. Therefore, when the signal period is constant, the pixels are charged only when the output signal reaches 90% of the peak voltage, so that the signal delay directly causes the reduction of the pixel charging time and the insufficient pixel charging, thereby causing the abnormality of the displayed image.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
An object of the present disclosure is to provide a shift register unit, a driving method thereof, and a gate driving circuit, thereby overcoming, at least to some extent, one or more of the problems due to the limitations and disadvantages of the related art.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.
According to an aspect of the present disclosure, there is provided a shift register unit including:
the input module is connected with the signal input end, the first power supply signal end and the pull-up node and used for responding to an input signal so as to transmit the first power supply signal to the pull-up node;
the pull-up module is connected with a first reference signal terminal, the pull-up node, a pull-down node and a second reference signal terminal, and is used for responding to a first reference signal to transmit the first reference signal to the pull-down node and responding to a voltage signal of the pull-up node to transmit a second reference signal to the pull-down node;
the pull-down module is connected with the pull-down node, the second reference signal terminal, the pull-up node and the signal output terminal, and is used for responding to a voltage signal of the pull-down node so as to transmit the second reference signal to the pull-up node and the signal output terminal respectively;
the reset module is connected with a reset signal end, a second power supply signal end and the pull-up node and used for responding to a reset signal to transmit a second power supply signal to the pull-up node;
the output module is connected with the pull-up node, the clock signal end and the signal output end and used for responding to a voltage signal of the pull-up node so as to transmit a clock signal to the signal output end;
and the compensation module is connected with a compensation signal terminal and the signal output terminal and is used for responding to the output signal of the signal output terminal so as to apply a compensation signal to the signal output terminal.
In an exemplary embodiment of the present disclosure, the input module includes:
a first switch element, a control end of which is connected with the signal input end, a first end of which is connected with the first power signal end, and a second end of which is connected with the pull-up node;
the reset module includes:
a second switch element, a control end of which is connected with the reset signal end, a first end of which is connected with the second power supply signal end, and a second end of which is connected with the pull-up node;
the output module includes:
a third switching element having a control terminal connected to the pull-up node, a first terminal connected to the clock signal terminal, and a second terminal connected to the signal output terminal; and the number of the first and second groups,
and the storage capacitor is connected between the pull-up node and the signal output end.
In an exemplary embodiment of the present disclosure, the compensation module includes:
and the control end of the fourth switching element is connected with the signal output end, the first end of the fourth switching element is connected with the compensation signal end, and the second end of the fourth switching element is connected with the signal output end.
In an exemplary embodiment of the present disclosure, the pull-up module includes:
a fifth switching element having a control terminal and a first terminal connected to the first reference signal terminal, and a second terminal connected to a pull-down control node;
a sixth switching element having a control terminal connected to the pull-down control node, a first terminal connected to the first reference signal terminal, and a second terminal connected to the pull-down node;
a seventh switching element, a control end of which is connected to the pull-up node, a first end of which is connected to the second reference signal end, and a second end of which is connected to the pull-down control node;
and the control end of the eighth switching element is connected with the pull-up node, the first end of the eighth switching element is connected with the second reference signal end, and the second end of the eighth switching element is connected with the pull-down node.
In an exemplary embodiment of the present disclosure, the pull-down module includes:
a ninth switching element having a control terminal connected to the pull-down node, a first terminal connected to the second reference signal terminal, and a second terminal connected to the pull-up node;
and a tenth switching element having a control terminal connected to the pull-down node, a first terminal connected to the second reference signal terminal, and a second terminal connected to the signal output terminal.
In an exemplary embodiment of the present disclosure, all of the switching elements are P-type transistors or are N-type transistors.
In an exemplary embodiment of the present disclosure, the first power signal and the first reference signal are both dc high level signals, and the second power signal and the second reference signal are both dc low level signals.
According to an aspect of the present disclosure, a gate driving circuit is provided, which includes a plurality of cascaded shift register units as described above; wherein,
the signal output end of the M-1 stage shift register unit is connected with the signal input end of the M stage shift register unit;
and the signal output end of the M +1 th stage shift register unit is connected with the reset signal end of the M stage shift register unit.
In an exemplary embodiment of the present disclosure, a scanning direction of the gate driving circuit is opposite to a compensation direction of the compensation signal.
According to an aspect of the present disclosure, there is provided a driving method of a shift register unit, including:
in a charging stage, an input module transmits a first power supply signal to a pull-up node under the control of an input signal, and a pull-up module transmits a second reference signal to the pull-down node under the control of a voltage signal of the pull-up node;
in an output/compensation stage, an output module transmits a clock signal to a signal output end under the control of a voltage signal of the pull-up node, a compensation module transmits a compensation signal to the signal output end under the control of a voltage signal of the signal output end, and the signal output end outputs a grid scanning signal;
in a reset stage, the reset module transmits a second power signal to the pull-up node under the control of a reset signal, the pull-up module transmits a first reference signal to the pull-down node under the control of a first reference signal, and the pull-down module transmits a second reference signal to the pull-up node and the signal output end respectively under the control of a voltage signal of the pull-down node.
According to the shift register unit, the driving method thereof and the gate driving circuit provided by the exemplary embodiment of the disclosure, a compensation module is added on the basis of a traditional shift register unit, and the compensation module is arranged at a signal output end. Therefore, when the shift register unit is in the signal output stage, the compensation signal can be directly applied to the signal output end to synchronously compensate the output signal. The application of the compensation signal can reduce the rise time of the output signal on one hand, so that the delay of the output signal is reduced, and the charging time of the pixel is ensured, and can improve the voltage peak value of the output signal and reduce the attenuation of the output signal on the other hand, so that the sufficient charging of the pixel is ensured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 schematically shows a waveform diagram of an output signal in the prior art;
FIG. 2 schematically illustrates a circuit configuration diagram of a shift register unit in an exemplary embodiment of the present disclosure;
FIG. 3 schematically illustrates a timing signal diagram of a shift register cell in an exemplary embodiment of the present disclosure;
fig. 4 schematically illustrates a cascade structure of the gate driving circuit in an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The present exemplary embodiment proposes a shift register unit for providing a gate driving signal; as shown in fig. 2, the shift register unit may include:
an Input module 10, connected to the signal Input terminal, the first power signal terminal VDD, and the pull-up node PU, for responding to the Input signal to transmit the first power signal to the pull-up node PU;
a pull-up module 20 connected to the first reference signal terminal VGH, the pull-up node PU, the pull-down node PD, and the second reference signal terminal VGL, and configured to respond to the first reference signal to transmit the first reference signal to the pull-down node PD and respond to the voltage signal of the pull-up node PU to transmit the second reference signal to the pull-down node PD;
the pull-down module 30 is connected to the pull-down node PD, the second reference signal terminal VGL, the pull-up node PU, and the signal Output terminal Output, and configured to respond to a voltage signal of the pull-down node PD to transmit a second reference signal to the pull-up node PU and the signal Output terminal Output, respectively;
the Reset module 40 is connected to the Reset signal terminal Reset, the second power signal terminal VSS, and the pull-up node PU, and configured to respond to the Reset signal to transmit the second power signal to the pull-up node PU;
an Output module 50, connected to the pull-up node PU, the clock signal terminal CLK, and the signal Output terminal Output, for responding to the voltage signal of the pull-up node PU to transmit the clock signal to the signal Output terminal Output;
and the compensation module 60 is connected with the compensation signal terminal VC and the signal Output terminal Output and is used for responding to the Output signal of the signal Output terminal Output so as to apply the compensation signal to the signal Output terminal Output.
It should be noted that: the Input signal is a voltage signal of a signal Input end Input, the first power signal is a voltage signal of a first power signal end VDD, the Reset signal is a voltage signal of a Reset signal end Reset, the second power signal is a voltage signal of a second power signal end VSS, the clock signal is a voltage signal of a clock signal end CLK, the compensation signal is a voltage signal of a compensation signal end VC, the first reference signal is a voltage signal of a first reference signal end VGH, and the second reference signal is a voltage signal of a second reference signal end VGL.
The shift register unit provided by the exemplary embodiment of the present disclosure adds a compensation module 60 on the basis of a conventional shift register unit, and the compensation module 60 is disposed at the signal Output terminal Output. Therefore, when the shift register unit is in the signal Output stage, the compensation signal can be directly applied to the signal Output terminal Output to perform synchronous compensation on the Output signal. On one hand, the application of the compensation signal can reduce the rising time of the output signal, so that the delay of the output signal is reduced, the charging time of the pixel is ensured, meanwhile, the peak voltage of the output signal can be improved, the attenuation of the output signal is reduced, and the full charging of the pixel is ensured; on the other hand, since the compensation module 60 is controlled by the Output signal of the signal Output terminal, the compensation is stopped when the Output of the shift register unit is turned off, thereby avoiding the phenomenon of pixel overcharge or current leakage.
In this example embodiment, the first power signal of the first power signal terminal VDD and the first reference signal of the first reference signal terminal VGH may both be dc high-level signals, and the second power signal of the second power signal terminal VSS and the second reference signal of the second reference signal terminal VGL may both be dc low-level signals.
Wherein, the first power signal is used for charging the pull-up node PU, the second power signal is used for discharging the pull-up node PU, the first reference signal is used for providing a high level signal for the pull-up module 20, and the second reference signal is used for providing a low level signal for the pull-up module 20 and the pull-down module 30.
It should be noted that: the first power signal and the first reference signal may be connected to the same high-level signal terminal or connected to different high-level signal terminals, and the second power signal and the second reference signal may be connected to the same low-level signal terminal or connected to different low-level signal terminals, as long as the effect of each functional module can be ensured, and the connection manner of each power signal terminal and each reference signal terminal is not specifically limited in this example embodiment.
The structure of the shift register unit in the present exemplary embodiment will be described in detail below with reference to fig. 2.
The input module 10 may include:
the first switch element M1 has a control terminal connected to the signal Input terminal Input, a first terminal connected to the first power signal terminal VDD, and a second terminal connected to the pull-up node PU.
The reset module 40 may include:
the second switching element M2 has a control terminal connected to the Reset signal terminal Reset, a first terminal connected to the second power signal terminal VSS, and a second terminal connected to the pull-up node PU.
The output module 50 may include:
a third switching element M3, a control end of which is connected to the pull-up node PU, a first end of which is connected to the clock signal terminal CLK, and a second end of which is connected to the signal Output terminal Output; and the number of the first and second groups,
and the storage capacitor C is connected between the pull-up node PU and the signal Output end Output.
The compensation module 60 may include:
a control end of the fourth switching element M4 is connected to the signal Output end Output, a first end is connected to the compensation signal end VC, and a second end is connected to the signal Output end Output.
The drawing-up module 20 may include:
a fifth switching element M5 having a control terminal and a first terminal connected to the first reference signal terminal VGH, and a second terminal connected to the pull-down control node PD-CN;
a sixth switching element M6, having a control terminal connected to the pull-down control node PD-CN, a first terminal connected to the first reference signal terminal VGH, and a second terminal connected to the pull-down node PD;
a seventh switching element M7, a control end of which is connected to the pull-up node PU, a first end of which is connected to the second reference signal end VGL, and a second end of which is connected to the pull-down control node PD-CN;
the eighth switching element M8 has a control terminal connected to the pull-up node PU, a first terminal connected to the second reference signal terminal VGL, and a second terminal connected to the pull-down node PD.
The pull-down module 30 may include:
a ninth switching element M9, having a control terminal connected to the pull-down node PD, a first terminal connected to the second reference signal terminal VGL, and a second terminal connected to the pull-up node PU;
a control end of the tenth switching element M10 is connected to the pull-down node PD, a first end thereof is connected to the second reference signal terminal VGL, and a second end thereof is connected to the signal Output terminal Output.
In this example embodiment, all of the switching elements may be P-type transistors or N-type transistors. Specifically, all the switching elements may be MOS (Metal Oxide Semiconductor, Metal-Oxide Semiconductor field effect transistor) field effect transistors, and specifically, P-type MOS transistors or N-type MOS transistors may be used. It should be noted that: the level signals of the respective signal terminals require a corresponding adjustment change for different transistor types.
The operation of the shift register unit of this embodiment will be specifically described with reference to fig. 2 and 3, taking all the switching elements as NMOS as an example. The first power signal and the first reference signal are high-level signals, and the second power signal and the second reference signal are low-level signals.
A charging stage: when the input signal is at a high level, the first switch element M1 is turned on to transmit the first power signal to the pull-up node PU and charge the storage capacitor C, and the pull-up node PU is at a high level; meanwhile, under the action of the first reference signal, the fifth switching element M5 is turned on to transmit the first reference signal to the pull-down control node PD-CN, so that the sixth switching element M6 is turned on to transmit the first reference signal to the pull-down node PD; however, under the high level action of the pull-up node PU, the seventh switching element M7 and the eighth switching element M8 are turned on to transmit the second reference signal to the pull-down control node PD-CN and the pull-down node PD, respectively, thereby pulling down the levels of the pull-down control node PD-CN and the pull-down node PD.
Output/compensation phase: the clock signal is at a high level, the pull-up node PU is kept at the high level under the action of the storage capacitor C, the third switching element M3 is turned on and the pull-up node PU has a higher potential through the bootstrap action of the storage capacitor C, and then the third switching element M3 is sufficiently turned on to transmit the clock signal to the signal Output terminal Output; the compensation signal is at a high level, and under the action of the high level of the signal Output terminal Output, the fourth switching element M4 is turned on to transmit the compensation signal to the signal Output terminal Output to compensate the Output signal, so as to realize the signal Output of the shift register unit at this stage.
A reset stage: when the reset signal is at a high level, the second switching element M2 is turned on to discharge the storage capacitor C by the second power signal, and as the voltage of the pull-up node PU decreases as the discharge progresses, the seventh switching element M7 and the eighth switching element M8 are turned off; under the action of the first reference signal, the fifth switching element M5 is turned on to transmit the first reference signal to the pull-down control node PD-CN, and the sixth switching element M6 is turned on to transmit the first reference signal to the pull-down node PD, so as to pull up the level of the pull-down node PD; under the high level action of the pull-down node PD, the ninth switching element M9 and the tenth switching element M10 are turned on to transmit the second reference signal to the pull-up node PU and the signal Output terminal Output, respectively, so as to reset the pull-up node PU and the signal Output terminal Output.
Based on the above working process, in the signal Output stage of the shift register unit, the compensation signal is applied to the signal Output terminal Output to implement synchronous compensation on the Output signal, so that the delay and attenuation of the Output signal can be reduced. Referring to fig. 1, the compensation signal acts as a compensation signal applied to the signal Output terminal Output at the beginning of the rising edge time Tr of the Output waveform, so that the actually Output voltage signal can be rapidly increased from 10% to 90% of the peak voltage Vmax, and the rising edge time Tr is greatly shortened, thereby ensuring the charging time of the pixel.
It should be noted that: the compensation signal is used for compensating the Output signal of the signal Output end, the voltage value of the compensation signal is set to be greater than or equal to 90% of the peak voltage, and the fourth transistor is guaranteed not to be broken down.
The present exemplary embodiment further provides a gate driving circuit, as shown in fig. 4, the gate driving circuit may include a plurality of cascaded shift register units; the signal Output end Output of the M-1 stage shift register unit is connected with the signal Input end Input of the M stage shift register unit; and the signal Output end Output of the M +1 th stage shift register unit is connected with the Reset signal end Reset of the M +1 th stage shift register unit.
It should be noted that: the scanning manner of the gate driving circuit may adopt forward scanning or direction scanning, which is not specifically limited in this embodiment.
In addition, in the cascade structure of the gate driving circuit, the scanning direction of the gate driving circuit is preferably opposite to the compensation direction of the compensation signal, considering that the attenuation of the output signal near the front end is small and the attenuation of the output signal near the rear end is large. That is, when the gate driving circuit adopts forward scanning, the direction of the compensation signal is from bottom to top; when the grid drive circuit adopts reverse scanning, the direction of the compensation signal is from top to bottom.
Based on the compensation mode, the attenuation of the output signal is smaller and the attenuation of the compensation signal is larger at the front end of the gate drive circuit, and the attenuation of the output signal is larger and the attenuation of the compensation signal is smaller at the tail end of the gate drive circuit, so that the output signals of all stages of the gate drive circuit can be balanced, the gate drive capability is improved, and the display effect is ensured.
It should be noted that: the specific details of each module unit in the gate driving circuit have been described in detail in the corresponding shift register unit, and therefore are not described herein again.
The present example embodiment also provides a display panel including a display area and a peripheral area. The gate driving circuit may be disposed in a peripheral region of the display panel. The display area of the display panel may include a plurality of gate lines and a plurality of data lines which are staggered horizontally and vertically, and a plurality of pixel units defined by adjacent gate lines and adjacent data lines: the gate lines are used for transmitting scanning signals provided by the gate driving circuit, and the data lines are used for transmitting data signals provided by the source driving circuit.
In the exemplary embodiment, the gate driving circuit is integrated on the periphery of the display panel by using the GOA technology, so that the manufacturing cost of the display panel can be effectively reduced and the process yield of the display module can be improved while the narrow-frame panel is designed.
In this exemplary embodiment, the display panel may be specifically an LCD display panel, an OLED display panel, a PLED (Polymer Light-Emitting Diode) display panel, a PDP (Plasma display panel), and the like, and the application of the display panel is not particularly limited herein.
The present exemplary embodiment also provides a display device including the display panel described above. The display device may include any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. A shift register cell, comprising:
the input module is connected with the signal input end, the first power supply signal end and the pull-up node and used for responding to an input signal so as to transmit the first power supply signal to the pull-up node;
the pull-up module is connected with a first reference signal terminal, the pull-up node, a pull-down node and a second reference signal terminal, and is used for responding to a first reference signal to transmit the first reference signal to the pull-down node and responding to a voltage signal of the pull-up node to transmit a second reference signal to the pull-down node;
the pull-down module is connected with the pull-down node, the second reference signal terminal, the pull-up node and the signal output terminal, and is used for responding to a voltage signal of the pull-down node so as to transmit the second reference signal to the pull-up node and the signal output terminal respectively;
the reset module is connected with a reset signal end, a second power supply signal end and the pull-up node and used for responding to a reset signal to transmit a second power supply signal to the pull-up node;
the output module is connected with the pull-up node, the clock signal end and the signal output end and used for responding to a voltage signal of the pull-up node so as to transmit a clock signal to the signal output end;
and the compensation module is connected with a compensation signal terminal and the signal output terminal and is used for responding to the output signal of the signal output terminal so as to apply a compensation signal to the signal output terminal.
2. The shift register cell of claim 1, wherein the input module comprises:
a first switch element, a control end of which is connected with the signal input end, a first end of which is connected with the first power signal end, and a second end of which is connected with the pull-up node;
the reset module includes:
a second switch element, a control end of which is connected with the reset signal end, a first end of which is connected with the second power supply signal end, and a second end of which is connected with the pull-up node;
the output module includes:
a third switching element having a control terminal connected to the pull-up node, a first terminal connected to the clock signal terminal, and a second terminal connected to the signal output terminal; and the number of the first and second groups,
and the storage capacitor is connected between the pull-up node and the signal output end.
3. The shift register cell of claim 1, wherein the compensation module comprises:
and the control end of the fourth switching element is connected with the signal output end, the first end of the fourth switching element is connected with the compensation signal end, and the second end of the fourth switching element is connected with the signal output end.
4. The shift register cell of claim 1, wherein the pull-up module comprises:
a fifth switching element having a control terminal and a first terminal connected to the first reference signal terminal, and a second terminal connected to a pull-down control node;
a sixth switching element having a control terminal connected to the pull-down control node, a first terminal connected to the first reference signal terminal, and a second terminal connected to the pull-down node;
a seventh switching element, a control end of which is connected to the pull-up node, a first end of which is connected to the second reference signal end, and a second end of which is connected to the pull-down control node;
and the control end of the eighth switching element is connected with the pull-up node, the first end of the eighth switching element is connected with the second reference signal end, and the second end of the eighth switching element is connected with the pull-down node.
5. The shift register cell of claim 1, wherein the pull-down module comprises:
a ninth switching element having a control terminal connected to the pull-down node, a first terminal connected to the second reference signal terminal, and a second terminal connected to the pull-up node;
and a tenth switching element having a control terminal connected to the pull-down node, a first terminal connected to the second reference signal terminal, and a second terminal connected to the signal output terminal.
6. The shift register cell according to any one of claims 2 to 5, wherein all of the switching elements are P-type transistors or N-type transistors.
7. The shift register cell of any one of claims 1-5, wherein the first power signal and the first reference signal are both DC high level signals, and the second power signal and the second reference signal are both DC low level signals.
8. A gate drive circuit comprising a plurality of cascaded shift register cells of any one of claims 1-7; wherein,
the signal output end of the M-1 stage shift register unit is connected with the signal input end of the M stage shift register unit;
and the signal output end of the M +1 th stage shift register unit is connected with the reset signal end of the M stage shift register unit.
9. The gate driving circuit according to claim 8, wherein a scanning direction of the gate driving circuit is opposite to a compensation direction of the compensation signal.
10. A method for driving a shift register unit, comprising:
in a charging stage, an input module transmits a first power supply signal to a pull-up node under the control of an input signal, and a pull-up module transmits a second reference signal to the pull-down node under the control of a voltage signal of the pull-up node;
in an output/compensation stage, an output module transmits a clock signal to a signal output end under the control of a voltage signal of the pull-up node, a compensation module transmits a compensation signal to the signal output end under the control of a voltage signal of the signal output end, and the signal output end outputs a grid scanning signal;
in a reset stage, the reset module transmits a second power signal to the pull-up node under the control of a reset signal, the pull-up module transmits a first reference signal to the pull-down node under the control of a first reference signal, and the pull-down module transmits a second reference signal to the pull-up node and the signal output end respectively under the control of a voltage signal of the pull-down node.
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Application publication date: 20170620 |