CN106874231B

CN106874231B - Bus retainer and electronic device

Info

Publication number: CN106874231B
Application number: CN201510926845.8A
Authority: CN
Inventors: 卢斌; 王俊; 刘毅; 马莹; 程惠娟
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2015-12-14
Filing date: 2015-12-14
Publication date: 2021-04-23
Anticipated expiration: 2035-12-14
Also published as: CN106874231A

Abstract

The invention provides a bus holder and an electronic device, the bus holder includes: a first pull-up circuit including a first switch and a second switch connected in series; a first pull-down circuit including a third switch and a fourth switch connected in series; and a fifth switch connected in series with the third switch and a sixth switch connected in series with the fourth switch, wherein a source of the fifth switch is connected with a source of the first switch and a source of the sixth switch is connected with a source of the fourth switch. The bus keeper uses fewer MOSFETs to obtain more functions, can perform bus keeping verification, utilizes pull-up and pull-down control pins to switch the bus keeper, can be applied to I/O circuits and can be mass produced.

Description

Bus retainer and electronic device

Technical Field

The invention relates to the field of electronic circuits, in particular to a bus retainer and an electronic device.

Background

The bus keeper is a positive feedback from the input port of the output signal through an inverter, which forms a bi-stable circuit (latched). The bus keeper is used to prevent the following situations: when connected to a tri-state network, the complementary metal oxide semiconductor CMOS gate input obtains a floating value. In addition, both transistors in the gate should be turned on, whereby the power supply and ground will be short-circuited, which will destroy the CMOS gate. The bus keeper prevents this by pulling the input up to the last valid logic level (0 or 1) on the network. Such circuits are typically arranged together in parallel with a tri-state network. Fig. 1 shows a bus keeper of the prior art. As shown in fig. 1, which shows a simplified schematic diagram, Q1Q2 and Q3Q4 are two inverters. Point 1 is the input signal and

points

4, 5 are the output signals, which are returned to the input through

points

2, 3.

Fig. 2 to 3 show schematic views of another bus retainer of the prior art. As shown in fig. 2, the bus hold circuit is formed by connecting two inverters (I1 and I2) in series, and is connected to a series of drivers and corresponding logic circuits through a bus. As shown in fig. 3, the internal structure of the bus hold circuit is specifically shown, which includes a pull-up circuit composed of

switches

15 and 17 and a pull-down circuit composed of

switches

11 and 13.

This bus keeper structure can be used to prevent shorting power and ground (which would damage the CMOS gates by pulling the input to the last valid logic level (0 or 1) on the network). This architecture has only bus hold functionality and cannot be directly plugged into an I/O design. The I/O design expects to obtain four states through additional control pins and use one of the states as a bus hold function.

Therefore, there is a need to provide a bus retainer to at least partially address the above mentioned problems.

Disclosure of Invention

In view of the deficiencies of the prior art, the present invention provides a bus keeper in which more functions are obtained using fewer MOSFETs than in the conventional method, bus retention verification can be performed, the bus keeper is switched using pull-up and pull-down control pins, and the bus keeper can be applied to an I/O circuit and can be mass-produced.

An embodiment of the present invention provides a bus holder, including: a first pull-up circuit including a first switch and a second switch connected in series; a first pull-down circuit including a third switch and a fourth switch connected in series; and a fifth switch connected in series with the third switch and a sixth switch connected in series with the fourth switch, wherein a source of the fifth switch is connected with a source of the first switch and a source of the sixth switch is connected with a source of the fourth switch.

Illustratively, the bus holder further includes a second pull-up circuit to which a pull-up control signal is input and one end of which is connected to the source of the fifth switch.

Illustratively, the bus holder further includes a second pull-down circuit to which a pull-down control signal is input, and one end of which is connected to the source of the sixth switch.

Illustratively, the bus holder further includes a pull-up/down circuit, one end of which is connected with the second pull-up circuit, and the other end of which is connected with the second pull-down circuit.

Illustratively, the second pull-up circuit includes a seventh switch and an eighth switch connected in series, and a ninth switch and a tenth switch connected in parallel, wherein a source of the seventh switch is connected with a source of the ninth switch.

Illustratively, the second pull-down circuit includes an eleventh switch and a twelfth switch connected in series, and a first resistor and a second resistor connected in series, wherein the eleventh switch is connected in series with the second resistor.

Illustratively, the pull-up/pull-down circuit includes a thirteenth switch and a fourteenth switch connected in series, a fifteenth switch and a sixteenth switch connected in series, and a seventeenth switch and an eighteenth switch connected in parallel, wherein a drain of the thirteenth switch is connected to a gate of the fifteenth switch, a source of the fifteenth switch is connected to a source of the seventeenth switch, and wherein a source of the fourteenth switch is connected to a source of the sixteenth switch, and a drain of the seventeenth switch is connected to a drain of the thirteenth switch.

Another embodiment of the present invention provides an electronic device, which includes the bus holder.

The invention proposes a bus keeper circuit for advanced technology, which is generated by a combinational logic circuit that can be inserted into an I/O circuit.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 is a schematic diagram of a prior art bus retainer;

FIG. 2 is a schematic diagram of another prior art bus keeper;

FIG. 3 is a schematic diagram of another prior art bus retainer;

FIG. 4 is a schematic diagram of a bus retainer in accordance with certain embodiments of the present invention;

FIG. 5 is a schematic diagram of an operating state of a bus keeper according to an embodiment of the invention;

FIG. 6 is a schematic illustration of technical parameters of a bus keeper according to an embodiment of the invention;

FIG. 7 is a schematic diagram of I/V masking of a bus keeper according to an embodiment of the invention; and

FIG. 8 is a diagram illustrating simulation results of a bus keeper, according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Example one

One embodiment of the present invention provides a bus retainer. The bus keeper may be generated by a combinational logic circuit that may be inserted into the I/O circuit.

Next, a bus bar holder of an embodiment of the present invention is specifically described with reference to fig. 4 to 8. FIG. 4 is a schematic diagram of a bus keeper, according to some embodiments of the invention. The bus holder of the embodiment of the present invention includes: a first pull-up circuit including a first switch and a second switch connected in series; a first pull-down circuit including a third switch and a fourth switch connected in series; and a fifth switch connected in series with the third switch and a sixth switch connected in series with the fourth switch, wherein a source of the fifth switch is connected with a source of the first switch and a source of the sixth switch is connected with a source of the fourth switch.

As shown in fig. 4, the bus bar holder (shown as "D") of the present embodiment is mainly composed of three parts, the first part being a first pull-up circuit including a first switch and a second switch connected in series; the second part is a first pull-down circuit including a third switch (shown as "2") and a fourth switch (shown as "3") connected in series; and a third part is a fifth switch ("1" shown in the drawing) connected in series with the third switch and a sixth switch ("4" shown in the drawing) connected in series with the fourth switch, wherein a source of the fifth switch is connected with a source of the first switch, and a source of the sixth switch is connected with a source of the fourth switch. Illustratively, "1" and "2" are P-channel metal oxide semiconductor PMOS, and "3" and "4" are N-channel metal oxide semiconductor NMOS. The first switch is PMOS, and the second switch is NMOS. The source of the fifth switch is connected to VDD, and the source of the sixth switch is connected to VSS. The output voltage VOUT is located at the gate of the first switch. The gate of the "1" is connected to the drain of the first switch, and the drain of the first switch is connected to the drain of the second switch. The gate of "4" is connected to the gate of "1" and the drains of the first and second switches.

Illustratively, the bus holder further includes a second pull-up circuit (shown as "B") to which a pull-up control signal PU is input and one end of which is connected to the source of the fifth switch. The bus holder further includes a second pull-down circuit (shown as "C") to which a pull-down control signal PD is input, and one end of which is connected to the source of the sixth switch. The bus holder further includes a pull-up/down circuit (shown as "a") having one end connected to the second pull-up circuit and the other end connected to the second pull-down circuit. The B circuit operates only when PU is 1 and network Kb is 0, and outputs Vout at a high level, which is a pull-up circuit. The C circuit operates only when PD is 1 and the network K is 1, so that Vout outputs a low level, which is a pull-down circuit.

Illustratively, the pull-up/pull-down circuit includes a thirteenth switch and a fourteenth switch connected in series, a fifteenth switch and a sixteenth switch connected in series, and a seventeenth switch and an eighteenth switch connected in parallel, wherein a drain of the thirteenth switch is connected to a gate of the fifteenth switch, a source of the fifteenth switch is connected to a source of the seventeenth switch, and wherein a source of the fourteenth switch is connected to a source of the sixteenth switch, and a drain of the seventeenth switch is connected to a drain of the thirteenth switch. Wherein, the grid of the seventeenth switch is connected with the grid of the fourteenth switch. The PU signal is connected to the gate of the seventeenth switch, the PD signal is connected to the gate of the thirteenth switch, K is connected to the gate of the fifteenth switch, and Kb is connected to the drain of the fifteenth switch. The network K is formed by NAND of the PU and PD input signals, which are inverted by 180 degrees via an inverter of one phase to generate a network Kb signal. Under the condition that the network K is 0 and the network Kb is 1, Vout is used as an input signal via two inverters to feed back to itself, thereby completing the bus hold function.

The operation of the bus holder according to an embodiment of the present invention will be described with reference to fig. 5. Fig. 5 is a schematic diagram of an operating state of a bus keeper according to an embodiment of the invention.

As shown in FIG. 5, the present invention has 4 working states (pull-up, pull-down, high impedance, bus hold) and the switching of four modes is controlled by two signals of PU and PD. This is a distinction from a typical single bus keeper circuit. The circuit can be used as a bus keeper circuit, and can be embedded into an I/O circuit to bear the functions of partial pull-up, pull-down and the like; in another area, the traditional bus keeper circuit generates a feedback signal by two stages of inverters to achieve the purpose of maintaining the previous working level of the bus, the design processes the second stage of inverter on the basis of reserving the first stage inverter, a controlled MOS transistor is respectively connected in series on a PMOS and an NMOS, and the two added MOS transistors are used for controlling the switch of the second stage of inverter corresponding to the grid terminal network K and the change of the high and low levels of the network Kb. If the network K is equal to 0 and the network Kb is equal to 1, assuming that the level of Vout is 1, PMOS (1) is turned on, NMOS (3), NMOS (4) is turned off, PMOS (1), PMOS (2) are connected in series and are all turned on, and the Vout output is high; assuming that the Vout level is 0, NMOS (3), NMOS (4) is turned on, PMOS (1), PMOS (2) is turned off, and NMOS (3), NMOS (4) are connected in series and are both turned on, the Vout output is low. Thus, the four MOS tubes replace the second-stage inverter, but have the bus holding function. If the network K is 1 and the network Kb is 0, no matter whether Vout is high or low, PMOS (1), PMOS (2), NMOS (3), NMOS (4) are turned on. The circuits in the dashed line do not work, but the circuits on the left side of the dashed line are different with the PU/PD input, and Vout generates different definition functions.

Hereinafter, simulation characteristics of the bus holder according to the embodiment of the present invention will be described with reference to fig. 6 to 8. Fig. 6 is a diagram of technical parameters of a bus keeper according to an embodiment of the invention, fig. 7 is a diagram of I/V masks of a bus keeper according to an embodiment of the invention, and fig. 8 is a diagram of simulation results of a bus keeper according to an embodiment of the invention.

As shown in fig. 6, the data IO should include a bus keeper, which is defined as a minimum output impedance and a maximum output impedance in table 1. At 0.1 × VDD<V<Output impedance R of bus keeper under 0.9 VDD_DATASIn the range 10K ohms to 50K ohms. This effectively creates a mask in the IV characteristics, as shown in fig. 7.

The MOS adopted by the simulation experiment is tt, ss, ff, fnsp and snfp; reset signals res _ tt, res _ ff, and res _ ss; the experimental temperature is-40 to 125 ℃; and VDD 2.5V.

As shown in fig. 8, the second-stage inverter of the conventional bus keeper circuit is modified on the basis of using fewer MOSFETs as much as possible, and in order to realize more functions (pull-up, pull-down, and high-resistance states) embedded in the I/O circuit, the improved bus keeper circuit is added, and the bus keeper circuit is controlled by an external input signal to ensure that the bus keeper circuit has a bus holding function and can be switched to other working states.

Example two

Yet another embodiment of the present invention provides an electronic device including the bus holder of the first embodiment.

The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.

The electronic device of the embodiment of the invention has the advantages because the bus retainer is used.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A bus retainer, comprising:

the first pull-up circuit comprises a first switching tube and a second switching tube which are connected in series;

the first pull-down circuit comprises a third switching tube and a fourth switching tube which are connected in series; and

the third switch tube and the fourth switch tube are connected in series, wherein a source electrode of the third switch tube is connected with a source electrode of the first switch tube, and a source electrode of the sixth switch tube is connected with a source electrode of the fourth switch tube, and the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube form an inverter, and the fifth switch tube and the sixth switch tube are used for controlling the on-off of the inverter.

2. The bus holder of claim 1, further comprising a second pull-up circuit to which a pull-up control signal is input and one end of which is connected to a source of the fifth switching tube.

3. The bus holder of claim 2, further comprising a second pull-down circuit to which a pull-down control signal is input, and one end of which is connected to the source of the sixth switching tube.

4. The bus holder of claim 3, further comprising a pull-up/down circuit, one end of the pull-up/down circuit being connected with the second pull-up circuit, and the other end of the pull-up/down circuit being connected with the second pull-down circuit.

5. The bus holder of claim 2, wherein the second pull-up circuit comprises a seventh switching tube and an eighth switching tube connected in series, and a ninth switching tube and a tenth switching tube connected in parallel, wherein a source of the seventh switching tube is connected with a source of the ninth switching tube.

6. The bus holder of claim 3, wherein the second pull-down circuit comprises an eleventh switching tube and a twelfth switching tube connected in series, and a first resistor and a second resistor connected in series, wherein the eleventh switching tube is connected in series with the second resistor.

7. The bus holder of claim 4, wherein the pull-up/pull-down circuit comprises a thirteenth switching tube and a fourteenth switching tube connected in series, a fifteenth switching tube and a sixteenth switching tube connected in series, and a seventeenth switching tube and an eighteenth switching tube connected in parallel, wherein a drain of the thirteenth switching tube is connected with a gate of the fifteenth switching tube, a source of the fifteenth switching tube is connected with a source of the seventeenth switching tube, and wherein a source of the fourteenth switching tube is connected with a source of the sixteenth switching tube, and a drain of the seventeenth switching tube is connected with a drain of the thirteenth switching tube.

8. An electronic device comprising the bus holder of any of claims 1-7.