CN106874220A - A kind of implementation method of NAND FLASH arrays two-level address mapping table - Google Patents
A kind of implementation method of NAND FLASH arrays two-level address mapping table Download PDFInfo
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- CN106874220A CN106874220A CN201710080630.8A CN201710080630A CN106874220A CN 106874220 A CN106874220 A CN 106874220A CN 201710080630 A CN201710080630 A CN 201710080630A CN 106874220 A CN106874220 A CN 106874220A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0882—Page mode
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Abstract
The present invention be more particularly directed to a kind of implementation method of NAND FLASH arrays two-level address mapping table.The implementation method of the NAND FLASH array two-level address mapping tables, determines that two-level address maps according to NAND FLASH array specifications, determines block address of cache table size and page address of cache table sizes；NAND FLASH array control units receive superior command and simultaneously parse, and perform the order for parsing and the block addresses that are sent according to higher level and operational order and data, inquire about the corresponding page address mapping table of the block, perform operation；Circulation performs above-mentioned flow, until completing whole file reading, erase or write operation.The implementation method of the NAND FLASH array two-level address mapping tables, address of cache is divided into two-layer, different files do not use block with, and support that the dynamic of block addresses is queued up, in the case where NAND FLASH controllers do not design abrasion equilibrium and garbage reclamation, support random erasure function, not only address administration is simple, and compatibility is strong, execution efficiency is high, has broad application prospects.
Description
Technical field
The present invention relates to NAND FLASH controllers and IC design fields, more particularly to a kind of NAND FLASH arrays
The implementation method of two-level address mapping table.
Background technology
NAND-FLASH internal memories are one kind of flash internal memories, and it is internal using non-linear macroelement pattern, is solid-state great Rong
The realization for measuring internal memory provides cheap effective solution.NAND-FLASH memories have capacity larger, rewrite speed fast
The advantages of, it is adaptable to the storage of mass data, thus in the industry cycle obtained increasingly being widely applied, such as wrapped in embedded product
Include digital camera, MP3 walkmans memory card, USB flash disk of compact etc..
Current NAND FLASH antenna array controls are used mostly one-level page address of cache, and each page of each chip is needed
Top-level module is wanted to be respectively controlled, top-level module address administration is complicated and efficiency is low.It is branch because address of cache does not have level
File random erasure is held, it is necessary to NAND FLASH controllers design abrasion equilibrium and garbage reclamation module, design difficulty is big.
For the one-level page address of cache of storage chip array, the present invention proposes a kind of two grades of NAND FLASH arrays
The implementation method of address mapping table.
The content of the invention
A kind of defect in order to make up prior art of the invention, there is provided simple efficient two grades of ground of NAND FLASH arrays
The implementation method of location mapping table.
The present invention is achieved through the following technical solutions：
A kind of implementation method of NAND FLASH arrays two-level address mapping table, it is characterised in that comprise the following steps：
（1）Determine that two-level address maps according to NAND FLASH array specifications, determine block address of cache table size and page ground
Location maps table size；
（2）NAND FLASH array control units receive superior command and parse；
（3）According to read command, erasing order or write order that the order for parsing, execution are parsed；
If read command or erasing order, then block address mapping table is inquired about, the corresponding blcok addresses of file are found out, from low
Block addresses send to storage chip array and read or erasing order to block address cycles high；
If writing commands, then judge whether current file is new file, inquire about whether current block addresses are writable, root
According to various conditions, different block addresses write-in data commands are sent to storage chip array；
（4）The block addresses sent according to higher level and operational order and data, inquire about the corresponding page addresses of the block and reflect
Firing table, performs operation；
（5）Circulation performs above-mentioned flow, until completing whole file reading, erase or write operation.
The step（1）In, it is parallel 16 NAND FLASH chips, 4 grades when NAND FLASH arrays specification is 16x4
The storage array of flowing water, every NAND FLASH chip has 32000 block, each block to have 256 page；
One-level block address of cache table size be 32000 address entrys and a current operation block address pointer entry,
There are two parts, filename and block address of cache and the whether writable flag bits of current block in each address entry, currently
The block addresses that operation block address pointer entry storages are currently being operated；
Two grades of page address mapping table have mono- page address of cache of each block of 32000x64 part, i.e. each chip
Table, each page address of cache table unit has 256 address entrys and a current operation page address pointer entry, each ground
Location entry includes page address and physical address map information, when address pointer points to last page, superior block ground
Location mapping table sends information, and current block is labeled as to write.
The step（3）In, if writing commands, judge whether current file is new file, inquire about current block addresses
Whether it is writable, if new file or current block are for that can not write, is write to next block, if ancient deed and works as
Preceding block is writable, and writing commands are sent to the current block addresses of individual chip.
The beneficial effects of the invention are as follows：The implementation method of the NAND FLASH array two-level address mapping tables, address of cache
It is divided into two-layer, different files do not use block with, and support that the dynamic of block addresses is queued up, and are not set in NAND FLASH controllers
In the case of meter abrasion equilibrium and garbage reclamation, random erasure function is supported, not only address administration is simple, and compatibility is strong,
Execution efficiency is high, has broad application prospects.
Brief description of the drawings
Accompanying drawing 1 is the implementation method schematic diagram of NAND FLASH arrays two-level address mapping table of the present invention.
Specific embodiment
In order that the technical problems to be solved by the invention, technical scheme and beneficial effect become more apparent, below tie
Drawings and Examples are closed, the present invention will be described in detail.It should be noted that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention.
The implementation method of the NAND FLASH array two-level address mapping tables, comprises the following steps：
（1）Determine that two-level address maps according to NAND FLASH array specifications, determine block address of cache table size and page ground
Location maps table size；
（2）NAND FLASH array control units receive superior command and parse；
（3）According to read command, erasing order or write order that the order for parsing, execution are parsed；
If read command or erasing order, then block address mapping table is inquired about, the corresponding blcok addresses of file are found out, from low
Block addresses send to storage chip array and read or erasing order to block address cycles high；
If writing commands, then judge whether current file is new file, inquire about whether current block addresses are writable, root
According to various conditions, different block addresses write-in data commands are sent to storage chip array；
（4）The block addresses sent according to higher level and operational order and data, inquire about the corresponding page addresses of the block and reflect
Firing table, performs operation；
（5）Circulation performs above-mentioned flow, until completing whole file reading, erase or write operation.
It is parallel 16 NAND FLASH chips, 4 grades of storage battle arrays of flowing water when NAND FLASH arrays specification is 16x4
Row, every NAND FLASH chip has 32000 block, each block to have 256 page；
The step（1）In, one-level block address of cache table size is 32000 address entrys and a current operation block
Address pointer entry, there is two parts in each address entry, whether filename and block address of cache and current block are writeable
Enter flag bit, the block addresses that current operation block address pointer entry storages are currently being operated；
Two grades of page address mapping table have mono- page address of cache of each block of 32000x64 part, i.e. each chip
Table, each page address of cache table unit has 256 address entrys and a current operation page address pointer entry, each ground
Location entry includes page address and physical address map information, when address pointer points to last page, superior block ground
Location mapping table sends information, and current block is labeled as to write.
The step（3）In, if writing commands, judge whether current file is new file, inquire about current block addresses
Whether it is writable, if new file or current block are for that can not write, is write to next block, if ancient deed and works as
Preceding block is writable, and writing commands are sent to the current block addresses of individual chip.
The implementation method of the NAND FLASH array two-level address mapping tables, address of cache is divided into two-layer, no matter chip battle array
Why is row specification, and the block address of cache table size that top-level module is seen is the block numbers in monolithic NAND FLASH chips
Mesh, address administration is simple；Different files do not use block with, and support that the dynamic of block addresses is queued up, in NAND FLASH controls
In the case that device processed does not design abrasion equilibrium and garbage reclamation, random erasure function is supported.
Claims (3)
1. a kind of implementation method of NAND FLASH arrays two-level address mapping table, it is characterised in that comprise the following steps：
（1）Determine that two-level address maps according to NAND FLASH array specifications, determine block address of cache table size and page ground
Location maps table size；
（2）NAND FLASH array control units receive superior command and parse；
（3）According to read command, erasing order or write order that the order for parsing, execution are parsed；
If read command or erasing order, then block address mapping table is inquired about, the corresponding blcok addresses of file are found out, from low
Block addresses send to storage chip array and read or erasing order to block address cycles high；
If writing commands, then judge whether current file is new file, inquire about whether current block addresses are writable, root
According to various conditions, different block addresses write-in data commands are sent to storage chip array；
（4）The block addresses sent according to higher level and operational order and data, inquire about the corresponding page addresses of the block and reflect
Firing table, performs operation；
（5）Circulation performs above-mentioned flow, until completing whole file reading, erase or write operation.
2. the implementation method of NAND FLASH arrays two-level address mapping table according to claim 1, it is characterised in that：Institute
State step（1）In, it is parallel 16 NAND FLASH chips, 4 grades of storages of flowing water when NAND FLASH arrays specification is 16x4
Array, every NAND FLASH chip has 32000 block, each block to have 256 page；
One-level block address of cache table size be 32000 address entrys and a current operation block address pointer entry,
There are two parts, filename and block address of cache and the whether writable flag bits of current block in each address entry, currently
The block addresses that operation block address pointer entry storages are currently being operated；
Two grades of page address mapping table have mono- page address of cache of each block of 32000x64 part, i.e. each chip
Table, each page address of cache table unit has 256 address entrys and a current operation page address pointer entry, each ground
Location entry includes page address and physical address map information, when address pointer points to last page, superior block ground
Location mapping table sends information, and current block is labeled as to write.
3. the implementation method of the NAND FLASH array two-level address mapping tables according to claim 1 any one, it is special
Levy and be：The step（3）In, if writing commands, judge whether current file is new file, inquire about current block addresses
Whether it is writable, if new file or current block are for that can not write, is write to next block, if ancient deed and works as
Preceding block is writable, and writing commands are sent to the current block addresses of individual chip.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107562644A (en) * | 2017-08-11 | 2018-01-09 | 记忆科技(深圳)有限公司 | A kind of compression method of solid-state hard disc mapping table |
| CN108470005A (en) * | 2018-03-13 | 2018-08-31 | 山东超越数控电子股份有限公司 | A kind of NandFlash antenna array controls method |
| CN109690498A (en) * | 2016-09-28 | 2019-04-26 | 华为技术有限公司 | EMS memory management process and equipment |
| CN110119252A (en) * | 2019-05-21 | 2019-08-13 | 济南浪潮高新科技投资发展有限公司 | A kind of management method and device of Common Flash Memory storage storage array |
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| US20170024277A1 (en) * | 2008-04-11 | 2017-01-26 | Micron Technology, Inc. | Method and apparatus for a volume management system in a non-volatile memory device |
| CN101937319A (en) * | 2009-06-29 | 2011-01-05 | 联发科技股份有限公司 | Memory system and its mapping method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109690498A (en) * | 2016-09-28 | 2019-04-26 | 华为技术有限公司 | EMS memory management process and equipment |
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| CN107562644A (en) * | 2017-08-11 | 2018-01-09 | 记忆科技(深圳)有限公司 | A kind of compression method of solid-state hard disc mapping table |
| CN108470005A (en) * | 2018-03-13 | 2018-08-31 | 山东超越数控电子股份有限公司 | A kind of NandFlash antenna array controls method |
| CN110119252A (en) * | 2019-05-21 | 2019-08-13 | 济南浪潮高新科技投资发展有限公司 | A kind of management method and device of Common Flash Memory storage storage array |
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