CN106873545A - A kind of real-time multiprocessors system based on FPGA - Google Patents
A kind of real-time multiprocessors system based on FPGA Download PDFInfo
- Publication number
- CN106873545A CN106873545A CN201510924600.1A CN201510924600A CN106873545A CN 106873545 A CN106873545 A CN 106873545A CN 201510924600 A CN201510924600 A CN 201510924600A CN 106873545 A CN106873545 A CN 106873545A
- Authority
- CN
- China
- Prior art keywords
- message
- data
- fpga
- real
- queue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 56
- 230000008569 process Effects 0.000 claims description 47
- 238000013523 data management Methods 0.000 claims description 16
- 238000012544 monitoring process Methods 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 238000004458 analytical method Methods 0.000 claims description 4
- 238000004891 communication Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 7
- 238000012790 confirmation Methods 0.000 description 7
- 230000004044 response Effects 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
- G05B19/41865—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by job scheduling, process planning, material flow
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Multi Processors (AREA)
Abstract
The invention discloses a kind of real-time multiprocessors system based on FPGA, the system includes：System clock module, for generation system clock signal；Message manager, for according to the message in clock signal of system timing new information queue, according to the processing sequence of priority decision message；The message is the mission bit stream for needing to perform；Fpga chip, the processing sequence of the message for being determined according to message manager, is processed the message in message queue, performs task corresponding with the message.The system realizes ensureing the real-time of control, and reduces cost.
Description
Technical field
The present invention relates to automatic control technology field, more particularly to a kind of reality based on FPGA
When multiple tasks dispatching system.
Background technology
At present, in automation field, it is ensured that real-time be it is critically important, designer although
It can be desirable to selection dominant frequency is higher, the stronger processor of operational capability, with reply increasingly complexity
Control object, but as the engineering problems such as EMC, radiating are often into the obstacle for being difficult to cross over.
Now, designer can often attempt the method with processor quantity is increased again, will to reach control
Ask, but reduces cost, to reduce the fault point be also the problem that can not be ignored.How control is ensured
Simultaneously reduces cost is a problem urgently to be resolved hurrily to real-time.
The content of the invention
It is an object of the invention to provide a kind of real-time multiprocessors system based on FPGA, with
Realize ensureing the real-time of control, and reduces cost.
In order to solve the above technical problems, the present invention provides a kind of real-time multi-task based on FPGA
Scheduling system, the system includes：
System clock module, for generation system clock signal；
Message manager, for according to disappearing in clock signal of system timing new information queue
Breath, according to the processing sequence of priority decision message；The message is the task letter for needing to perform
Breath；
Fpga chip, the processing sequence of the message for being determined according to message manager, offsets
Message in breath queue is processed, and performs task corresponding with the message.
Preferably, the system also includes counter, for being carried out to the message in message queue
Count.
Preferably, the fpga chip is additionally operable to obtain business datum from external data bus,
The business datum for getting is cached in piece in information source FIFO.
Preferably, the fpga chip also includes：
Sending module, for sending host process；
Receiver module, for receiving traffic frame monitoring process, receives data, and data are solved
Analysis.
Preferably, the fpga chip also includes：
Information source data management module, confirms for performing data-message query procedure, internal storage data
Process, data management host process, data management assisted process and pointer update synchronized process；
Stay of two nights data management module, for performing state auxiliary operation process and more new state information
Process and more new state information assisted process.
Preferably, the message includes data-message, command messages and check code message.
A kind of real-time multiprocessors system based on FPGA provided by the present invention, including：
System clock module, for generation system clock signal；Message manager, for according to system
Message in clock signal timing new information queue, the place according to priority decision message is made in order
Sequence；The message is the mission bit stream for needing to perform；Fpga chip, for according to message pipe
Reason device determine message processing sequence, the message in message queue is processed, perform with
The corresponding task of the message.It can be seen that, message manager updates according to clock signal of system timing
Message in message queue, according to the processing sequence of priority decision message, fpga chip is pressed
Message is processed according to order, task corresponding with message is performed, thus by message management
Device is updated to message, and multiple message correspondences are performed using parallel mode using FPGA module
Task, according to processing sequence perform, realize the real-time of task control, and need not increase
Add a processor to realize task processes, it is only necessary to processed using fpga chip
, cost so is saved on the premise of real-time is ensured, so the system is realized ensureing
The real-time of control, and reduces cost.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below
The accompanying drawing to be used needed for embodiment or description of the prior art will be briefly described, show and
Easy insight, drawings in the following description are only embodiments of the invention, common for this area
For technical staff, on the premise of not paying creative work, can also be attached according to what is provided
Figure obtains other accompanying drawings.
Fig. 1 is a kind of real-time multiprocessors system based on FPGA provided by the present invention
Structural representation.
Specific embodiment
Core of the invention is to provide a kind of real-time multiprocessors system based on FPGA, with
Realize ensureing the real-time of control, and reduces cost.
In order that those skilled in the art more fully understand the present invention program, below in conjunction with this
Accompanying drawing in inventive embodiments, is carried out clear, complete to the technical scheme in the embodiment of the present invention
Ground description, it is clear that described embodiment is only a part of embodiment of the invention, rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not having
The every other embodiment obtained under the premise of creative work is made, protection of the present invention is belonged to
Scope.
Fig. 1 is refer to, Fig. 1 is a kind of real-time many based on FPGA provided by the present invention
The structural representation of scheduling system of being engaged in, the system includes：
System clock module 101, for generation system clock signal；
Message manager 102, for according in clock signal of system timing new information queue
Message, according to the processing sequence of priority decision message；The message is the needing to perform of the task
Information；
Fpga chip 103, the processing sequence of the message for being determined according to message manager,
Message in message queue is processed, task corresponding with message is performed.
Wherein, the message includes data-message, command messages and check code message.
Optionally, the system also includes counter, for being carried out to the message in message queue
Count.
Fpga chip is additionally operable to obtain business datum from external data bus, the industry for getting
Business data buffer storage is in information source FIFO in piece.
Fpga chip also includes：
Sending module, for sending host process；
Receiver module, for receiving traffic frame monitoring process, receives data, and data are solved
Analysis.
Fpga chip also includes：
Information source data management module, confirms for performing data-message query procedure, internal storage data
Process, data management host process, data management assisted process and pointer update synchronized process；
Stay of two nights data management module, for performing state auxiliary operation process and more new state information
Process and more new state information assisted process.
It can be seen that, message manager is according to disappearing in clock signal of system timing new information queue
Breath, according to the processing sequence of priority decision message, fpga chip enters to message in sequence
Row treatment, performs task corresponding with message, and message is carried out more thus by message manager
Newly, the corresponding task of multiple message is performed using parallel mode using fpga chip, according to place
Make sequence execution in order, realize the real-time of task control, and multiple processors need not be increased
Realize task processes, it is only necessary to processed using fpga chip, so protecting
Cost is saved on the premise of card real-time, so the system realizes ensureing the real-time of control,
And reduces cost.
Specifically, the elementary cell of FPGA, i.e. look-up table Look-Up-Table --- referred to as
LUT, a suitable ram cell.Many LUT using 4 inputs in FPGA, so often
One LUT can regard a RAM for having 4 bit address lines as.When by schematic diagram or language
After describing a logic circuit, FPGA exploitations software can automatic calculation logic circuit it is all
Possible result, and result is write RAM in advance, i.e., being often input into a signal carries out logic fortune
Calculation is equal to one address of input and is tabled look-up, and finds out the corresponding content in address, and then output is
Can.Function based on look-up table, FPGA can perform parallel work-flow.With traditional serial behaviour
Compared as mechanism, this parallel mode can greatly improve logical operation capability.Therefore FPGA
With the ability for processing multiple events simultaneously.
Message manager is related to the message queue in operating system.Because FPGA has parallel
The ability of computing, it is possible to while responding multiple from outside actuation event.But in reality
Automatic control system in, for the response of event, should often be ordered into.Event is made
It is message, and various message is sorted successively, so that it may obtains message queue.And message manager
It is responsible for, the medium pending message of message queue, being sent to according to pre-defined rule and performing list
Position, the information process unit for making it perform corresponding operating.
Multi-task scheduling is realized with FPGA, system must just have system clock, system clock
It is the driving source of scheduling mechanism.Because scheduling system, differentiates message, " message " row is given
Sequence, is all based on the hardware configuration of LUT, if without clock triggering, the addressing of LUT is with regard to nothing
Method is realized.Further, since the excitation of input automatic control system is often across time domain, so
System clock can be multichannel, the event different to tackle response speed.Multipath clock can have
Standby certain phase relation, can be realized by phaselocked loop etc..
The system can also include administrative unit, and administrative unit is gone back in addition to comprising message manager
Can be including the counter of correspondence system clock, parameter configuration unit, abnormal restoring unit etc..
The module, it is believed that be the maincenter of scheduling system.When the module is designed, in considering
Outside portion's logical synchronization, it is also contemplated that preventing self-locking.
The system can also include execution unit, and execution unit is typically to carrying out self-management unit
What instruction was explained.Because, the operation of some complexity, it may be possible to by some action sequences
Row are combined, in order to ensure the real-time of administrative unit, for those more complicated events,
Execution unit assists to complete the generation of final control information.Exactly because the also direct face of execution unit
To the logic module of bottom, there is more complicated time domain to convert, so just should not be with administrative unit
Merge, so reduce system design difficulty.
Message content in message manager timing new information queue, and according to priority,
The processing sequence of decision message.It should be noted that in order to ensure the real-time for automatically controlling,
The time interval of information processing, will be much smaller than the time requirement of system incentive response.Additionally, excellent
First level, can dynamically adjust, without processed information, into suspended state, until being swashed
It is living.In scheduling mechanism, it is necessary to add the monitoring module for preventing self-locking, prevent from crashing.Scheduling
Mechanism essence is exactly：Message manager presses the process of rule process information.
FPGA within the system, undertakes following task：Business number is obtained from external data bus
According to；The business datum for acquiring is cached in piece in information source FIFO；Inquiry stay of two nights state；
Switching " transmission service condition "：Information source/the stay of two nights；From information source FIFO access, and send；To hair
The business sent carries out ECC codings；The traffic frame that verification is received, and parse；According to business solution
The content of analysis, carries out various operations, for example, update or reduce information source FIFO, update or reduction letter
Place FIFO, toward stay of two nights FIFO write-in data, update system message manager related content and
Asynchronous operation is realized with the method for synchronization；When exporting effective, the data in stay of two nights FIFO,
It is sent on external data bus；
Due to requiring to realize full duplex communication function, so in structure, FPGA should mainly be wrapped
Include the modules such as transmission, reception, data management.Sending module correspondence transmitting terminal host process, transmission
Process；Receiver module correspondence receiving terminal traffic frame monitoring process, receiving terminal data receiver process,
Receive end data parsing process；Module, corresponding data information query process are managed in information source data management
And internal storage data confirmation process, data management host process and assisted process, transmitting terminal read pointer are more
New synchronized process；Stay of two nights data management module, corresponding states auxiliary operation process, more new state
Message procedure and assisted process.Each functional module is uniformly coordinated by M count device and message manager
Work, M count code is by transmitting terminal system counter controls process and transmitting terminal system counter M
Process is produced, for the process of each functional module provides synchronous beat；Message manager is a pipe
The message queue of reason system task switching, it includes data, order and check code message, each work(
Energy module judges whether corresponding operating is activated by query messages queue.The system is also wrapped
Two analog phase-locked looks PLL_Send and PLL_Receive are included, they are respectively transmitting terminal system
Statistical number device M and receiving terminal system counter provide reference clock.
Specifically, information source FIFO read pointer _ N is defined as Rsp_N, when forward direction is incremented by and stepping
When length is 1, represent that information source FIFO exports a 8bit data；When negative sense is incremented by, table
Show communication error.Information source FIFO read pointer _ O is defined as Rsp_O, information source FIFO outputs "
Before bag " data, backup of the system to information source FIFO read pointer _ N.Stay of two nights FIFO write pointers
_ N is defined as Wrp_N, when forward direction is incremented by and stepping length is 1, represents that stay of two nights FIFO is defeated
Enter a 8bit data；When negative sense is incremented by, communication error is represented.Stay of two nights FIFO write pointers
_ O is defined as Wrp_O, and before stay of two nights FIFO inputs " bag " data, system is to stay of two nights FIFO
The backup of write pointer _ N.Pointer zero is the Wrp_N when resetting or communication malfunctions<=
Wrp_O.It is the Wrp_O when " bag " communication is successfully completed that pointer updates<=Wrp_N.
Search space is the information source inquiry stay of two nights, if with the memory space for accommodating " maximum bag length ",
That is whether stay of two nights FIFO also has memory space.Inquiry check code is the information source inquiry stay of two nights, this bag
The verification state of data.It is that pointer rezero operation is completed that pointer has been zeroed.Pointer has updated and has referred to
Pin updates operation to be completed.Business datum is the data that information source passes to the stay of two nights.Check code is the stay of two nights
Pass to the check information of information source.
Inside FPGA, while in the presence of two flow of task, also including in each flow of task
Some small tasks.Before task scheduling is illustrated, clear and definite message queue is first wanted.
Under full duplex state, system is both information source for message and system message queue, is again the stay of two nights.
The mutual conversion of information source state and stay of two nights state is realized, system is it is necessary to have a manager.
The manager was responsible in the specific time, and what operation is the system of informing should perform.So, it is fixed
Control information in adopted manager, is message；It is system message queue to define manager simultaneously.
According to type of service above, define type of message and be respectively：Check code message, command messages,
Data-message.Extended code be system under information source state, the information to be sent.The information is divided into
Three classes：Local stay of two nights state, command code, business datum.Local stay of two nights state, i.e., at system
In stay of two nights state, it is necessary to the state of response communication the opposing party order, it includes：Pointer is zeroed
State, the enough states in space, pointer more new state.
When command code, i.e. system are in information source state, the operational order of communication the opposing party is issued,
It includes：The order of pointer zero, pointer more newer command, search space order, inquiry check code
Order.When business datum is that system is in information source state, from local information source FIFO, take out
, it is intended to be sent to the data of communication the opposing party.Reception state confirmation code is when information source sends certain life
After order to the stay of two nights, information source needs to wait the response of the stay of two nights, the i.e. stay of two nights to return corresponding state.When
To after corresponding state, reception state confirmation code is updated to command messages identification code to signal source receiving,
This is one kind of message authentication code, and to represent that preceding once-through operation is completed, system can perform other
Command operation.It is because system is multitask running, so sending module is needed to send confirmation code
The information for having sent is marked, i.e., sending module needs to carry out to the message having responded to
Mark, with confirmation message queue, can be updated.Message authentication code is responsible for the different behaviour of mark
Make, i.e. each operation has a numbering, after a certain operation is finished, the code Jia 1 certainly.
Action type includes：State, order, data.Hang up mark i.e. order and hang up mark.Work as letter
When source sends data, its command messages is updated to inquire about check code order by search space order.
Now, because information source has not sent data, so inquiry check code order should not be performed.
Mark is hung up in order, that is, represent that the order is in suspended state.When data is activation terminates, hang up
Mark is released.Information source is the data amount check of the actual transmission of each business packet per bag data number.
Timing query messages queue, and by judging that sending confirmation code and message authentication code is
No synchronization, to determine which kind of task performed.After system performs certain task, send and confirm
Code is updated to corresponding message authentication code.The executive process of system task switching, really sends out
It is sent into journey.The relation of transmission process and suitable 2 level production line of transmitting terminal host process：Host process root
According to the priority of message, current being performed for the task of selection；After host process tasks clear type,
Transmission process relevant information can be passed to.Transmission process is transmitted work as indicated, and bears
Duty updates and sends confirmation code.Due to using parallel mode, real-time also to reach estimated index.
To sum up, a kind of real-time multiprocessors system based on FPGA provided by the present invention,
Including：System clock module, for generation system clock signal；Message manager, for according to
According to the message in clock signal of system timing new information queue, according to priority decision message
Processing sequence；The message is the mission bit stream for needing to perform；Fpga chip, for foundation
The processing sequence of the message that message manager is determined, is processed the message in message queue,
Perform task corresponding with the message.It can be seen that, message manager is determined according to clock signal of system
When new information queue in message, according to the processing sequence of priority decision message, FPGA
Chip is processed message in sequence, performs corresponding with message task, thus by disappearing
Breath manager is updated to message, and performing multiple using parallel mode using FPGA module disappears
Corresponding task is ceased, is performed according to processing sequence, realize the real-time of task control, and not
Need to increase multiple processors to realize task processes, it is only necessary to enter using fpga chip
Row treatment, so saves cost, so the system reality on the premise of real-time is ensured
Now ensure the real-time of control, and reduces cost.
A kind of real-time multiprocessors system based on FPGA provided by the present invention is entered above
Go and be discussed in detail.Specific case used herein is entered to principle of the invention and implementation method
Elaboration is gone, the explanation of above example is only intended to help and understands the method for the present invention and its core
Thought is thought.It should be pointed out that for those skilled in the art, not departing from
On the premise of the principle of the invention, some improvement and modification can also be carried out to the present invention, these change
Enter and modify to also fall into the protection domain of the claims in the present invention.
Claims (6)
1. a kind of real-time multiprocessors system based on FPGA, it is characterised in that including：
System clock module, for generation system clock signal；
Message manager, for according to disappearing in clock signal of system timing new information queue
Breath, according to the processing sequence of priority decision message；The message is the task letter for needing to perform
Breath；
Fpga chip, the processing sequence of the message for being determined according to message manager, offsets
Message in breath queue is processed, and performs task corresponding with the message.
2. the system as claimed in claim 1, it is characterised in that the system also includes meter
Number device, for being counted to the message in message queue.
3. the system as claimed in claim 1, it is characterised in that the fpga chip is also
For obtaining business datum from external data bus, the business datum for getting is cached in piece
In information source FIFO.
4. system as claimed in claim 3, it is characterised in that the fpga chip is also
Including：
Sending module, for sending host process；
Receiver module, for receiving traffic frame monitoring process, receives data, and data are solved
Analysis.
5. system as claimed in claim 4, it is characterised in that the fpga chip is also
Including：
Information source data management module, confirms for performing data-message query procedure, internal storage data
Process, data management host process, data management assisted process and pointer update synchronized process；
Stay of two nights data management module, for performing state auxiliary operation process and more new state information
Process and more new state information assisted process.
6. the system as described in any one in claim 1 to 5, it is characterised in that institute
Stating message includes data-message, command messages and check code message.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510924600.1A CN106873545A (en) | 2015-12-14 | 2015-12-14 | A kind of real-time multiprocessors system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510924600.1A CN106873545A (en) | 2015-12-14 | 2015-12-14 | A kind of real-time multiprocessors system based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106873545A true CN106873545A (en) | 2017-06-20 |
Family
ID=59177624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510924600.1A Pending CN106873545A (en) | 2015-12-14 | 2015-12-14 | A kind of real-time multiprocessors system based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106873545A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107480002A (en) * | 2017-07-26 | 2017-12-15 | 阿里巴巴集团控股有限公司 | Message treatment method and device, electronic equipment |
| CN107992370A (en) * | 2017-11-28 | 2018-05-04 | 上海机电工程研究所 | VxWorks platform multi-tasks Software framework implementation method |
| CN112596354A (en) * | 2020-12-29 | 2021-04-02 | 南京立思辰智能设备有限公司 | High-speed scanning control system and method for laser printer |
| CN112596353A (en) * | 2020-12-29 | 2021-04-02 | 南京立思辰智能设备有限公司 | High-speed scanning control circuit for laser printing |
| CN114327649A (en) * | 2021-12-17 | 2022-04-12 | 中国船舶重工集团公司第七一五研究所 | High-precision active sonar display control method based on VxWorks |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266553A (en) * | 2008-05-06 | 2008-09-17 | 无锡紫芯集成电路系统有限公司 | Multitask management process based on embedded system |
| CN101290588A (en) * | 2008-03-07 | 2008-10-22 | 重庆邮电大学 | A micro-embedded real-time task scheduler and scheduling method |
| CN103412755A (en) * | 2013-08-16 | 2013-11-27 | 深圳东原电子有限公司 | Hardware real-time operation system |
| US20140245314A1 (en) * | 2004-03-29 | 2014-08-28 | Sony Computer Entertainment Inc. | Methods and apparatus for achieving thermal management using processing task scheduling |
| CN104615488A (en) * | 2015-01-16 | 2015-05-13 | 华为技术有限公司 | Task scheduling method and device on heterogeneous multi-core reconfigurable computing platform |
-
2015
- 2015-12-14 CN CN201510924600.1A patent/CN106873545A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140245314A1 (en) * | 2004-03-29 | 2014-08-28 | Sony Computer Entertainment Inc. | Methods and apparatus for achieving thermal management using processing task scheduling |
| CN101290588A (en) * | 2008-03-07 | 2008-10-22 | 重庆邮电大学 | A micro-embedded real-time task scheduler and scheduling method |
| CN101266553A (en) * | 2008-05-06 | 2008-09-17 | 无锡紫芯集成电路系统有限公司 | Multitask management process based on embedded system |
| CN103412755A (en) * | 2013-08-16 | 2013-11-27 | 深圳东原电子有限公司 | Hardware real-time operation system |
| CN104615488A (en) * | 2015-01-16 | 2015-05-13 | 华为技术有限公司 | Task scheduling method and device on heterogeneous multi-core reconfigurable computing platform |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107480002A (en) * | 2017-07-26 | 2017-12-15 | 阿里巴巴集团控股有限公司 | Message treatment method and device, electronic equipment |
| CN107480002B (en) * | 2017-07-26 | 2020-06-30 | 阿里巴巴集团控股有限公司 | Message processing method and device and electronic equipment |
| CN107992370A (en) * | 2017-11-28 | 2018-05-04 | 上海机电工程研究所 | VxWorks platform multi-tasks Software framework implementation method |
| CN107992370B (en) * | 2017-11-28 | 2021-01-22 | 上海机电工程研究所 | VxWorks platform multitask software framework implementation method |
| CN112596354A (en) * | 2020-12-29 | 2021-04-02 | 南京立思辰智能设备有限公司 | High-speed scanning control system and method for laser printer |
| CN112596353A (en) * | 2020-12-29 | 2021-04-02 | 南京立思辰智能设备有限公司 | High-speed scanning control circuit for laser printing |
| CN114327649A (en) * | 2021-12-17 | 2022-04-12 | 中国船舶重工集团公司第七一五研究所 | High-precision active sonar display control method based on VxWorks |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106873545A (en) | A kind of real-time multiprocessors system based on FPGA | |
| CN113258546B (en) | Chip-level software and hardware cooperative relay protection device | |
| CN109815028A (en) | Data synchronous system, method, apparatus and computer storage medium | |
| CN113179227B (en) | AT instruction control method based on queue | |
| CN113132144A (en) | Alarm processing method and device and storage medium | |
| CN108509327A (en) | A kind of log-output method, device, terminal device and storage medium | |
| CN101867490B (en) | Maintenance operation system and method | |
| CN111899501B (en) | Remote control method for switch in distribution network automation master station substation | |
| CN105677469A (en) | Timing task executing method and device | |
| CN106444425A (en) | Design method of DCS controlled TTP/C bus controller catering to aeroengine | |
| CN106453541A (en) | Data synchronization method, server and data synchronization system | |
| CN110569113A (en) | Method and system for scheduling distributed tasks and computer readable storage medium | |
| CN110740145A (en) | Message consumption method, device, storage medium and electronic equipment | |
| CN109783151A (en) | The method and apparatus of rule change | |
| CN113193947B (en) | Method, apparatus, medium, and program product for implementing distributed global ordering | |
| CN114448802A (en) | Gateway configuration method and device, electronic equipment and storage medium | |
| CN107924330A (en) | Technology for integrated thread scheduling | |
| CN112559202A (en) | Aircraft application software communication method based on embedded real-time operating system | |
| CN113608765A (en) | Data processing method, apparatus, device and storage medium | |
| CN113656239A (en) | Monitoring method and device for middleware and computer program product | |
| CN115168141A (en) | Optical interface management system, method, device, programmable logic device and storage medium | |
| CN114844920A (en) | Internet of things equipment checking method and device, electronic equipment and storage medium | |
| CN103973489A (en) | Centralized monitoring system for heterogeneous devices | |
| CN111813621B (en) | Data processing method, device, equipment and medium based on Flume data center | |
| CN113419921A (en) | Task monitoring method, device, equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170620 |
|
| RJ01 | Rejection of invention patent application after publication |