CN106873272B - Liquid crystal display panel in multi-domain vertical orientation mode and manufacturing method thereof - Google Patents
Liquid crystal display panel in multi-domain vertical orientation mode and manufacturing method thereof Download PDFInfo
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- CN106873272B CN106873272B CN201611257896.7A CN201611257896A CN106873272B CN 106873272 B CN106873272 B CN 106873272B CN 201611257896 A CN201611257896 A CN 201611257896A CN 106873272 B CN106873272 B CN 106873272B
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 230000008878 coupling Effects 0.000 claims abstract description 80
- 238000010168 coupling process Methods 0.000 claims abstract description 80
- 238000005859 coupling reaction Methods 0.000 claims abstract description 80
- 239000003990 capacitor Substances 0.000 claims abstract description 65
- 239000010409 thin film Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000003860 storage Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 55
- 239000002184 metal Substances 0.000 claims description 27
- 238000002161 passivation Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 5
- 239000010408 film Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 71
- 238000002834 transmittance Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 9
- 230000001808 coupling effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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Abstract
The invention discloses a liquid crystal display panel of a multi-domain vertical orientation mode and a manufacturing method thereof, wherein the liquid crystal display panel comprises an array substrate, a plurality of pixel units are arranged on the array substrate, each pixel unit comprises a first sub-pixel electrode and a second sub-pixel electrode, and the first sub-pixel electrode and the second sub-pixel electrode respectively form a storage capacitor with a public electrode wiring; in each pixel unit, the first sub-pixel electrode is configured to be electrically connected with the drain electrode of the thin film transistor and electrically connected with the coupling capacitor wiring; the second sub-pixel electrode is configured to form a coupling capacitance with the coupling capacitance wiring; the common electrode wiring is overlapped with the first sub-pixel electrode and the second sub-pixel electrode, a hollow area used for accommodating the coupling capacitor wiring is arranged below the second sub-pixel electrode, the coupling capacitor wiring is insulated from the common electrode wiring, and the common electrode wiring is formed by the etched transparent conductive layer. This scheme of adoption can improve the penetrating rate of liquid crystal display panel and show the quality simultaneously.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a multi-domain vertical alignment mode liquid crystal panel and a manufacturing method thereof.
Background
The liquid crystal display has the characteristics of low radiation, low power consumption, small size and the like, gradually becomes the mainstream of display devices, and is widely applied to products such as mobile phones, notebook computers, flat televisions and the like.
In order to obtain a high viewing angle and a high display quality, a general MVA (Multi-Domain vertical alignment) display panel adopts a 4-Domain (Domain) display structure. Fig. 1 is a schematic structural diagram of a 4-domain MVA display panel of the related art, and as shown in fig. 1, a Gate line (Gate)101, a Data line (Data)102, a common electrode line (Com)103, a Thin Film Transistor (TFT)104, and a pixel electrode (ITO)105 form a basic pixel structure. The pixel electrode is designed to have a structure with a notch 106, and is cut into a plurality of areas to match with alignment protrusions (Protrusion) on a Color Filter (CF) substrate, so that a 4-domain display structure is formed. In this display structure, the common electrode and the pixel electrode form a storage capacitor for holding a pixel voltage and reducing a Feed Through voltage. Increasing the storage capacitance helps to improve display quality, but increasing the common electrode area reduces transmittance.
The defects of the prior art are as follows: the display quality and transmittance of the display panel cannot be improved at the same time.
Disclosure of Invention
In view of the above technical problems, the present invention provides a multi-domain vertical alignment mode liquid crystal display panel, which includes an array substrate having a plurality of pixel units disposed thereon, wherein each pixel unit has a thin film transistor, a coupling capacitor wire, and a common electrode wire disposed therein,
each pixel unit comprises a first sub-pixel unit with a first sub-pixel electrode and a second sub-pixel unit with a second sub-pixel electrode, and the first sub-pixel electrode and the second sub-pixel electrode respectively form storage capacitors with the common electrode wiring;
in each pixel unit, the first sub-pixel electrode is configured to be electrically connected with the drain electrode of the thin film transistor and electrically connected with the coupling capacitor wiring; the second sub-pixel electrode is configured to form a coupling capacitance with the coupling capacitance wiring;
the common electrode wiring covers the whole pixel area of the pixel unit, a hollow area for accommodating the coupling capacitance wiring is arranged below the second sub-pixel electrode, the coupling capacitance wiring is insulated from the common electrode wiring, and the common electrode wiring is formed by a transparent conductive layer.
In one embodiment, the coupling capacitance wiring is formed by an etched transparent conductive layer, and the coupling capacitance wiring and the common electrode wiring are arranged in the same layer.
In one embodiment, the gate wiring of the thin film transistor includes a transparent conductive layer and a gate metal.
In one embodiment, the drain of the thin film transistor is communicated with a first via hole, the coupling capacitor wire is communicated with a second via hole, the first sub-pixel electrode is electrically connected with the drain of the thin film transistor through the first via hole, and the first sub-pixel electrode is electrically connected with the coupling capacitor wire through the second via hole.
In one embodiment, the color filter further comprises a color filter substrate, and the color filter substrate is provided with a ridge-shaped protrusion.
In one embodiment, the pixel electrode on the array substrate is provided with a notch.
In one embodiment, the first sub-pixel unit forms the first display area divided into a plurality of domains by the ridge-like protrusion and/or the notch; the second sub-pixel unit forms a second display area divided into a plurality of domains through the ridge-shaped protrusion and/or the notch.
According to another aspect of the present invention, there is also provided a method of fabricating a multi-domain vertical alignment mode liquid crystal display panel, comprising the steps of:
depositing a layer of transparent conductive material on the substrate to form a transparent conductive layer, and then continuously depositing gate metal to form a gate metal layer;
etching the transparent conductive layer and the grid metal layer by adopting a multi-gray scale photomask process, forming a common electrode wiring and a coupling capacitor wiring by the exposed transparent conductive layer after the grid metal layer of the pixel region is etched, and forming a grid wiring with a double-layer structure by the etched transparent conductive layer and the etched grid metal layer of the thin film transistor region; the common electrode wiring is provided with a hollow-out area used for accommodating the coupling capacitor wiring below the second sub-pixel electrode, and the coupling capacitor wiring is insulated from the common electrode wiring;
depositing a layer of gate insulating material to form a gate insulating layer;
carrying out a semiconductor layer process and a source drain process, and depositing a layer of passivation material to form a passivation layer after forming an active layer, a data line and a source drain;
performing a via hole process, wherein the drain is communicated with a first via hole, and the coupling capacitor wiring is communicated with a second via hole, so that the first sub-pixel electrode is electrically connected with the drain of the thin film transistor through the first via hole and is electrically connected with the coupling capacitor wiring through the second via hole;
and at least two independent sub-pixel electrodes are formed in the pixel area on the passivation layer by using a transparent conductive material, each sub-pixel electrode forms a storage capacitor with the common electrode wiring, and the second sub-pixel electrode is configured to form a coupling capacitor with the coupling capacitor wiring.
In one embodiment, the multi-gray scale mask process comprises:
semi-exposing with a semi-permeable film;
or, the micro-slit below the resolution of the exposure machine is made, and a part of the light source is shielded by the micro-slit part, so as to achieve the semi-exposure effect.
One or more embodiments of the present invention may have the following advantages over the prior art:
first, in the liquid crystal display panel provided by the present invention, the existing pixel structure is improved to form a plurality of display regions, so as to improve the display quality of the display panel, and the common electrode wiring is formed by using a transparent conductive layer with high transmittance, so as to improve the transmittance of the display panel, that is, to improve both the transmittance and the display quality of the display panel.
Secondly, in the manufacturing method of the liquid crystal display panel provided by the invention, the transparent conducting layer and the grid metal layer are etched by adopting a multi-gray-scale photomask process through 1 photomask, the exposed transparent conducting layer after the grid metal layer in the pixel region is etched away forms a common electrode wiring and a coupling capacitor wiring, and the etched transparent conducting layer in the thin film transistor region and the etched grid metal layer form a grid wiring with a double-layer structure, so that the process cost is saved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a conventional 4-domain MVA display panel;
FIG. 2a is a schematic diagram of an 8-domain MVA display panel according to a first embodiment of the present invention;
FIG. 2b is a schematic diagram of a pixel electrode structure according to the first embodiment of the present invention;
FIG. 3 is a flowchart of a method of fabricating a multi-domain vertical alignment mode LCD panel according to a second embodiment of the present invention;
FIG. 4a is a schematic cross-sectional view of a pixel region of a liquid crystal display panel according to a second embodiment of the present invention;
FIG. 4b is a schematic cross-sectional view of a TFT region of an LCD panel according to a second embodiment of the present invention;
fig. 5a is a schematic cross-sectional structure diagram of a common electrode wiring and a coupling capacitance wiring formed on the basis of fig. 4a according to a second embodiment of the present invention;
FIG. 5b is a schematic cross-sectional view of a gate wiring formed on the substrate of FIG. 4b according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram of a second embodiment of a LCD panel corresponding to the one shown in FIG. 5;
FIG. 7a is a schematic cross-sectional view of a data line formed on the basis of FIG. 5a according to a second embodiment of the present invention;
FIG. 7b is a schematic cross-sectional structure diagram of a source/drain formed on the basis of FIG. 5b according to a second embodiment of the present invention;
FIG. 8 is a schematic diagram of a second embodiment of a LCD panel corresponding to the one shown in FIG. 7;
FIG. 9a is a schematic cross-sectional view of a via formed on the substrate of FIG. 7a according to a second embodiment of the present invention;
FIG. 9b is a schematic cross-sectional view of a via formed on the substrate of FIG. 7b according to a second embodiment of the present invention;
FIG. 10 is a schematic diagram of a second embodiment of a LCD panel corresponding to the one shown in FIG. 9;
FIG. 11a is a schematic cross-sectional view of a pixel region of a liquid crystal display panel after a second embodiment of the present invention is completed;
FIG. 11b is a schematic cross-sectional view of a TFT region of an LCD panel after the process is completed according to a second embodiment of the present invention;
fig. 12 is a schematic structural view of a liquid crystal display panel corresponding to fig. 11 according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings.
First embodiment
In a first embodiment of the present invention, there is provided a multi-domain vertical alignment mode liquid crystal display panel including an array substrate on which a plurality of pixel units are disposed, wherein each of the pixel units has a thin film transistor, a coupling capacitor wire, and a common electrode wire disposed therein,
each pixel unit comprises a first sub-pixel unit with a first sub-pixel electrode and a second sub-pixel unit with a second sub-pixel electrode, and the first sub-pixel electrode and the second sub-pixel electrode respectively form storage capacitors with the common electrode wiring;
in each pixel unit, the first sub-pixel electrode is configured to be electrically connected with the drain electrode of the thin film transistor and electrically connected with the coupling capacitor wiring; the second sub-pixel electrode is configured to form a coupling capacitance with the coupling capacitance wiring; when the thin film transistor is turned on, the first sub-pixel electrode receives a first voltage to form a first display region and simultaneously transmits the first voltage to the coupling capacitor wiring, and the second sub-pixel electrode obtains a second voltage by the coupling effect of the coupling capacitor formed with the coupling capacitor wiring to form a second display region
The common electrode wiring is overlapped with the first sub-pixel electrode and the second sub-pixel electrode, a hollow area used for containing the coupling capacitor wiring is arranged below the second sub-pixel electrode, the coupling capacitor wiring and the common electrode wiring are arranged discontinuously and are insulated from each other, and the common electrode wiring is formed by a transparent conductive layer.
In the following, an 8-domain MVA pixel structure obtained by improving the conventional 4-domain MVA pixel structure is taken as an example, and the number of domain regions and the number of sub-pixel electrodes are not limited in the specific implementation process, and can be set according to actual needs.
Fig. 2a is a schematic structural view of an 8-domain MVA display panel according to a first embodiment of the present invention, and as shown in the figure, a gate line 201, a data line 202, a common electrode wiring 203, a coupling capacitor wiring 204, a thin film transistor 205, and a pixel electrode 206 are disposed on an array substrate of a liquid crystal panel, and a notch 207 is disposed on the pixel electrode 206.
The structure of each device of the above-described display panel will be described in detail below.
The pixel electrode 206 covers the entire pixel area of the pixel unit, and is configured as shown in fig. 2b, each pixel unit includes a first sub-pixel unit having a first sub-pixel electrode 10 and a second sub-pixel unit having a second sub-pixel electrode 20, the first sub-pixel electrode 10 is configured to be electrically connected to the drain 2051 of the tft 205 and to be electrically connected to the coupling capacitor wire 204, and the second sub-pixel electrode 20 is configured to form a coupling capacitor with the coupling capacitor wire 204. The positional relationship of the common electrode wiring 203, the coupling capacitance wiring 204, and the pixel electrode may be: the common electrode wiring 203 overlaps the first sub-pixel electrode 10 and the second sub-pixel electrode 20, a hollow area for accommodating the coupling capacitor wiring 204 (shown as a triangular area in fig. 2 a) is arranged below the second sub-pixel electrode 20 under the common electrode wiring 203, and the coupling capacitor wiring 204 is insulated from the common electrode wiring 203.
When the thin film transistor 205 is turned on, the first sub-pixel electrode 10 receives a first voltage to form a 4-domain first display region; meanwhile, the first voltage is transmitted to the coupling capacitance wiring 204, a second voltage is obtained through the coupling effect of the coupling capacitance formed by the coupling capacitance wiring 204 and the second subpixel electrode 20, and the second subpixel electrode 20 receives the second voltage to form a 4-domain second display region. It is because the voltages applied to the first sub-pixel electrode 10 and the second sub-pixel electrode 20 are different, which results in two different 4-domain display regions, i.e., 8-domain display regions.
Specifically, the gate wiring 2053 of the thin film transistor 205 is electrically connected to the gate line 201, the source 2052 is electrically connected to the data line 202, the drain 2051 is communicated with the first via hole 208, the coupling capacitor wiring 204 is communicated with the second via hole 209, the first sub-pixel electrode 10 is electrically connected to the drain 2051 of the thin film transistor 205 through the first via hole 208, and the first sub-pixel electrode 10 is electrically connected to the coupling capacitor wiring 204 through the second via hole 209.
In the prior art, increasing the storage capacitance is helpful to improve the display quality, but increasing the area of the common electrode reduces the transmittance, so in this embodiment, the common electrode wiring is formed by the etched transparent conductive layer, on one hand, the storage capacitance of the display device is improved by increasing the area of the common electrode wiring, and by dividing the pixel electrode into 2 or more regions, the display quality of the panel is improved by forming a display region with 8 domains or even more, on the other hand, the transmittance of the panel is improved by forming the common electrode wiring by using a large-area transparent conductive material with high transmittance, that is, the display quality and the transmittance of the liquid crystal display panel can be improved simultaneously.
Preferably, the coupling capacitor wiring 204 may also be formed by an etched transparent conductive layer, and the coupling capacitor wiring 204 and the common electrode wiring 203 are disposed in the same layer, which is helpful for improving the transmittance of the liquid crystal display panel because the transparent conductive material has high transmittance.
Preferably, the gate wire 2053 of the thin film transistor 205 includes a transparent conductive layer and a gate metal, and has a double-layer structure of the transparent conductive layer and the gate metal, which is provided to save the process cost when the process is performed.
As a preferable mode, the pixel electrode on the array substrate is provided with a notch.
The first sub-pixel unit forms the first display area divided into a plurality of domains through the ridge-shaped protrusion and/or the notch; the second sub-pixel unit forms a second display area divided into a plurality of domains through the ridge-shaped protrusion and/or the notch.
Therefore, the liquid crystal display panel provided by the embodiment can simultaneously improve the display quality and the transmittance of the liquid crystal display panel.
In summary, the liquid crystal display panel of the multi-domain vertical alignment mode of the present embodiment has practical guiding significance in the field of liquid crystal display technology.
Second embodiment
Fig. 3 is a flowchart of a method for manufacturing a multi-domain vertical alignment mode lcd panel according to a second embodiment of the present invention, as shown in fig. 3, the method may include the following steps:
step S310, after depositing a layer of transparent conductive material on the substrate to form a transparent conductive layer, continuously depositing a grid metal to form a grid metal layer;
the cross-sectional structure of the pixel region of the liquid crystal display panel obtained through the process of step S310 is as shown in fig. 4a, and a gate metal layer 11 and a transparent conductive layer 12 are formed on the glass substrate of the pixel region; the cross-sectional structure of the tft area of the lcd panel obtained through the process of step S310 is as shown in fig. 4b, and a gate metal layer 21 and a transparent conductive layer 22 are formed on the glass substrate of the tft area.
In step S320, the transparent conductive layer and the gate metal layer are etched by using a multi-gray scale photo mask process, the exposed transparent conductive layer 12 is formed by etching away the gate metal layer 11 in the pixel region to form the common electrode wiring 203 and the coupling capacitor wiring 204, and the etched transparent conductive layer 22 and the gate metal layer 21 in the tft region form the gate wiring 2053 having a double-layer structure.
In step S330, a gate insulating material is deposited to form a gate insulating layer.
The cross-sectional structure of the pixel area of the liquid crystal display panel obtained through the processes of step S320 and step S330 is shown in fig. 5a, and the specific process is that after the transparent conductive layer and the gate metal layer in fig. 4a are etched through 1 photo mask by using the multi-gray-scale photo mask process, the gate metal layer 11 in the pixel area is etched away, and the exposed transparent conductive layer 12 forms the common electrode wiring 203 and the coupling capacitor wiring 204. The method is realized by adopting a multi-gray-scale photomask process through 1 photomask, and can also be realized by matching with the existing 4 photomasks or 5 photomasks.
The pixel unit structure formed through the processes of steps S320 and S330 is shown in fig. 6, and includes: the gate line 201, the common electrode wiring 203 and the coupling capacitor wiring 204, wherein the coupling capacitor wiring 204 (shown as a triangular area in fig. 6) is located in a hollow-out area of the common electrode wiring 203, the shape of the hollow-out area is not limited, and the shape of the coupling capacitor wiring 204 is not limited as long as the coupling capacitor wiring 204 is not electrically connected with the common electrode wiring 203; the common electrode wiring 203 and the coupling capacitance wiring 204 are provided on the same layer, and the coupling capacitance wiring 204 and the common electrode wiring 203 are disconnected and insulated.
The cross-sectional structure of the tft area of the lcd panel obtained through the processes of steps S320 and S330 is shown in fig. 5b, and the specific process includes etching the transparent conductive layer and the gate metal layer in fig. 4b through 1 mask by using a multi-tone mask process, and then forming a gate wiring 2053 with a dual-layer structure.
In the invention, the gate line 201, the gate wiring 2053, the common electrode wiring 203 and the coupling capacitor wiring 204 are manufactured in the same photomask manufacturing process, so that the process steps can be reduced, and the process cost can be saved.
After the common electrode wiring 203, the coupling capacitor wiring 204 and the gate wiring 2053 are formed, a gate insulating layer (GI) is formed by depositing a layer of gate insulating material using a chemical vapor deposition process
Step S340, performing a semiconductor layer process and a source/drain process to form an active layer, a data line 202, a drain 2051, and a source 2052, and then depositing a passivation material to form a passivation layer;
the cross-sectional structure of the pixel region of the liquid crystal display panel obtained through the process of step S340 is as shown in fig. 7a, and the data line 202 is formed through a source-drain process.
The cross-sectional structure of the tft area of the lcd panel obtained through the process of step S340 is as shown in fig. 7b, and the specific process includes performing a semiconductor layer process to form the active layer 42, and forming the source electrode 2052 and the drain electrode 2051 through a source/drain electrode process.
And then a passivation layer is coated to form the data line 202 and the thin film transistor 205. The panel structure formed through the process of step S340 is shown in fig. 8, and further includes: a data line 202 and a thin film transistor 205.
Step S350, performing a via hole process, wherein the drain 2051 is communicated with a first via hole 208, and the coupling capacitor wire 204 is communicated with a second via hole 209, so that the first sub-pixel electrode 10 is electrically connected to the drain 2051 of the thin film transistor 205 through the first via hole 208, and is electrically connected to the coupling capacitor wire 204 through the second via hole 209;
the cross-sectional structure of the pixel region of the lcd panel obtained through the via process of step S350 is as shown in fig. 9a, and the specific process is to etch away a portion of the gate insulating layer and a portion of the passivation layer covered above the coupling capacitor wire 204 to form a second via 209.
The cross-sectional structure of the tft area of the lcd panel obtained through the via hole process in step S350 is as shown in fig. 9b, and the specific process includes etching away a portion of the passivation layer covering the drain electrode 2051 to form the first via hole 208.
The panel structure formed by the via process of step S350 is shown in fig. 10, and further includes: a first via 208 and a second via 209.
In step S360, at least two independent sub-pixel electrodes are formed in the pixel region on the passivation layer by using a transparent conductive material, each sub-pixel electrode forms a storage capacitor with the common electrode wiring 203, and the second sub-pixel electrode 20 is configured to form a coupling capacitor with the coupling capacitor wiring 204.
The cross-sectional structure of the pixel area of the liquid crystal display panel obtained through the process of step S360 is as shown in fig. 11a, and the specific process includes forming a pixel electrode on the passivation layer by using a transparent conductive material, where the pixel electrode is as shown in fig. 2b, the pixel electrode is divided into at least two independent sub-pixel electrodes including a first sub-pixel electrode 10 and a second sub-pixel electrode 20, and the first sub-pixel electrode 10 is electrically connected to the coupling capacitor wiring 204 through the second via 209 etched in step S150.
The cross-sectional structure of the tft area of the lcd panel obtained through the process of step S360 is as shown in fig. 11b, and the specific process is that the first sub-pixel electrode 10 is electrically connected to the drain 2051 of the tft 205 through the first via hole 208.
The display panel manufacturing process is completed to obtain the 8-domain MVA display panel structure shown in fig. 12, further comprising: and a pixel electrode 206. On one hand, the storage capacitance is increased, and on the other hand, the transmittance of the panel is also increased because the common motor wiring and the pixel electrode wiring are both formed by transparent conductive materials with high transmittance.
As a preferred scheme, the multi-gray scale photomask process comprises:
semi-exposure (Half-Tone) using a semi-permeable membrane;
or, a micro-slit below the resolution of the exposure machine is made, and a part of the light source is shielded by the micro-slit portion to achieve the half-exposure effect (Gray-Tone).
The above description is only an embodiment of the present invention, and the protection scope of the present invention is not limited thereto, and any person skilled in the art should modify or replace the present invention within the technical specification of the present invention.
Claims (8)
1. A liquid crystal display panel of a multi-domain vertical orientation mode comprises an array substrate, wherein a plurality of pixel units are arranged on the array substrate, a thin film transistor, a coupling capacitor wiring and a common electrode wiring are arranged in each pixel unit, each pixel unit comprises a first sub-pixel unit with a first sub-pixel electrode and a second sub-pixel unit with a second sub-pixel electrode, and the first sub-pixel electrode and the second sub-pixel electrode respectively form a storage capacitor with the common electrode wiring; in each pixel unit, the first sub-pixel electrode is configured to be electrically connected with the drain electrode of the thin film transistor and electrically connected with the coupling capacitor wiring; the second sub-pixel electrode is configured to form a coupling capacitance with the coupling capacitance wiring; the common electrode wiring is overlapped with the first sub-pixel electrode and the second sub-pixel electrode, a hollow area for accommodating the coupling capacitance wiring is arranged below the second sub-pixel electrode, the coupling capacitance wiring is insulated from the common electrode wiring, and the common electrode wiring is formed by a transparent conductive layer; the coupling capacitance wiring is formed by a transparent conductive layer, and the coupling capacitance wiring and the common electrode wiring are arranged on the same layer.
2. The liquid crystal display panel according to claim 1, wherein the gate wiring of the thin film transistor includes a transparent conductive layer and a gate metal.
3. The liquid crystal display panel according to claim 1, wherein a drain of the thin film transistor is connected to a first via hole, the coupling capacitor wire is connected to a second via hole, the first subpixel electrode is electrically connected to the drain of the thin film transistor through the first via hole, and the first subpixel electrode is electrically connected to the coupling capacitor wire through the second via hole.
4. The liquid crystal display panel according to claim 1, further comprising a color film substrate, wherein the color film substrate is provided with a ridge-shaped protrusion.
5. The liquid crystal display panel according to claim 4, wherein the first subpixel electrode and the second subpixel electrode on the array substrate are provided with a cutout.
6. The liquid crystal display panel according to claim 5, wherein the first sub-pixel unit forms a first display region divided into a plurality of domains by the ridge protrusion and/or the notch; the second sub-pixel unit forms a second display area divided into a plurality of domains through the ridge-shaped protrusion and/or the notch.
7. A method for manufacturing a multi-domain vertical alignment mode liquid crystal display panel is characterized by comprising the following steps: depositing a layer of transparent conductive material on the substrate to form a transparent conductive layer, and then continuously depositing gate metal to form a gate metal layer; etching the transparent conductive layer and the grid metal layer by adopting a multi-gray scale photomask process, forming a common electrode wiring and a coupling capacitor wiring by the exposed transparent conductive layer after the grid metal layer of the pixel region is etched, and forming a grid wiring with a double-layer structure by the etched transparent conductive layer and the etched grid metal layer of the thin film transistor region; the common electrode wiring is provided with a hollow-out area used for accommodating the coupling capacitor wiring below the second sub-pixel electrode, and the coupling capacitor wiring is insulated from the common electrode wiring; depositing a layer of gate insulating material to form a gate insulating layer; carrying out a semiconductor layer process and a source drain process, and depositing a layer of passivation material to form a passivation layer after forming an active layer, a data line and a source drain; performing a via hole process, wherein the drain is communicated with a first via hole, and the coupling capacitor wiring is communicated with a second via hole, so that the first sub-pixel electrode is electrically connected with the drain of the thin film transistor through the first via hole and is electrically connected with the coupling capacitor wiring through the second via hole; and at least two independent sub-pixel electrodes are formed in the pixel area on the passivation layer by using a transparent conductive material, each sub-pixel electrode forms a storage capacitor with the common electrode wiring, and the second sub-pixel electrode is configured to form a coupling capacitor with the coupling capacitor wiring.
8. The method of claim 7, wherein the multi-tone mask process comprises: semi-exposing with a semi-permeable film; or, the micro-slit below the resolution of the exposure machine is made, and a part of the light source is shielded by the micro-slit part, so as to achieve the semi-exposure effect.
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| MX383732B (en) * | 2017-12-07 | 2025-03-14 | Boe Technology Group Co Ltd | DISPLAY PANEL HAVING A LIGHT MODULATING REGION, DISPLAY APPARATUS, METHOD FOR MODULATING THE DISPLAY CONTRAST OF THE DISPLAY PANEL, AND METHOD FOR MANUFACTURING THE DISPLAY PANEL. |
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| CN201298129Y (en) * | 2008-12-04 | 2009-08-26 | 上海广电光电子有限公司 | Multi-domain vertical alignment liquid crystal display panel |
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| KR100925463B1 (en) * | 2003-02-17 | 2009-11-06 | 삼성전자주식회사 | Liquid crystal display |
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| CN201298129Y (en) * | 2008-12-04 | 2009-08-26 | 上海广电光电子有限公司 | Multi-domain vertical alignment liquid crystal display panel |
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