CN106873267B

CN106873267B - Display panel

Info

Publication number: CN106873267B
Application number: CN201510924046.7A
Authority: CN
Inventors: 余翊菱; 林峻良; 蔡嘉豪
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2015-12-14
Filing date: 2015-12-14
Publication date: 2021-02-19
Anticipated expiration: 2035-12-14
Also published as: CN106873267A

Abstract

The present invention provides a display panel, comprising: a substrate, comprising a display area and a non-display area; a plurality of scan lines, arranged in the display area; a plurality of data lines, arranged in the display area and staggered with the scan lines to define a plurality of pixel units; a first common signal line, arranged in the display area and staggered with the data lines; and a first common signal pad, arranged in one of the pixel units in the display area, electrically connected to the first common signal line, and the first common signal pad is located between two adjacent data lines of the data lines; wherein the first common signal pad has different minimum distances from the two adjacent data lines.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a display panel having a special design for a position of a first common signal pad in a display area.

Background

With the continuous progress of display technology, all display panels are developed to be small, thin and light, so that the mainstream display devices in the market are developed into thin displays such as liquid crystal display panels, organic light emitting diode display panels or inorganic light emitting diode display panels from the conventional cathode ray tubes. Among them, thin displays are applicable to a wide range of fields, and display panels such as mobile phones, notebook computers, video cameras, music players, mobile navigation devices, and televisions, which are used in daily life, are mostly used.

Although the lcd panel or the oled display panel is a common display panel in the market, especially the technology of the lcd panel is more mature, as the display panel is continuously developed and the requirement of the consumer for the display quality of the display panel is gradually increased, the manufacturers are not forced to develop the display panel with higher display quality. Among them, the arrangement and design of the elements in the display area of the display panel become one of the factors affecting the overall efficiency of the display panel.

In view of the above, there is still a need to improve the configuration and design of the elements in the display area of the display panel to further improve the display quality of the display panel.

Disclosure of Invention

The present invention is directed to a display panel, in which the position of a first common signal pad in a display region is designed to avoid the problem of an excessive parasitic capacitance between a data line and a first transparent conductive layer above the data line.

The display panel of the present invention includes: a substrate including a display region and a non-display region; a plurality of scan lines disposed in the display area; a plurality of data lines arranged in the display area and staggered with the scanning lines to define a plurality of pixel units; a first common signal line disposed in the display region and interlaced with the data lines; the first common signal connecting pad is arranged in one of the pixel units in the display area and is electrically connected with the first common signal line, and the first common signal connecting pad is positioned between two adjacent data lines of the data lines; wherein the first common signal pad and the two adjacent data lines have different minimum distances respectively.

In the display panel of the invention, the first common signal line includes a first metal layer, the first common signal pad includes a second metal layer, wherein a first insulating layer is disposed between the first metal layer and the second metal layer and includes a first hole, and the second metal layer directly contacts the first metal layer through the first hole. In addition, a second insulating layer is arranged on the second metal layer and comprises a second hole, the second metal layer is directly contacted with a first transparent conducting layer through the second hole, and the second hole is partially overlapped with the first hole. Furthermore, a third insulating layer is arranged on the second insulating layer and comprises a third hole, one of the first transparent conducting layer and the second transparent conducting layer is arranged between the third insulating layer and the second insulating layer, the other one of the first transparent conducting layer and the second transparent conducting layer is arranged on the third insulating layer, and the first transparent conducting layer is directly contacted with the second transparent conducting layer through the third hole. Wherein the third hole is not overlapped with the first hole and the second hole.

In the display panel of the invention, the minimum distances between the first common signal pad and the two adjacent data lines are designed to be different, so as to avoid the problem of overlarge parasitic capacitance between the data line and the first transparent conductive layer above the data line. More specifically, a first common signal pad may be disposed in a pixel unit of the display panel; when a common signal is to be transmitted from the first metal layer to the second transparent conductive layer, the signal can be transmitted to the second metal layer through the first hole which enables the first metal layer to be in direct contact with the second metal layer, then the signal can be transmitted to the first transparent conductive layer through the second hole which enables the second metal layer to be in direct contact with the first transparent conductive layer, and then the signal can be transmitted to the second transparent conductive layer through the third hole which enables the first transparent conductive layer to be in direct contact with the second transparent conductive layer. Therefore, in a pixel unit, in addition to the first hole corresponding to the first common signal pad, a third hole capable of electrically connecting the first transparent conductive layer and the second transparent conductive layer is required to be disposed. If the minimum distance between the first common signal pad and the two adjacent data lines is designed to be the same, the third hole is closer to the data lines; although the data line is isolated from the transparent conductive layer by the insulating layer, the sidewall of the hole of the insulating layer is an inclined sidewall, and the upper portion of the data line is an inclined sidewall when the third hole is located closer to the data line. Therefore, in the display panel of the invention, the minimum distance between the first common signal pad and the two adjacent data lines is designed to be different, so that the position of the third hole is far away from the data lines, the problem of poor shielding performance of the insulating layer between the first and second transparent conductive layers and the data lines is avoided, and the parasitic capacitance between the first and second transparent conductive layers and the data lines is further reduced.

In the display panel of the invention, in a cross-sectional view or a top view, the boundary of the second hole exceeds the edge of the first metal layer; in other words, the boundary of the second hole is located outside the first metal layer; in terms of replacement, the edge of the first metal layer is located in the second hole.

In addition, the display panel of the invention may further include a second common signal pad, a third common signal pad, a second common signal line and a third common signal line, wherein the second common signal line and the third common signal line are disposed in the display region and are staggered with the data lines, and the second common signal pad and the third common signal pad are disposed in the display region and are electrically connected to the second common signal line and the third common signal line, respectively; the second common signal pad is located between the first common signal pad and the third common signal pad, and a distance between the first common signal pad and the second common signal pad is not equal to a distance between the second common signal pad and the third common signal pad.

In the display panel of the invention, the first common signal line includes a protrusion portion located at a position crossing the data lines and protruding toward a length direction of the data lines.

In addition, in the display panel of the invention, at the first hole, an included angle between the first metal layer and the second metal layer is greater than 0 degree and less than 45 degrees.

Furthermore, in the display panel of the present invention, the first common signal pad has a first edge and a second edge, and the first edge is opposite to the second edge, and the data lines include a first data line and a second data line, wherein the first common signal pad is located between the first data line and the second data line, the first data line is relatively adjacent to the first edge, and the second data line is relatively adjacent to the second edge; the minimum distances between the first data line and the first edge and between the second data line and the second edge in the extending direction of the scanning lines are respectively a first distance and a second distance. In one embodiment, when the width of the pixel units in the extending direction of the scan lines is 300 to 320 μm, the difference between the first distance and the second distance is 1.5 to 299 μm; in another embodiment, when the width of the pixel units in the extending direction of the scan lines is 200 to 220 μm, the difference between the first distance and the second distance is 1.5 to 196.17 μm; in yet another embodiment, when the width of the pixel units in the extending direction of the scan lines is 145 to 165 μm, the difference between the first distance and the second distance is 1.5 to 144.75 μm; in a further embodiment, when the width of the pixel units in the extending direction of the scan lines is 100 to 120 μm, the difference between the first distance and the second distance is 1.5 to 93.33 μm. Here, the first common signal pad further has a third edge, and two ends of the third edge intersect with the first edge and the second edge respectively; wherein the third edge is substantially parallel to the extending direction of the scan lines.

Drawings

Fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention.

Fig. 2 is a top view of a display area of a thin film transistor substrate of a display panel according to an embodiment of the invention.

Fig. 3A and 3B are enlarged views of a partial region of a thin film transistor substrate of a display panel according to an embodiment of the invention.

Fig. 4 and fig. 5 are schematic cross-sectional views of a partial region of a thin film transistor substrate of a display panel according to an embodiment of the invention.

Fig. 6 is an enlarged view of a partial region of the thin film transistor substrate of the display panel according to a comparative example of the present invention.

Fig. 7 is a schematic cross-sectional view of a partial region of a thin film transistor substrate of a display panel according to a comparative example of the present invention.

[ notation ] to show

1, 21

substrate

11, 11a scanning line

12 data line 121 first data line

122 second data line 13a first common signal line

13b second common signal line 13c third common signal line

131 protrusion 14a first common signal pad

14b second common signal pad 14c third common signal pad

141 first edge 142 second edge

143 third edge 2 to side substrate

22 first metal layer 22a edge

23 first insulating layer 231 first hole

24 second metal layer 25 second insulating layer

25a boundary 251 second hole

26 insulating layer 26a hole sidewall

261, 262 holes 27 transparent conductive layer

28 third insulating layer 281 third hole

29 transparent conductive layer 3 display layer

AA display area B non-display area

C position D1 first distance

D2 second distance P pixel unit

R1 region S1, S2 spacing

X direction of extension and Y direction of extension

W, W1, W2, W3, W4, W5 and width theta

W6

Detailed Description

The following description is provided for illustrative purposes only, and is not intended to limit the scope of the present disclosure. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.

Furthermore, ordinal numbers such as "first," "second," "third," etc., used in the specification and claims to modify a component of a request do not by itself connote any preceding ordinal number of the request component, nor do they denote any order in which a request component is currently presented or in which a request component having a certain name is currently presented or in which another request component having a same name is currently presented.

Fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention. The display panel of the embodiment includes: the display device comprises a substrate 1, a display area AA, a non-display area B and a control unit, wherein the non-display area B is arranged around the display area AA; a counter substrate 2 disposed opposite to the substrate 1; and a display layer 3 disposed between the counter substrate 2 and the substrate 1. In this embodiment, the substrate 1 may be a thin film transistor substrate on which a thin film transistor structure (not shown) is disposed, and the opposite substrate 2 may be a color filter substrate on which a color filter layer (not shown) is disposed; however, in other embodiments of the present invention, a color filter layer (not shown) may also be disposed on the substrate 1, in which case the substrate 1 is a color filter on array (COA) integrated with a color filter array. In addition, the display layer 3 in the display panel of the embodiment may be a liquid crystal layer, an organic light emitting diode element layer or an inorganic light emitting diode element layer. When the display layer 3 in the display panel of this embodiment is a liquid crystal layer, the display panel of this embodiment further includes a backlight module disposed below the substrate 1. Next, the structural features of the elements provided above the display area AA of the substrate 1 will be described in detail.

Fig. 2 is a top view of a display area of a thin film transistor substrate of a display panel according to an embodiment of the invention. As shown in fig. 1 and fig. 2, the display panel of the present embodiment further includes: a plurality of scan lines 11 disposed in the display area AA; a plurality of data lines 12 disposed in the display area AA and interlaced with the scan lines 11 to define a plurality of pixel units P; at least one first common signal line 13a disposed in the display area AA and crossing the data line 12; and a first common signal pad 14a disposed in one of the pixel units P in the display area AA and electrically connected to the first common signal line 13a, wherein the first common signal pad 14a is located between two adjacent data lines 12 of the data lines 12. Accordingly, the first common signal pad 14a can transmit the signal on the first common signal line 13a to, for example, a transparent conductive layer connected thereto. The arrangement and operation of the first common signal pad 14a will be described in detail later.

FIGS. 3A and 3B are enlarged views of a region R1 shown in FIG. 2, wherein FIG. 3B is the same as FIG. 3A for clarity, and the difference is that FIG. 3B does not show the fill lines in FIG. 3A; FIG. 4 is a cross-sectional view taken along line L1-L2 shown in FIG. 3A; FIG. 5 is a sectional view of the L3-L4 of FIG. 3A. As shown in fig. 3A to 5, in the display panel of the present invention, a first metal layer 22 is formed on a substrate 21, wherein the first metal layer 22 forms a scan line 11 and a first common signal line 13A through processes such as exposure, development and etching. A first insulating layer 23 is formed on the first metal layer 22, and the first insulating layer 23 has a first hole 231 to expose a portion of the first metal layer 22 (e.g., the first common signal line 13 a). Next, a second metal layer 24 is formed on the first insulating layer 23, wherein the second metal layer 24 is formed by exposing, developing and etching processes to form the data line 12 (as shown in fig. 2) including the first data line 121 and the second data line 122 and the first common signal pad 14 a. A second insulating layer 25 is formed on the second metal layer 24, and the second insulating layer 25 has a second hole 251. An insulating layer 26 is formed on the second insulating layer 25, and the insulating layer 26 has

holes

261 and 262 and a hole sidewall 26 a. Next, a transparent conductive layer 27 is formed over the insulating layer 26. The third insulating layer 28 is formed on the transparent conductive layer 27, and the third insulating layer 28 has a third hole 281. Next, a transparent conductive layer 29 is formed on the third insulating layer 28.

In the present embodiment, the substrate 21 can be made of a substrate material such as glass, plastic, flexible material, etc. The first insulating layer 23, the second insulating layer 25, the third insulating layer 28, and the insulating layer 26 can be made of an insulating layer material such as an oxide (e.g., silicon oxide or aluminum oxide), a nitride (e.g., silicon nitride), or an oxynitride (e.g., silicon oxynitride). The first metal layer 22 and the second metal layer 24 can be made of conductive materials, such as metals, alloys, metal oxides, metal oxynitrides, or other electrode materials. The transparent conductive layer 29 and the transparent conductive layer 27 can be made of a transparent conductive electrode material such as ITO, IZO or ITZO. However, in other embodiments of the present invention, the material of the foregoing elements is not limited thereto.

As shown in fig. 4, in the display panel of the present embodiment, the third insulating layer 28 is disposed on the second insulating layer 25 and includes a third hole 281, the transparent conductive layer 27 is disposed between the third insulating layer 28 and the second insulating layer 25, the transparent conductive layer 29 is disposed on the third insulating layer 28, and the transparent conductive layer 29 directly contacts the transparent conductive layer 27 through the third hole 281.

In addition, as shown in fig. 3A and 5, in the display panel of the present embodiment, the first common signal line 13A is formed by a first metal layer 22, the first common signal pad 14a is formed by a second metal layer 24, wherein the first insulating layer 23 is disposed between the first metal layer 22 and the second metal layer 24 and includes a first hole 231, and the second metal layer 24 directly contacts the first metal layer 22 through the first hole 231. In other words, the first common signal pad 14a is electrically connected to the first common signal line 13 through the first hole 231. In addition, the second insulating layer 25 is disposed on the second metal layer 24 and includes a second hole 251, and the second metal layer 24 directly contacts the transparent conductive layer 29 through the second hole 251. In other words, the first common signal line 13a is electrically connected to the transparent conductive layer 29 through the first common signal pad 14 a. Here, the transparent conductive layer 27 shown in fig. 4 is not formed at the position where the first common signal pad 14a is formed.

In addition, in the display panel of the embodiment, as shown in fig. 3A and 3B, the first common signal pad 14a has a first edge 141 and a second edge 142, and the first edge 141 is opposite to the second edge 142, the first common signal pad 14a is located between the first data line 121 and the second data line 122, the first data line 121 is relatively adjacent to the first edge 141, and the second data line 122 is relatively adjacent to the second edge 142. Furthermore, the first common signal pad 14a further has a third edge 143, and two ends of the third edge 143 intersect the first edge 141 and the second edge 142 respectively; the third edge 143 is parallel to the extending direction X of the scan line 11. The minimum distances between the first data line 121 and the first edge 141, and between the second data line 122 and the second edge 142 in the extending direction X of the scan line 11 are the first distance D1 and the second distance D2, respectively.

As shown in fig. 3A to 5, when a common signal is to be transmitted from the first common signal line 13A (the first metal layer 22 of fig. 5) to the transparent conductive layer 27, the first common signal pads 14a (the second metal layer 24 of fig. 5) are electrically connected to each other by directly contacting the first metal layer 22 through the first holes 231, so that the common signal is transmitted from the first metal layer 22 to the first common signal pads 14a (the second metal layer 24 of fig. 5); then, the first common signal pads 14a (the second metal layer 24 in fig. 5) are electrically connected to the transparent conductive layer 29 through the second holes 251, so that the common signals transmitted to the second metal layer 24 are further transmitted to the transparent conductive layer 29; then, the transparent conductive layer 29 is electrically connected to the transparent conductive layer 27 through the third hole 281 and the transparent conductive layer 27, so that the common signal transmitted to the transparent conductive layer 29 is further transmitted to the transparent conductive layer 27.

In this embodiment, the transparent conductive layer 27 serves as a common electrode layer, and the transparent conductive layer 29 serves as a pixel electrode layer. In addition, in the present embodiment, the transparent conductive layer 27 is disposed between the third insulating layer 28 and the second insulating layer 25, and the transparent conductive layer 29 is disposed on the third insulating layer 28; however, in other embodiments of the present invention, as long as the transparent conductive layer 29, the transparent conductive layer 27, the first metal layer 22 and the second metal layer 24 are electrically connected to each other as described above, the arrangement of the transparent conductive layer 29 and the transparent conductive layer 27 is not limited to the above-mentioned relation shown in fig. 4, and one of them may be disposed between the third insulating layer 28 and the second insulating layer 25, and the other may be disposed on the third insulating layer 28.

As shown in fig. 3A to 5, in a pixel unit, in addition to the first hole 231 corresponding to the first common signal pad 14a (and the second metal layer 24 included therein), a third hole 281 capable of electrically connecting the transparent conductive layer 29 and the transparent conductive layer 27 is required to be disposed, and the first hole 231 and the third hole 281 are disposed on the first common signal line 13A and are disposed in a staggered manner.

FIG. 6 is an enlarged view of a portion of a TFT substrate of a display panel according to a comparative example of the present invention, which is the same view as FIG. 3A according to an embodiment of the present invention; FIG. 7 is a cross-sectional view taken along line L1-L2 of FIG. 6, which is the same view as FIG. 4 of an embodiment of the present invention. As shown in fig. 6, if the first common signal pad 14a is disposed between the adjacent first data line 121 and second data line 122, that is, the minimum distances (i.e., the first distance D1 and the second distance D2) between the first common signal pad 14a and the adjacent first data line 121 and second data line 122 are designed to be the same, the third hole 281 is located closer to the first data line 121; as shown in fig. 6 and 7, although the insulating layer 26 is disposed between the first data line 121 (the second metal layer 24) and the transparent conductive layer 27, since the sidewall 26a of the hole of the insulating layer 26 is an inclined sidewall, when the third hole 281 is located closer to the first data line 121 (the second metal layer 24), the sidewall 26a of the hole of the insulating layer 26 is located above the first data line 121 (the second metal layer 24), and the inclined sidewall 26a of the hole is used to isolate the thickness of the insulating layer 26 between the first data line 121 (the second metal layer 24) and the transparent conductive layer 27; particularly, if the width of the pixel unit in the extending direction X of the scan line 11 is reduced, under the condition that the size of the first common signal pad 14a is similar, the hole 261 of the insulating layer 26 may be directly located above the first data line 121 (the second metal layer 24), so that a portion of the first data line 121 (i.e., the second metal layer 24) is even isolated from the transparent conductive layer 27 only through the second insulating layer 25. Therefore, in the case of the present comparative example, the insulating layer 26 between the transparent conductive layer 27 and the first data line 121 (i.e., the second metal layer 24) has poor shielding property, and thus the parasitic capacitance is too large.

In contrast to the embodiment of the present invention, as shown in fig. 3B and fig. 4, the first common signal pad 14a and the adjacent first data line 121 and second data line 122 respectively have different minimum distances (i.e., the first distance D1 and the second distance D2), and particularly the first distance D1 is greater than the second distance D2, so that the third hole 281 is located farther away from the first data line 121 (the second metal layer 24), thereby avoiding the problem of poor shielding performance between the transparent conductive layer 27 and the first data line 121 (the second metal layer 24) due to the thinner sidewall 26a of the hole of the insulating layer 26 in the comparative example, and further reducing the parasitic capacitance between the transparent conductive layer 27 and the first data line 121 (the second metal layer 24).

As shown in fig. 3B, the first distance D1 and the second distance D2 are related to the widths of the first data line 121, the second data line 122 and the first common signal pad 14a in the extending direction X of the scan line 11, and are also related to the position of the third hole 281 and the aperture thereof in the extending direction X of the scan line 11. In one embodiment, the distance width W1 between the third hole 281 and the first data line 121 is at least 1 μm (micrometer) or more in the extending direction X of the scan line 11; the aperture width W2 of the third holes 281 is at least 1.5 μm or more; the distance width W3 between the third via 281 and the first common signal pad 14a is at least 2 μm or more; the width W4 of the first common signal pad 14a is at least 3.5 μm or more; the distance width W5 between the first common signal pad 14a and the second data line 122 is at least 2 μm or more; the width W6 of the first data line 121 and the second data line 122 is at least 2 μm or more; the width W of the pixel unit is the sum of the widths W1, W2, W3, W4, W5 and W6. Therefore, in the present embodiment, the upper and lower limits of the first distance D1 can be respectively shown by the following formulas (1) and (2), and the second distance D2 is equivalent to the width W5.

First distance D1 lower limit W1+ W2+ W3 (1)

The upper limit of the first distance D1 is W-W6-W5-W4 (2)

For example, when the width W of the pixel unit in the extending direction X of the scan line 11 is 309 μm, the difference between the first distance D1 and the second distance D2 can be 1.5-299 μm; when the width W of the pixel unit is 206 μm, the difference between the first distance D1 and the second distance D2 can be 1.5 to-196.17 μm; when the width W of the pixel unit is 155 μm, the difference between the first distance D1 and the second distance D2 can be 1.5-144.75 μm; when the width W of the pixel unit is 103 μm, the difference between the first distance D1 and the second distance D2 can be 1.5-93.33 μm. If the process variability is considered, the difference between the first distance D1 and the second distance D2 may be 1.5-299 μm when the width W of the pixel unit in the extending direction X of the scan line 11 is 300-320 μm; when the width W of the pixel unit is 200-220 μm, the difference between the first distance D1 and the second distance D2 can be 1.5-196.17 μm; when the width W of the pixel unit is 145-165 μm, the difference between the first distance D1 and the second distance D2 can be 1.5-144.75 μm; when the width W of the pixel unit is 100 to 120 μm, the difference between the first distance D1 and the second distance D2 is 1.5 to 93.33 μm.

The upper and lower limits of the widths W, W1, W2, W3, W4, W5, W6 and the first distance D1 are values obtained according to the current patterning process and the required electrical relationship among the devices; however, if the patterning process is improved and the electrical relationship between the elements is changed, the widths W, W1, W2, W3, W4, W5, W6, the upper and lower limits of the first distance D1, and the difference between the first distance D1 and the second distance D2 are not limited to the values disclosed in the present invention.

In addition, in an embodiment of the invention, as shown in fig. 2, the display panel of the embodiment further includes a second common signal pad 14b, a third common signal pad 14c, a second common signal line 13b, and a third common signal line 13 c. Here, the structures of the second common signal pad 14b and the third common signal pad 14c are the same as the first common signal pad 14a, and thus, are not described again. In addition, the second common signal line 13b and the third common signal line 13c are disposed in the display area AA (shown in fig. 1) and are staggered with the data line 12, and the second common signal pad 14b and the third common signal pad 14c are disposed in the display area AA (shown in fig. 1) and are electrically connected to the second common signal line 13b and the third common signal line 13c, respectively; wherein the second common signal pad 14b is located between the first common signal pad 14a and the third common signal pad 14c, and the distance between the first common signal pad 14a and the second common signal pad 14b is not equal to the distance between the second common signal pad 14b and the third common signal pad 14 c. Here, the "the distance between the first common signal pad 14a and the second common signal pad 14b is not equal to the distance between the second common signal pad 14b and the third common signal pad 14 c" is defined as follows: if the scan line 11a is taken as a reference, the first common signal pad 14a, the second common signal pad 14b and the third common signal pad 14C may respectively vertically correspond to positions C on the scan line 11a in a direction Y perpendicular to the extending direction X of the scan line 11, and the distances S1 and S2 between adjacent positions C are not equal.

As described above, in fig. 3A to 5, when a common signal is applied, the common signal can be transmitted to the transparent conductive layer 27 through the first common signal pad 14a, the second common signal pad 14b and the third common signal pad 14c (the second metal layer 24 in fig. 5), so that the voltage of the transparent conductive layer 27 is uniform; therefore, in the present embodiment, as shown in fig. 2, the distances between two adjacent first common signal pads 14a, second common signal pads 14b and third common signal pads 14c are not equal to each other, so as to avoid generating moire (mura) visible to human eyes.

In addition, in the present embodiment, as shown in fig. 3A, the first common signal line 13A further includes a protrusion 131 located at a position staggered with the first data line 121 and the second data line 122 and protruding toward the length direction (direction Y) of the first data line 121 or the second data line 122; thereby, the contact area between the first common signal line 13a and the first and

second data lines

121 and 122 is increased. Due to the arrangement of the first common signal line 13a, a height difference is generated at the intersection of the first common signal line 13a and the first and

second data lines

121 and 122 when the first and

second data lines

121 and 122 are formed; therefore, when the first common signal line 13a includes the protrusion 131 at the intersection, the protrusion 131 can increase the contact area between the first common signal line 13a and the first and

second data lines

121 and 122, so as to reduce the risk of wire breakage when forming the first and

second data lines

121 and 122. Meanwhile, the accumulation of the etching solution at the intersection can be prevented, so as to further reduce the risk of the disconnection of the first data line 121 and the second data line 122.

As shown in fig. 3A and fig. 5, in the display panel of the present embodiment, the second hole 251 and the first hole 231 are partially overlapped, i.e. they are designed to be shifted. In particular, in the cross-sectional view of fig. 5, the boundary 25a of the second hole 251 is beyond the edge 22a of the first metal layer 22, i.e. the boundary 25a of the second hole 251 is located outside the first metal layer 22, i.e. the edge 22a of the first metal layer 22 is located inside the second hole 251. In this case, as indicated by the dotted line in fig. 5, the edge 22a of the first metal layer 22 may have a height and a curvature of the second metal layer 24 formed thereon, so as to increase the surface area of the second metal layer 24; in this manner, when the transparent conductive layer 29 is formed on the second metal layer 24, since the surface area of the second metal layer 24 increases, the surface contact between the transparent conductive layer 29 and the second metal layer 24 also increases.

In addition, as shown in fig. 5, in the display panel of the embodiment, at the first hole 231, an included angle θ between the first metal layer 22 and the second metal layer 24 is greater than 0 degree and less than 45 degrees (0 ° < θ < 45 °). Generally, the first insulating layer 23 is made of a double-layer insulating material, the lower layer is a silicon nitride layer and the upper layer is a silicon oxide layer; when the first insulating layer 23 is patterned to form the first hole 231, undercutting (undercut) is easily generated due to the faster etching speed of the silicon nitride layer, which may affect the contact effect between the subsequently formed second metal layer 24 and the first metal layer 22. Therefore, in the present embodiment, by adjusting etching parameters, such as etching time, etching liquid composition, etching manner, and the like, the slope of the first hole 231 of the first insulating layer 2 is controlled such that the included angle θ between the first metal layer 22 and the second metal layer 24 is greater than 0 degree and less than 45 degrees; in this case, the risk of undercut can be reduced, the first metal layer 22 and the second metal layer 24 can be better contacted, and the risk of disconnection of the subsequent transparent conductive layer 29 due to too steep slope of the first hole 231 can be avoided.

In the present invention, the display panel manufactured in the foregoing embodiments can be applied to a liquid crystal display panel, an organic light emitting diode display panel, or an inorganic light emitting diode display panel. In addition, the display panel manufactured by the foregoing embodiment can also be used in combination with a touch panel as a touch display device. Meanwhile, the display panel or the touch display device manufactured in the foregoing embodiment of the invention may be applied to any electronic device that needs a display screen and is known in the art, such as a display, a mobile phone, a notebook computer, a video camera, a music player, a mobile navigation device, a television, and other electronic devices that need to display images.

The above-described embodiments are merely exemplary for convenience in explanation, and the scope of the claims of the present invention should be determined by the claims rather than by the limitations of the above-described embodiments.

Claims

1. A display panel, characterized in that, comprising:

a substrate, including a display area and a non-display area;

a first metal layer forming a plurality of scan lines, a first common signal line, a second common signal line and a third common signal line, wherein at least one scan line among the plurality of scan lines is along an extension direction extend;

a second metal layer forming a plurality of data lines, a first common signal pad, a second common signal pad and a third common signal pad;

Wherein the data lines are arranged in the display area and are arranged alternately with the scan lines to define a plurality of pixel units;

The first common signal line and the data lines are alternately arranged, the first common signal pad is arranged in one of the pixel units, and the first common signal pad is located in two phases of the data lines between adjacent data lines;

a first insulating layer disposed between the first metal layer and the second metal layer and including a first hole, wherein the first common signal pad is electrically connected to the first common signal line through the first hole connect;

a second insulating layer disposed on the second metal layer and including a second hole, wherein the first common signal pad is electrically connected to a first transparent conductive layer through the second hole; and

a third insulating layer disposed on the second insulating layer and including a third hole, one of the first transparent conductive layer and a second transparent conductive layer is disposed on the third insulating layer and the second insulating layer and another one is disposed on the third insulating layer, and the first transparent conductive layer is in direct contact with the second transparent conductive layer through the third hole;

Wherein the first common signal pad and the two adjacent data lines have different minimum distances respectively,

wherein the first hole and the second hole have an overlapping area in a bottom view direction of the substrate,

wherein in the overlapping area, the first common signal line is in direct contact with the first common signal pad, and the first common signal pad is in direct contact with the first transparent conductive layer;

Wherein the second common signal line and the third common signal line are arranged in the display area and are arranged alternately with the data lines, and the second common signal pad and the third common signal pad are arranged in the display area and The second common signal line and the third common signal line are respectively electrically connected; wherein in the extending direction, the second common signal pad is located between the first common signal pad and the third common signal pad, And the distance between the first common signal pad and the second common signal pad is not equal to the distance between the second common signal pad and the third common signal pad.

2 . The display panel of claim 1 , wherein the first hole partially overlaps the second hole, and an edge of the first metal layer is located in the second hole. 3 .

3 . The display panel of claim 1 , wherein the first common signal line comprises a protruding portion located at a position intersecting with the data lines and protruding toward a length direction of the data lines. 4 .

4 . The display panel of claim 1 , wherein at the first hole, an included angle between the first metal layer and the second metal layer is greater than 0 degrees and less than 45 degrees. 5 .

5. The display panel of claim 1, wherein the first common signal pad has a first edge and a second edge, the first edge is opposite to the second edge, and the data lines comprise a a first data line and a second data line, wherein the first common signal pad is located between the first data line and the second data line, the first data line is relatively adjacent to the first edge, and the second data line The line is relatively adjacent to the second edge; wherein, the minimum distances between the first data line and the first edge and the second data line and the second edge in the extending direction of the scan lines are respectively a first distance and a second distance, and when the width of the pixel units in the extending direction of the scan lines is 300-320 μm, the difference between the first distance and the second distance is 1.5-299 μm.

6. The display panel of claim 1, wherein the first common signal pad has a first edge and a second edge, the first edge is opposite to the second edge, and the data lines comprise a a first data line and a second data line, wherein the first common signal pad is located between the first data line and the second data line, the first data line is relatively adjacent to the first edge, and the second data line The line is relatively adjacent to the second edge; wherein, the minimum distances between the first data line and the first edge and the second data line and the second edge in the extending direction of the scan lines are respectively a first distance and a second distance, and when the width of the pixel units in the extending direction of the scan lines is 200-220 μm, the difference between the first distance and the second distance is 1.5-196.17 μm.

7. The display panel of claim 1, wherein the first common signal pad has a first edge and a second edge, the first edge is opposite to the second edge, and the data lines comprise a a first data line and a second data line, wherein the first common signal pad is located between the first data line and the second data line, the first data line is relatively adjacent to the first edge, and the second data line The line is relatively adjacent to the second edge; wherein, the minimum distances between the first data line and the first edge and the second data line and the second edge in the extending direction of the scan lines are respectively a first distance and a second distance, and when the width of the pixel units in the extending direction of the scan lines is 145-165 μm, the difference between the first distance and the second distance is 1.5-144.75 μm.

8 . The display panel of claim 1 , wherein the first common signal pad has a first edge and a second edge, the first edge is opposite to the second edge, and the data lines comprise a a first data line and a second data line, wherein the first common signal pad is located between the first data line and the second data line, the first data line is relatively adjacent to the first edge, and the second data line The line is relatively adjacent to the second edge; wherein, the minimum distances between the first data line and the first edge and the second data line and the second edge in the extending direction of the scan lines are respectively a first distance and a second distance, and when the width of the pixel units in the extending direction of the scan lines is 100-120 μm, the difference between the first distance and the second distance is 1.5-93.33 μm.

9 . The display panel according to claim 5 , wherein the first common signal pad further has a third edge, and two ends of the third edge are respectively connected with the first edge and the first edge. 10 . The two edges intersect; wherein, the third edge is parallel to the extending direction of the scan lines.