CN106847896A - Groove-shaped super junction and its manufacture method - Google Patents

Abstract

The invention discloses a trench-type super junction, comprising: a plurality of trenches, each trench is filled with a first epitaxial layer of a second conductivity type, and the first epitaxial layer tends to completely fill the trench with the smallest volume , the grooves not completely filled by the first epitaxial layer are also filled with the second epitaxial layer, and the second epitaxial layer is stacked on the surface of the first epitaxial layer and completely fills each groove. The second epitaxial layer is undoped or doped with a second conductivity type whose doping concentration is lower than that of the first epitaxial layer, and the doping of the second epitaxial layer and the first epitaxial layer is different so that the total doping of the second conductivity type thin layer The amount is determined by the first epitaxial layer, so as to reduce the influence of the volume difference of each trench on the breakdown voltage of the super junction, thereby improving the in-plane uniformity of the breakdown voltage of the super junction. The invention also discloses a method for manufacturing the trench type super junction. The invention can improve the in-plane uniformity of the breakdown voltage of the super junction, has simple technology, and has important significance for the mass production of the super junction technology platform.

Description

Trench type super junction and manufacturing method thereof

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench super junction; the invention also relates to a method for manufacturing the trench super junction.

Background technique

The super junction is composed of alternately arranged P-type thin layers (also called P-type pillars) and N-type thin layers (also called N-type pillars) formed in a semiconductor substrate, and the matching is completed by using P-type thin layers and N-type thin layers The formed depletion layer supports the reverse withstand voltage while maintaining a small on-resistance.

The pillar structure of the PN interval of the super junction is the biggest feature of the super junction. Currently, there are mainly two methods for manufacturing the pillar structure of the PN spacer, one is obtained by multiple epitaxy and ion implantation, and the other is made by deep trench etching and epitaxy (EPI) filling. The latter method is the manufacturing method of trench-type super junction. This method is to manufacture super junction devices through trench technology. It is necessary to etch a certain amount on the N-type doped epitaxial layer on the surface of a semiconductor substrate such as a silicon substrate. The depth and width of the groove, and then use the epitaxial filling (EPIFilling) method to fill the etched groove with P-type doped silicon epitaxy. In the etching of trenches, the morphology of trenches in different regions of the same semiconductor substrate is not exactly the same, and the reverse breakdown voltage of super junction devices is greatly affected by the morphology of trenches, making the same crystal The uniformity of the reverse breakdown voltage of the superjunction device on the circle is poor.

Contents of the invention

The technical problem to be solved by the present invention is to provide a trench type super junction, which can improve the in-plane uniformity of the reverse breakdown voltage of the super junction device. To this end, the present invention also provides a method for manufacturing a trench-type super junction.

In order to solve the above technical problems, the trench type super junction provided by the present invention includes:

A plurality of grooves formed in the epitaxial layer of the first conductivity type, the epitaxial layer of the first conductivity type is formed on the surface of the semiconductor substrate, each of the grooves is formed by the same photolithographic etching process, and each of the grooves There are errors caused by the photolithography process in the opening size and side slope angle of the grooves, and the error of the opening size and the side slope angle of each groove makes the difference between the grooves in the same semiconductor substrate plane. There are volume differences.

Each of the trenches is filled with a first epitaxial layer of the second conductivity type, the first epitaxial layer of each of the trenches is formed at the same time, and the first epitaxial layer tends to completely fill the trench with the smallest volume Filling, the grooves not completely filled by the first epitaxial layer are also filled with a second epitaxial layer, the second epitaxial layer is superimposed on the surface of the first epitaxial layer and each of the grooves completely filled.

The second conductivity type thin layer is composed of the first epitaxial layer and the second epitaxial layer filled in each of the trenches, and the second conductivity type epitaxial layer is formed between each of the trenches. A conductive type thin layer, which is composed of the first conductive type thin layer and the second conductive type thin layer arranged alternately to form a super junction.

The second epitaxial layer is undoped or doped with a second conductivity type with a doping concentration lower than that of the first epitaxial layer, and the doping of the second epitaxial layer and the first epitaxial layer is different so that the The total doping amount of the thin layer of the second conductivity type is determined by the first epitaxial layer, thereby reducing the influence of the volume difference of each trench on the breakdown voltage of the super junction, thereby making the breakdown of the super junction The in-plane uniformity of the voltage is improved.

A further improvement is that the semiconductor substrate is a silicon substrate, and the epitaxial layer of the first conductivity type, the first epitaxial layer and the second epitaxial layer are all silicon epitaxial layers.

A further improvement is that the error of the opening size and side slope angle of each of the grooves causes volume differences among the grooves in the same semiconductor substrate plane, and the maximum volume difference is 1%-20%.

A further improvement is that the first epitaxial layer tends to completely fill the trench with the smallest volume, so that the first epitaxial layer fills 70% to 100% of the volume of the trench with the smallest volume.

A further improvement is that the first epitaxial layer completely fills the trench with the smallest volume.

A further improvement is that the first conductivity type is N type, and the second conductivity type is P type; the semiconductor substrate is heavily doped with N type.

A further improvement is that the first conductivity type is P-type, and the second conductivity type is N-type.

In order to solve the above-mentioned technical problems, the manufacturing method of the trench type super junction provided by the present invention includes the following steps:

Step 1: Provide a semiconductor substrate, and an epitaxial layer of the first conductivity type is formed on the surface of the semiconductor substrate.

Step 2: Etching the epitaxial layer of the first conductivity type using a photolithography process to form a plurality of grooves; the opening size and side slope angle of each groove are caused by the photolithography process Errors, the errors of the opening size of each of the grooves and the angle of inclination of the side surface cause volume differences among the grooves in the same semiconductor substrate plane.

Step 3, filling the trench with an epitaxial layer, and the epitaxial layer filling process includes:

Step 31 , performing the first epitaxial filling to fill each trench with a first epitaxial layer of the second conductivity type, and the first epitaxial layer tends to completely fill the trench with the smallest volume.

Step 32, performing a second epitaxial filling to fill the grooves not completely filled by the first epitaxial layer with a second epitaxial layer, the second epitaxial layer superimposed on the surface of the first epitaxial layer and Each of the trenches is completely filled.

The second conductivity type thin layer is composed of the first epitaxial layer and the second epitaxial layer filled in each of the trenches, and the second conductivity type epitaxial layer is formed between each of the trenches. A conductive type thin layer, which is composed of the first conductive type thin layer and the second conductive type thin layer arranged alternately to form a super junction.

The second epitaxial layer is undoped or doped with a second conductivity type with a doping concentration lower than that of the first epitaxial layer, and the doping of the second epitaxial layer and the first epitaxial layer is different so that the The total doping amount of the thin layer of the second conductivity type is determined by the first epitaxial layer, thereby reducing the influence of the volume difference of each trench on the breakdown voltage of the super junction, thereby making the breakdown of the super junction The in-plane uniformity of the voltage is improved.

A further improvement is that the semiconductor substrate is a silicon substrate, and the epitaxial layer of the first conductivity type, the first epitaxial layer and the second epitaxial layer are all silicon epitaxial layers.

A further improvement is that the error of the opening size and side slope angle of each of the grooves causes volume differences among the grooves in the same semiconductor substrate plane, and the maximum volume difference is 1%-20%.

A further improvement is that the first epitaxial layer tends to completely fill the trench with the smallest volume, so that the first epitaxial layer fills 70% to 100% of the volume of the trench with the smallest volume.

A further improvement is that the first epitaxial layer completely fills the trench with the smallest volume.

A further improvement is that the first epitaxial filling in step 31 and the second epitaxial filling in step 32 are performed continuously, and the difference between the second epitaxial filling and the first epitaxial filling is that In the second epitaxial filling, the doping gas of the second conductivity type is closed or the flow rate of the doping gas of the second conductivity type is reduced.

A further improvement is that after step 32 is completed, it also includes performing a chemical mechanical polishing process (CMP), and the chemical mechanical polishing process removes the second epitaxial layer on the surface of the first conductivity type epitaxial layer outside each of the grooves. and the first epitaxial layer are removed.

A further improvement is that the first conductivity type is N type, and the second conductivity type is P type; the semiconductor substrate is heavily doped with N type.

A further improvement is that the first conductivity type is P-type, and the second conductivity type is N-type.

The present invention sets the epitaxial layer filled in the trench, wherein the first epitaxial layer tends to completely fill the trench with the smallest volume, and the second epitaxial layer completely fills the unfilled trench. The difference in the doping concentration of the second epitaxial layer and the second epitaxial layer makes the total doping amount of the second conductivity type thin layer determined by the first epitaxial layer, thereby reducing the influence of the volume difference of each trench on the breakdown voltage of the super junction so that The in-plane uniformity of the breakdown voltage of the superjunction is improved.

The present invention only needs to adjust the doping concentration of the first epitaxial layer and the second epitaxial layer to improve the in-plane uniformity of the breakdown voltage of the super junction, and the first epitaxial layer and the second epitaxial layer can realize continuous epitaxial growth , it can be realized only after the first epitaxial layer tends to completely fill the trench with the smallest volume and then turn off or reduce the flow of dopant gas, so the process of the present invention is simple, and it is suitable for the mass production of the super junction process platform has important meaning.

In addition, the distribution of the volume difference of the grooves caused by the error of the photolithography and etching process is not easy to be counted in the actual process, that is, the grooves with large volume are not necessarily fixed in one area, and the grooves with small volume are not necessarily fixed in one area. Fixed in another area, so the distribution of various volumes of the groove is complicated. In the present invention, by using the first epitaxial layer to determine the total doping amount of the second conductivity type thin layer, the influence of the volume difference of the trench on the total doping amount of the second conductivity type thin layer can be eliminated. Moreover, the first epitaxial layer of the present invention The growth thickness of an epitaxial layer is only set according to the groove with a small volume and has nothing to do with the volume distribution of the groove. The present invention can realize precise control and the process is simple and stable.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

FIG. 1 is a schematic structural diagram of an existing trench superjunction;

FIG. 2A is a schematic structural view of a P-type column with a smaller volume in an existing trench-type super junction;

FIG. 2B is a schematic structural diagram of a larger volume region of a P-type column in an existing trench-type super junction;

Fig. 3 is a schematic diagram of a breakdown voltage shift caused by a process mismatch of an existing trench-type super junction;

FIG. 4A is a schematic structural diagram of a region with a smaller volume of a P-type column in a trench-type super junction according to an embodiment of the present invention;

FIG. 4B is a schematic structural view of a region with a larger volume of a P-type column in a trench-type super junction according to an embodiment of the present invention;

5 is a schematic diagram of a breakdown voltage shift caused by a process mismatch of a trench-type super junction according to an embodiment of the present invention;

FIG. 6A is a schematic structural view of a P-type column with a smaller volume after the first epitaxial filling in the method for manufacturing a trench-type super junction according to an embodiment of the present invention;

FIG. 6B is a schematic structural view of the larger volume region of the P-type column after the first epitaxial filling in the manufacturing method of the trench-type super junction according to the embodiment of the present invention.

detailed description

Before describing the embodiments of the present invention, the influence of process mismatch on the breakdown voltage of existing trench-type super junction devices is introduced first:

As shown in FIG. 1 , it is a structural schematic diagram of an existing trench-type super junction; an N-type epitaxial layer 102 is formed on the surface of an N-type semiconductor substrate such as a silicon substrate 101, and multiple N-type epitaxial layers are formed in the N-type epitaxial layer 102 grooves and each groove is filled with a P-type epitaxial layer 103, and the P-type epitaxial layer 103 filled in each groove forms a P-type thin layer, that is, a P-type column 103, and the P-type thin layer 103 between each The N-type epitaxial layer 102 forms an N-type thin layer. The structure shown in FIG. 1 shows that the super junction is composed of multiple alternately arranged N-type thin layers and P-type thin layers 103 . FIG. 1 shows an alternate arrangement structure of multiple N-type thin layers and P-type thin layers 103 .

When making a super junction device by deep trench etching and filling process scheme, because the reverse breakdown voltage of the device matches the total doping amount of the P-type region, that is, the P-type thin layer 103, and the N-type region, that is, the N-type thin layer is very sensitive, so precise control of the total amount of doping in the two regions is critical. However, in the actual process, due to the in-plane differences in the size and angle of the trench opening caused by photolithography and etching, it is always difficult to achieve the best match between the P-type region and the N-type region in the plane at the same time, resulting in Poor reverse breakdown voltage in-plane distribution. That is, in the actual process, the grooves of the P-type thin layer 103 are formed by a photolithography process, and the photolithography process has certain errors, so that the dimensions of the grooves at different regions of the same semiconductor substrate 101 For example, the width and side inclination of the grooves will be different, so that the volume of each P-type thin layer 103 will be different. As shown in Figure 2A, it is a schematic diagram of the structure of the P-type column in the existing trench super junction with a smaller volume; as shown in Figure 2B, it is the larger volume of the P-type column in the existing trench super junction 2A and 2B, it can be seen that the volume of the P-type thin layer 103a is smaller than the volume of the P-type thin layer 103b.

For the sake of convenience, the volume change of the P-type column caused by the opening size of the trench defined by the photolithography process, that is, the width and angle, is analyzed in the CD change. In a general process, a 10% difference in the volume of the P-type region due to the opening size of the deep trench and the inclination angle of the deep trench is a relatively common performance. After normalizing to the impact of CD, for example, for a deep trench with a CD of 4 μm , the in-plane difference is about 0.4 μm.

When there is a 10% difference in the deep grooves on the silicon substrate 101 of the same wafer (wafer) that is a wafer structure, for PN matching, PN matching is a P-type thin layer and an N-type thin layer. The matching of the P-type and N-type impurities in the layer, because the volume of the P region increases by 10% while the volume of the N region will shrink by 10%, so the matching difference is about 20%. Assuming that the in-plane uniformity of the epitaxial filling (EPI Filling) is well controlled, then according to the matching quadratic curve, as shown in Figure 3, the reverse breakdown voltages of the two regions, that is, the regions with larger and smaller volumes of P-type columns, are very different. The big differences are explained below:

The abscissa in Fig. 3 is the process mismatch normalized to the CD size, and the ordinate is the breakdown voltage. The curve of the mismatch change, since the doping concentration of the N-type epitaxial layer 102 corresponds to the resistivity, the doping concentration is now described by the resistivity, the resistivity of the curve 201 is 1.5ohm cm, and the resistivity of the curve 202 is 1.2ohm cm, the resistivity of curve 203 is 1.0 ohm·cm, it can be seen that curves 201, 202 and 203 have similar structures. Now take the doping concentration of the N-type epitaxial layer 102 as 1.2ohm-cm, that is, the curve 202, and the step (Pitch) is 9 μm as an example. The step is the sum of the width and pitch of the trench. When the larger trench region is in The BV of the best match is about 750V, and at this time the BV of the smaller groove area is still about 400V, and the in-plane Range is more than 300V, that is, the circle corresponding to the mark 204 is a larger groove and this place is set to the maximum The best match, the circle corresponding to the mark 205 is a smaller groove, because the larger groove is the best match, so there will be about -20% process mismatch at the smaller groove, so the breakdown voltage will be reduced . And if the circle corresponding to the mark 204 is set as a smaller trench area and the smaller trench area is set as the best match and its breakdown voltage reaches 750V, then the larger trench area will have about + With a 20% process mismatch, the total P-type doping in the larger trench region would be too rich, and the BV would have dropped to about 500V. Therefore, it is difficult to improve the in-plane uniformity of the breakdown voltage of the existing trench-type super junction, and it is basically not manufacturable. In order to improve the in-plane uniformity, the applicant has made the following improvements: firstly, the in-plane distribution difference of the deep trench morphology is studied, and then the in-plane uniformity of the deep trench volume is improved by actively controlling the lithography CD compensation, so as to improve the device The purpose of breakdown voltage in-plane uniformity. However, the scope of application of this method is limited, and good results can be achieved only when the regional distribution is simple; for complex in-plane distribution, it is necessary to accurately grasp the in-plane distribution, and active compensation is very difficult to achieve accurately, and the improvement is not only difficult to control, but also It is difficult to be stable, and the effect of improving the in-plane uniformity of the breakdown voltage is not obvious.

As shown in Figure 4A, it is a schematic structural diagram of the smaller volume area of the P-type column in the trenched super junction according to the embodiment of the present invention; as shown in Figure 4B, it is the P-type column in the trenched super junction according to the embodiment of the present invention Schematic diagram of the structure of the larger volume region; the embodiment of the present invention trench type super junction includes:

A plurality of grooves formed in the epitaxial layer 2 of the first conductivity type, the epitaxial layer 2 of the first conductivity type is formed on the surface of the semiconductor substrate 1, each of the grooves is formed by the same photolithographic etching process, each of There are errors caused by the photolithography process in the opening size and side slope angle of the grooves, and the errors in the opening size and side slope angle of each groove make each of the same semiconductor substrate 1 surface There are volume differences between the trenches. Mark 3a in FIG. 4A represents the groove with the smallest volume, and mark 3b in FIG. 4B represents the groove with larger volume.

Each of the trenches is filled with a first epitaxial layer 4a of the second conductivity type, and the first epitaxial layer 4a of each of the trenches is formed simultaneously, and the first epitaxial layer 4a forms the smallest volume of the trench 3a tends to be completely filled, and the groove 3b that is not completely filled by the first epitaxial layer 4a is also filled with a second epitaxial layer 4b, and the second epitaxial layer 4b is superimposed on the first epitaxial layer 4a surface and completely fill each of the grooves.

The second conductivity type thin layer is composed of the first epitaxial layer 4a and the second epitaxial layer 4b filled in each of the grooves, and the first conductivity type epitaxial layer between each of the grooves 2 forming thin layers of the first conductivity type, where the thin layers of the first conductivity type and the thin layers of the second conductivity type are alternately arranged to form a super junction.

The second epitaxial layer 4b is not doped or doped with a second conductivity type with a doping concentration lower than that of the first epitaxial layer 4a, and the doping of the second epitaxial layer 4b and the first epitaxial layer 4a The difference makes the total doping amount of the thin layer of the second conductivity type determined by the first epitaxial layer 4a, thereby reducing the influence of the volume difference of each trench on the breakdown voltage of the super junction so that the The in-plane uniformity of the breakdown voltage of the superjunction is improved.

In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate, and the first conductivity type epitaxial layer 2, the first epitaxial layer 4a and the second epitaxial layer 4b are all silicon epitaxial layers.

Errors in the opening size and side inclination angle of each of the trenches lead to volume differences between the trenches in the same semiconductor substrate 1 plane; according to different process levels, the maximum volume difference is 1% to 1%. 20%; in the embodiment of the present invention, the volume difference with a maximum value of 10% is used for illustration.

The first epitaxial layer 4 a tends to completely fill the trench with the smallest volume, and the first epitaxial layer 4 a fills up 70% to 100% of the volume of the trench with the smallest volume. Preferably, the first epitaxial layer 4 a completely fills the trench with the smallest volume.

In the embodiment of the present invention, the first conductivity type is N type, and the second conductivity type is P type; the semiconductor substrate 1 is heavily doped with N type. In other embodiments, it can also be: the first conductivity type is P type, and the second conductivity type is N type.

The method for manufacturing a trench-type super junction according to an embodiment of the present invention is characterized in that it includes the following steps:

Step 1, as shown in FIG. 6A , a semiconductor substrate 1 is provided, and an epitaxial layer 2 of the first conductivity type is formed on the surface of the semiconductor substrate 1 . Preferably, the semiconductor substrate 1 is a silicon substrate, and the epitaxial layer 2 of the first conductivity type,

Step 2: Etching the epitaxial layer 2 of the first conductivity type by a photolithography process to form a plurality of grooves; the opening size and side slope angle of each groove are caused by the photolithography process. The error of the opening size of each groove and the error of the slope angle of the side surface make there are volume differences among the grooves in the same semiconductor substrate plane. Mark 3a in FIG. 6A represents the groove with the smallest volume, and mark 3b in FIG. 6B represents the groove with larger volume. In the method of the embodiment of the present invention, the error of the opening size and the side slope angle of each of the grooves causes a volume difference between the grooves in the same semiconductor substrate surface 1, and the maximum volume difference is 1%~ 20%. In the method of the embodiment of the present invention, a volume difference of 10% is used for illustration.

Preferably, before performing photolithography, a step of forming a hard mask layer 5 on the surface of the semiconductor substrate 1 is also included, and the hard mask layer 5 is silicon oxide or silicon nitride. After the trench region is defined by photolithography, the hard mask layer 5 is etched first, and then the epitaxial layer 2 of the first conductivity type at the bottom is etched.

Step 3, filling the trench with an epitaxial layer, and the epitaxial layer filling process includes:

Step 31 , performing the first epitaxial filling to fill each trench with the first epitaxial layer 4 a of the second conductivity type, and the first epitaxial layer 4 a tends to completely fill the trench 3 a with the smallest volume.

Step 32, performing a second epitaxial filling and filling the trench 3b not completely filled by the first epitaxial layer 4a with the second epitaxial layer 4b, the second epitaxial layer 4b superimposed on the first epitaxial layer 4a and completely fill each of the grooves.

Preferably, both the first epitaxial layer 4a and the second epitaxial layer 4b are silicon epitaxial layers.

The first epitaxial filling in step 31 and the second epitaxial filling in step 32 are performed continuously, and the difference between the second epitaxial filling and the first epitaxial filling is that in the second During the epitaxial filling, the doping gas of the second conductivity type is closed or the flow rate of the dopant gas of the second conductivity type is reduced.

The first epitaxial layer 4 a tends to completely fill the trench with the smallest volume, and the first epitaxial layer 4 a fills up 70% to 100% of the volume of the trench with the smallest volume. Preferably, the first epitaxial layer 4 a completely fills the trench with the smallest volume.

The second conductivity type thin layer is composed of the first epitaxial layer 4a and the second epitaxial layer 4b filled in each of the grooves, and the first conductivity type epitaxial layer between each of the grooves 2 forming thin layers of the first conductivity type, where the thin layers of the first conductivity type and the thin layers of the second conductivity type are alternately arranged to form a super junction.

The second epitaxial layer 4b is not doped or doped with a second conductivity type with a doping concentration lower than that of the first epitaxial layer 4a, and the doping of the second epitaxial layer 4b and the first epitaxial layer 4a The difference makes the total doping amount of the thin layer of the second conductivity type determined by the first epitaxial layer 4a, thereby reducing the influence of the volume difference of each trench on the breakdown voltage of the super junction so that the The in-plane uniformity of the breakdown voltage of the superjunction is improved.

After that, it also includes performing a chemical mechanical polishing process. The chemical mechanical polishing process will remove the second epitaxial layer 4b and the first epitaxial layer 4a on the surface of the first conductivity type epitaxial layer 2 outside each of the trenches. Both are removed.

In the method of the embodiment of the present invention, the first conductivity type is N type, and the second conductivity type is P type; the semiconductor substrate 1 is heavily doped with N type. In other embodiments, the method can also be: the first conductivity type is P-type, and the second conductivity type is N-type.

In the embodiment of the present invention, the epitaxial filling process of the first epitaxial layer 4a and the second epitaxial layer 4b is completely continuous, which can be realized only by reducing or closing the flow of dopant gas after filling for a certain period of time. That is, it can be realized by reducing or closing the flow of doping gas after the epitaxial growth reaches the required thickness of the first epitaxial layer 4a, that is, the embodiment of the present invention realizes the overall doping of each P-type thin layer based on time Concentration instead of controlling the overall doping concentration of each P-type thin layer through the volume of the groove, that is, the embodiment of the present invention realizes that the total doping amount of each P-type thin layer has nothing to do with the volume of each groove, and successfully gets rid of the The impact of the volume difference of deep trenches brought about by corrosion on the total doping amount of P-type columns can eliminate the influence of the volume difference of each trench on the BV of the device, that is, the breakdown voltage, so that the embodiments of the present invention can be used without increasing In the case of any process difficulty, the in-plane uniformity of BV can be greatly improved, which is of great significance for the mass production of the super junction process platform.

The method of the embodiment of the present invention is completely based on the current mature epitaxial (EPI) filling process. It is only necessary to divide the EPI filling process into two stages. An epitaxial layer 4a, the second stage, that is, the second epitaxial filling is P-type EPI filling with no doping or very light doping, that is, filling the second epitaxial layer 4b. It is ideal for the boundary point of the two stages to be just filled with the smaller trench (Trench) in the plane, and better results can be achieved slightly earlier or later. When the first stage is completed, the filling conditions of the smaller and larger trenches in the plane are shown in Figure 6A and Figure 6B, respectively.

In the second stage, it is filled with P-type EPI without or very lightly doped. Since the position of the smaller Trench has been filled at this time, only P-type EPI will be deposited on the surface, and the larger Trench will continue to be filled with undoped P-type EPI, that is, the second epitaxial layer 4b, until it is filled. . Afterwards, CMP surface planarization is carried out uniformly, and the cross-sections of the two regions after the second stage is completed are shown in Fig. 4A and Fig. 4B.

In the embodiment of the present invention, the total doping amount of the P-type region, that is, the P-type thin layer, is completely controlled based on the filling time of the first stage (the time when the smaller region has just been filled is the best), instead of being completely controlled by Trench to determine the volume. In the embodiment of the present invention, no matter how the Trench volume changes in the plane, the total doping amount in the P-type pillars is always consistent. Compared with the scheme of using photolithography CD to actively correct in advance, the improvement of the uniformity of the total doping amount of the P-type columns in the embodiment of the present invention is completely self-aligned, that is, the embodiment of the present invention does not need to use a photolithography process to remove Determine the volume difference of the P-type columns, no matter how the volume of the P-type columns is distributed in the plane, the method of the embodiment of the present invention only needs to control the filling time of the first stage to achieve the in-plane uniformity of the total doping amount of the P-type columns performance improvement, so the embodiment of the present invention is completely self-aligned; just because the embodiment of the present invention is completely self-aligned, the embodiment of the present invention does not need complex precise control at all, thereby greatly improving the producibility of the process sex. Most importantly, the method of the embodiment of the present invention does not bring any increase in process difficulty and process cost, and only needs to turn off the dopant gas at a certain correct time point.

As shown in Figure 5, it is a schematic diagram of the breakdown voltage shift caused by the process mismatch of the trench super junction according to the embodiment of the present invention; as in Figure 3, the abscissa in Figure 5 is normalized to the CD size The process mismatch, the ordinate is the breakdown voltage, and the curves 301, 302 and 303 correspond to the curves of the breakdown voltage of the N-type epitaxial layer 2 with different doping concentrations and the variation of the process mismatch, because the N-type epitaxial layer 2 The doping concentration corresponds to the resistivity. The doping concentration is now described by resistivity. The resistivity of curve 301 is 1.5ohm cm, the resistivity of curve 302 is 1.2ohm cm, and the resistivity of curve 303 is 1.0ohm cm , it can be seen that the curves 301, 302 and 303 have a similar structure. Now take the doping concentration of the N-type epitaxial layer 2 as 1.2ohm-cm, which is the doping concentration corresponding to the curve 302, and the step (Pitch) is 9 μm as an example to illustrate: since the P-Pillar is the total doping amount in the P-type column The plane is completely consistent. Therefore, the reason for the PN mismatch, that is, the mismatch between the P-type doping and the N-type doping of the P-type thin layer and the N-type thin layer, is only the P-type region, that is, the N-type region caused by the increase of the P-type thin layer. The shrinkage of the N-type thin layer, because the size of the P region is generally smaller than the N region, when the process level is still 10%, the mismatch of the in-plane device is less than 10%, that is, the process mismatch will be less than 10%, and now There is a process mismatch of about 20% in the method. The range of process mismatch is circled by the dotted box 304 in FIG. 5 . From the curve 302 in FIG. 5 , it can be seen that the worst BV is still above 650V under a single matching concentration. It can be seen that the embodiment of the present invention has a very significant effect on improving the reverse breakdown voltage BV.

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (16)

1. A trench type super junction, characterized in that, comprising: A plurality of grooves formed in the epitaxial layer of the first conductivity type, the epitaxial layer of the first conductivity type is formed on the surface of the semiconductor substrate, each of the grooves is formed by the same photolithographic etching process, and each of the grooves There are errors caused by the photolithography process in the opening size and side slope angle of the grooves, and the error of the opening size and the side slope angle of each groove makes the difference between the grooves in the same semiconductor substrate plane. There is a volume difference; Each of the trenches is filled with a first epitaxial layer of the second conductivity type, the first epitaxial layer of each of the trenches is formed at the same time, and the first epitaxial layer tends to completely fill the trench with the smallest volume Filling, the grooves not completely filled by the first epitaxial layer are also filled with a second epitaxial layer, the second epitaxial layer is superimposed on the surface of the first epitaxial layer and each of the grooves completely filled; The second conductivity type thin layer is composed of the first epitaxial layer and the second epitaxial layer filled in each of the trenches, and the second conductivity type epitaxial layer is formed between each of the trenches. A conductive type thin layer, which is composed of the first conductive type thin layer and the second conductive type thin layer arranged alternately to form a super junction; The second epitaxial layer is undoped or doped with a second conductivity type with a doping concentration lower than that of the first epitaxial layer, and the doping of the second epitaxial layer and the first epitaxial layer is different so that the The total doping amount of the thin layer of the second conductivity type is determined by the first epitaxial layer, thereby reducing the influence of the volume difference of each trench on the breakdown voltage of the super junction, thereby making the breakdown of the super junction The in-plane uniformity of the voltage is improved. 2. The trench type super junction according to claim 1, characterized in that: the semiconductor substrate is a silicon substrate, the first conductivity type epitaxial layer, the first epitaxial layer and the second epitaxial layer The layers are all silicon epitaxial layers. 3. The trench type super junction as claimed in claim 1 or 2, characterized in that: the error of the opening size of each trench and the angle of inclination of the side surface makes the difference between the trenches in the same semiconductor substrate plane There is a volume difference between them, and the maximum volume difference is 1% to 20%. 4. The trench-type super junction according to claim 3, characterized in that: the first epitaxial layer tends to completely fill the trench with the smallest volume, and the first epitaxial layer tends to completely fill all the trenches with the smallest volume. 70% to 100% of the volume of the trench is filled. 5. The trench-type super junction according to claim 4, wherein the first epitaxial layer completely fills the trench with the smallest volume. 6. The trench-type super junction according to claim 1 or 2, characterized in that: the first conductivity type is N-type, the second conductivity type is P-type; the semiconductor substrate is heavily doped with N-type. 7. The trench-type super junction according to claim 1 or 2, wherein the first conductivity type is P-type, and the second conductivity type is N-type. 8. A method for manufacturing a trench-type super junction, comprising the steps of: Step 1, providing a semiconductor substrate, an epitaxial layer of the first conductivity type is formed on the surface of the semiconductor substrate; Step 2: Etching the epitaxial layer of the first conductivity type by a photolithography process to form a plurality of grooves; the opening size and side slope angle of each groove are caused by the photolithography process error, the error of the opening size of each of the grooves and the inclination angle of the side surface makes there is a volume difference between the grooves in the same semiconductor substrate plane; Step 3, filling the trench with an epitaxial layer, and the epitaxial layer filling process includes: Step 31, performing the first epitaxial filling to fill each trench with a first epitaxial layer of the second conductivity type, and the first epitaxial layer tends to completely fill the trench with the smallest volume; Step 32, performing a second epitaxial filling to fill the grooves not completely filled by the first epitaxial layer with a second epitaxial layer, the second epitaxial layer superimposed on the surface of the first epitaxial layer and each of said trenches is completely filled; The second conductivity type thin layer is composed of the first epitaxial layer and the second epitaxial layer filled in each of the trenches, and the second conductivity type epitaxial layer is formed between each of the trenches. A conductive type thin layer, which is composed of the first conductive type thin layer and the second conductive type thin layer arranged alternately to form a super junction; The second epitaxial layer is undoped or doped with a second conductivity type with a doping concentration lower than that of the first epitaxial layer, and the doping of the second epitaxial layer and the first epitaxial layer is different so that the The total doping amount of the thin layer of the second conductivity type is determined by the first epitaxial layer, thereby reducing the influence of the volume difference of each trench on the breakdown voltage of the super junction, thereby making the breakdown of the super junction The in-plane uniformity of the voltage is improved. 9. The method for manufacturing a trench-type super junction according to claim 8, characterized in that: the semiconductor substrate is a silicon substrate, the first conductivity type epitaxial layer, the first epitaxial layer and the The second epitaxial layers are all silicon epitaxial layers. 10. The method for manufacturing a trench-type super junction as claimed in claim 8 or 9, characterized in that: the error of the opening size and side slope angle of each trench makes each of the trenches in the same semiconductor substrate plane There is a volume difference between the grooves and the maximum volume difference is 1%-20%. 11. The method for manufacturing a trench-type super junction as claimed in claim 10, characterized in that: the first epitaxial layer tends to completely fill the trench with the smallest volume, which is the volume of the first epitaxial layer. 70%-100% of the volume of the smallest groove is filled. 12 . The method for manufacturing a trench-type super junction according to claim 11 , wherein the first epitaxial layer completely fills the trench with the smallest volume. 13 . 13. The method for manufacturing a trench-type super junction according to claim 8 or 9, characterized in that: the first epitaxial filling in step 31 and the second epitaxial filling in step 32 are performed continuously, and the The difference between the second epitaxial filling and the first epitaxial filling is that in the second epitaxial filling, the doping gas of the second conductivity type is closed or the flow rate of the doping gas of the second conductivity type is reduced . 14. The manufacturing method of trench type super junction as claimed in claim 8 or 9, characterized in that: after step 32 is completed, it also includes performing a chemical mechanical polishing process, and the chemical mechanical polishing process removes the Both the second epitaxial layer and the first epitaxial layer on the surface of the first conductivity type epitaxial layer are removed. 15. The method for manufacturing a trench-type super junction as claimed in claim 8 or 9, characterized in that: the first conductivity type is N-type, the second conductivity type is P-type; the semiconductor substrate is N-type heavily doped miscellaneous. 16. The method for manufacturing a trench-type super junction according to claim 8 or 9, wherein the first conductivity type is P-type, and the second conductivity type is N-type.